JPH0846222A - Injection silicon resonance tunneling diode and its preparation - Google Patents

Abstract

PURPOSE: To manufacture a resonance tunneling element with a standard silicon treatment process by forming a second tunneling barrier that is separated from a first tunneling barrier and forming a quantum well between the first and second tunneling barriers. CONSTITUTION: A resonance tunneling diode 400 has a silicon anode 402, a silicon dioxide tunneling barrier 404, a silicon quantum well 406, and an oxide tunneling barrier 408. Also, it has a mesa structure 430 consisting of a lamination of the tunneling barriers 404 and 408 and the quantum well 406. The tunneling barriers 404 and 408 become approximately 2 nm in thickness containing each transition layer and become a region of approximately 10 μm×20 μ. The quantum well 406 is as thick as approximately 4 nm and the thickness of the barriers 406 and 408 mainly affect a tunneling current intensity but does not influence a resonance level obtained by the width of a quantum well and the height of the barriers.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electronic devices, and more particularly to resonant tunneling devices and systems and methods of making the same.

[0002]

2. Description of the Related Art As a result of the continuous demand for higher performance transistors and integrated circuits, silicon bipolar and CM
Improvements have been made to existing devices such as OS transistors and gallium arsenide MOSEFT, as well as the introduction of new types of devices and materials. In particular, by reducing the size of the device and improving high frequency performance, such as carrier tunneling phenomenon passing through the potential barrier,
Quantum mechanical effects have also been observed. This has led to the development of device structures that replace conventional ones, such as resonant tunneling diodes, and resonant tunneling thermionic transistors that utilize such tunneling phenomena.

A resonant tunneling diode has a negative differential resistance due to conduction carriers passing through a potential barrier.
It is a two-terminal element that produces a current-voltage curve having a portion exhibiting al resistance). The basic Esaki diode is a band-to-band tunneling phenomenon (eg, from conduction band to valence band) in a heavily doped PN junction.
Remember that you had. Another resonant tunneling diode structure is based on the resonant tunneling phenomenon through quantum wells within a single band. AlGaAs
See FIG. 1, which shows a / GaAs quantum well. In addition, Mars et al, "Renewable Growth and Application of AlAs / GaAs Double Barrier Resonance Tunneling Diodes" (11J.Vac.Sci.Tech.B965 (1993)), and Ozby et al. ), "110-GHz monolithic resonance-tunneling-diode trigger circuit" (12 IEEE Ele
c. Dev. Lett. 480 (1991)) forms a quantum well resonant tunneling diode using two AlAs tunneling barriers, each embedded in a GaAs structure. The quantum well thickness can be 4.5 nanometers (nm) and the tunneling barrier thickness can be 1.7 nm. FIG. 2 shows current-voltage behavior at room temperature. Note that such resonant tunneling "diodes" are symmetrical. With the bias shown in FIG. 3, the discrete electron level
Since the te electron level (bottom edge of the sub-band) is aligned with the edge of the cathode conduction band, the electron tunneling phenomenon easily occurs and the current becomes large. On the contrary, when the bias shown in FIG. 4 is used, the cathode conduction band is matched between the quantum well levels and the tunneling phenomenon is suppressed, so that the current becomes small.

III-like AlGaAs and GaAs
Attempts to create quantum wells in silicon-based semiconductors other than Group V semiconductors have focused primarily on silicon-germanium alloys. For example, the second conference on remarkable silicon-based heterogeneous structures (Topic Con
conference on Silicon-Based Heterostructures II) (1
In 1992 Chicago, Grutzmacher et al.
cher et al) “Very narrow SiGe / Si deposited by chemical vapor deposition at low temperature and atmospheric pressure” (J.Vac.Sci.Tech.B).
1083 (1993) (1 nm wide Si _0.75 Ge _0.25 well with 10 nm wide Si tunneling barrier), and Sedgwick et al, "Atmospheric pressure chemical vapor deposition" (1
1 J.Vac.Sci.Tech.B 1124 (1993) (5 nm wide silicon tunneling barrier and 6 nm wide Si _0.75 Ge _0.25)
Selectively grown Si / SiGe resonant tunneling diode with oxide well)
Was included in the paper. At the SiGe / Si interface, the valence band offset greatly exceeds the conduction band offset, so most researchers think that the strained layer
Ned layer) Hole tunneling, not electron tunneling using SiGe.

However, the SiGe strained layer has a significant intrinsic obstacle of small band discontinuity (less than 500 meV). Therefore, a large peak-to-valley current difference (greater than about 5) occurs, so that operation at room temperature cannot be performed. In addition, the addition of strained heterogeneous junctions and the new material germanium requires the development and implementation of new low temperature manufacturing methods to enable manufacturing, which is not desirable.

Tsu, US Pat.
No. 16,262, describes a silicon-based quantum well structure with a tunneling barrier made of a short-period silicon / silicon dioxide superlattice of a single-layer, two-thick epitaxial silicon dioxide. ing.

Since the silicon / silicon oxide interface is the basis of the performance of CMOS transistor structures, which currently occupy the majority of silicon integrated circuits, many researchers are investigating this. Growth and analysis of oxide monolayers is no longer uncommon. For example, Ohmi et al. “Ultra-thin oxide ultra-thin film on silicon surface by ultra-clean oxidation” (60 Appl.Phys.Let
2126 (1992)), Hattori's "Thin SiO.
High-Resolution X-ray Photoemission Spectroscopy Spectroscopy of ₂ and Si / SiO ₂ Interface ”(11 J. Vac. Sci. Tech. B 1
528 (1993), and Siple et al., "Si (I observed by scanning tunneling microscopy.
II) High temperature oxidation and etching of 7x7 surface "(11 J.
There is Vac.Sci.Tech.A 1649 (1993). In Ohmi et al.'S paper, an oxide monolayer formed on a silicon wafer at 300 ° C. was described by Frenk-Pool for oxide thin films.
It has been observed to form a better oxide film basis than standard thermal oxides for el-Poole) emission.

[0008]

The present invention provides a silicon-based resonant tunneling diode and transistor using at least one injected dielectric tunneling barrier.

The present invention has technical advantages, including the ability to fabricate resonant tunneling devices with standard silicon processing steps.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference is generally made to FIG. 5 and FIG.
FIG. 3 is a cross-sectional view and a plan view of a resonant tunneling diode according to the first preferred embodiment shown in FIG. 1, showing a silicon anode 402, a silicon dioxide (“oxide”) tunneling barrier 404, a silicon quantum well 406. , Oxide tunneling barrier 408, silicon cathode 410, anode metal contact 422, and cathode metal contact 420. The plan view of FIG. 6 shows tunneling barriers 404/408 and quantum wells 406.
Shows a mesa structure 430 of a stack of. The tunneling barriers 404/408 are each about 2 nm thick including the transition layer (generally amorphous with 8 molecular layers) and about 10 μm.
x20 μm region (hence, FIGS. 5 and 6).
Is not based on actual size 0). The quantum well 406 has a thickness of about 4 nm. It is pointed out that the thickness of the barriers 404/408 mainly affects the tunneling current strength, but not the resonance level obtained by the width of the quantum well and the height of the barrier. Also, the exact electronic and chemical properties of the tunneling barrier vary within the barrier.

A wave packe that describes electrons at a periodic potential (ie, electrons in the single crystal silicon of anode 402, quantum well 406, or cathode 410).
The spread of t) is, roughly speaking, the inverse of the spread of the waveform vectors that make up the wave packet. Thus, for small wave vector diffusions compared to the dimensions of the Brillouin zone (which is required for any resonances with respect to the wave vector), the wave packet diffusion can be a cryst of many crystals.
al primitie cells). The diffusion of wave packets in silicon is at least about 4 nm greater than seven simple cells.

The width of the quantum well 406 of 4 nm is such that the edge of the lowest conduction sub-band is about 20 meV, 85 meV more than the edge of the conduction band due to the quantized component of the crystal momentum in the quantum well. , 200 meV, and 350 meV above. The conduction band offset at the silicon / oxide interface is about 2.9 eV for very thin oxides
(For 3.2 eV for thick oxide), FIGS. 7-9 show band diagrams of electron conduction through diode 400. In FIG. 7, no current is generated at zero bias. In FIG. 8, the diode 400 has about 100
The first resonant peak current occurs when biased at mV. In FIG. 9, about 150 mV is applied to the diode 400.
When biased at, the first valley current occurs. It should be pointed out that the anode 402 is n + doped except for a few nm which is in contact with the barrier 404, while the cathode 410 is also doped n + except for a few nm which is adjacent to the barrier 408. Separating the doped region from the tunneling barrier avoids the dopant atoms merging into the tunneling barrier and the interstitial region and causing the impurity assisted tunneling phenomenon. By using a doped anode and cathode, most of the bias applied between the anode and cathode appears between the barrier and the quantum well. Since the dielectric constant of silicon is about three times that of oxide, the voltage drop applied is roughly 1/3 for the oxide barrier, 1/3 for the quantum well, and 1/3 for oxidation. It is divided into an undoped anode and cathode that adjoin the material barrier. The breakdown voltage of oxides is
Since it is on the order of 10 MV / cm, in order to avoid a breakdown current that can destroy the oxide barrier, depletion on the cathode side of the tunnel barrier should be ignored and the breakdown voltage should be less than about 3 volts between full duplex barriers. I have to hold back.

The tunneling barrier 404/408 is formed by oxygen ion implantation. Since this oxygen ion implantation can accurately control the oxygen amount, the thickness of the barrier can also be accurately controlled. The thinness of the silicon-oxide interface depends on the segregation of oxygen in the oxide as opposed to the variation in silicon.

Thus, the diode 400 is capable of producing resonant tunneling phenomena and operating at room temperature in systems using only standard integrated circuit materials, namely silicon and oxide.

Manufacture FIGS. 10 to 13 show a first method of manufacturing the diode 400.
An embodiment is shown in cross-section and comprises the following steps.

(1) A silicon wafer 6 having a thickness of 25 mils and a diameter of about 10 cm and oriented in the (100) direction.
00 is prepared. By decomposing dichlorosilane using stibine (SbH ₃ ) for in-situ doping of antimony, n-thickness of 1 μm thick silicon 602 is deposited on the wafer 600 in the LPCVD (Low Pressure Chemical Vapor Deposition) reactor.
The + layer is epitaxially grown. The flow of stibine was stopped before the dichlorosilane and the upper portion of layer 602 (about 5
It should be pointed out that it is possible to minimize the doping to 0 to 60 nm). Then, a 100 nm thick oxide layer 604 is grown on layer 602. This consumes about 45 nm of layer 602 with minimal doping and about 10 nm of oxide 6 adjacent silicon.
04 remains. Referring to FIG. 10, this doping minimized sublayer is shown at 606. It should be pointed out that the oxide 604 serves only as a hard implant mask and that any other suitable material such as silicon nitride or titanium-tungsten may be used instead. Moreover, because the diode 400 has a mesa structure, a hard mask is actually only needed to protect other areas of the wafer during diode fabrication.

(2) Spin on the photoresist to form a pattern defining an opening of about 15 μm × 25 μm. Next, using the patterned photoresist as an etching mask, the exposed oxide 604 is etched using a HF / NH ₄ F solution. Etching with HF / NH ₄ F and washing with water stabilizes the oxide-free silicon surface by forming a monohydride surface layer. The isotropic nature of this etching is not a problem since the dimensions of the openings are not very precise. Next, the photoresist is removed with acetone, and the surface of silicon is stabilized by washing again with HF / NH ₄ F and water.

(3) The wafer 600 was inserted into an ion implanter (high vacuum), 1 KeV, and the dose was about 1 × 10 ¹⁶ atoms /
Implant oxygen at cm ² and at a wafer temperature of about 600 ° C. When the wafer 600 is tilted by about 7 degrees in order to limit the channeling, the projected range (pro) of oxygen atoms is
jected range is about 2.2nm, projection straggle (proje
The cted struggle is about 1.6 nm, and the transverse struggle is slightly larger, about 1.8 nm.
Becomes Implantation (imp
A continuous anneal during lantation is ensured so that the upper surface of the silicon is single crystal. Referring to FIG. 11, the implanted oxygen is shown in region 610. Since implantation allows control of the amount of oxygen, the tunneling barrier can be formed to the target thickness without the necessary process control in the preferred embodiment without implantation.

(4) Anneal the wafer 600 at 1200 ° C. in an inert atmosphere for 1 hour. During the anneal, the implanted oxygen separates into a buried oxide layer centered at the implanted oxygen peak concentration position 2.2 nm below the surface.
If 90% of the oxygen were separated into this oxide layer, the thickness of the oxide layer would be about 2 nm and finally the diode 40
A zero tunneling barrier 408 is formed. It should be pointed out that some oxygen, in the form of SiO, is lost by evaporation from the surface. The resulting annealed structure has about 1 nm thick single crystal silicon on a 2 nm thick oxide. Also, this oxide is on single crystal silicon. As an alternative, a high-speed (10 seconds) thermal annealing process (1400 ° C. or higher) is performed.
By using g) good oxygen separation and a high quality silicon-oxide interface can be ensured. Also, because the antimony dopant has low diffusivity, it can be kept away from the tunneling barrier. If the dopant penetrates the tunneling barrier, defect-assisted tunneling will occur and the resonance acuity of the resonant tunneling will be lost.

(5) This 1 nm thick silicon is the second
Wafer 600 is too thin to support the growth of the oxide tunneling barrier of Si.
Grow approximately 6 nm of epitaxial silicon from Cl ₄ and H ₂ . If this reaction is performed at 900 ° C, it will be about 15 nm.
Only silicon grows at a rate of / min. In fact, the anneal of step (3) is performed with S for epitaxial growth.
It can also be done in a CVD reactor before the iCl ₄ injection. Epitaxial growth also deposits polysilicon on oxide 604. Referring to FIG. 12, a 2 nm thick oxygen-implanted oxide 618, 7 is formed on the oxide 604.
nm single crystal silicon 624 and polysilicon 62
6 is shown. After epitaxial growth, HF / N
Clean the wafer 600 with H ₄ F and water to remove silicon 624
Stabilizes the surface of. It should be pointed out that the rate of epitaxial growth is controllable, and by controlling the concentrations of chloride and hydrogen, the reaction can be reversed to etch silicon. Recall that the overall reaction is:

[Equation 1] By controlling the gas used, the reaction can proceed in either direction.

(6) As described in step (3), 1
KeV, a dose of about 1 × 10 ¹⁶ atoms / cm ² , and a wafer temperature of about 600 ° C. were repeatedly injected with oxygen, and the peak oxygen concentration was at about 2.2 nm in silicon 624.
An oxygen rich region is formed. Next, the annealing in step (4) is repeated to separate oxygen into the oxide layer 614. The oxide layer 614 has a thickness of about 2 nm and is centered about 2.2 nm below the silicon surface. Therefore, oxide 6
14 will divide the silicon 624 into a silicon top layer 612 about 1 nm thick and a silicon layer 616 about 4 nm thick between the oxygen-implanted oxide layers 614 and 618. FIG. 13 also shows oxygen-implanted oxide in polysilicon 626. In this way,
Two oxide tunneling barriers 614 and 616 are formed, the thickness of which is controlled by the oxygen implantation amount, and the thickness of the silicon quantum well in these tunneling barriers is
It is controlled by slow epitaxial growth.

(7) The epitaxial silicon growth in step (5) is repeated, but a thickness of 50 is formed on the silicon 614.
The growth is continued until an 0 nm silicon layer is grown and an n-type dopant (antimony with stibine) is added in situ. Next, the photoresist is spun on and patterned so as to define a region of 10 μm × 20 μm in the center of the mesa of the tunneling barriers 614 to 618 and the quantum well 616. Then, plasma etching is performed using fluorocarbon to remove both the oxide and the polysilicon, thereby forming a mesa including the tunneling barrier and the quantum well as shown in FIGS. 5 and 6. It should be pointed out that a short thermal oxidation treatment may be performed to form passivation on the sidewalls of the mesas.

Alternative Fabrication Method According to the Embodiment Using Implant The fabrication method of the diode 400 according to the second embodiment differs from the steps (1) to (3) of the first preferred embodiment except that the implantation energy is about 3 KeV. ) Start from. this is,
The peak density is about 6 nm below the surface and the projection straggle is about 5 nm. Again, the high temperature anneal separates oxygen into an oxide layer about 2 nm thick centered about 6 nm below the surface. Since the struggle is much larger than in the first preferred embodiment, either increase the annealing temperature or
Alternatively, it is necessary to lengthen the annealing time. The resulting silicon on the oxide layer will be about 5 nm thick.

Next, an oxide layer having a thickness of 2 nm is grown on the surface of silicon as follows. First HF / N
Wafer 600 is cleaned by cleaning in H ₄ F solution to remove about 1.4 nm of native oxide that grows when wafer 600 comes in contact with air, and then cleaning with deoinized water. To clean. The HF / NH ₄ F cleaning stabilizes the oxide-free silicon surface by forming a monohydride surface layer. Next, the wafer 600 is inserted into a furnace, heated to 300 ° C. in an oxygen-free argon atmosphere, and then the wafer 600 is oxidized at 300 ° C. in a moisture-free oxygen atmosphere. This desorbs hydrogen and grows a monolayer of oxide. Then, after the growth of the oxide monolayer, the wafer is heated to a growth temperature of 900 ° C. in an oxygen-free argon atmosphere, and then about 2
nm of oxide is grown.

Finally, deposit a conductor (such as titanium-tungsten) on the top oxide that acts as an anode. Referring to FIG. 14, a silicon wafer 71
0, 2 nm thick tunneling oxide 708, 4 n thick
m silicon quantum well 706, 2 nm thick tunneling oxide 704, and silicon anode 702 are shown. Again, photoresist masking and etching, and cathode contact formation complete the final mesa diode structure. The following example illustrates a method of forming single crystal silicon on oxide 704 for an anode.

Lattice Tunneling Diode FIG. 15 shows a cross-sectional view of a resonant tunneling diode 800 according to the preferred embodiment. The diode 800 is a modification of the diode 400 and includes an upper oxide tunneling barrier 804 having a lattice structure and a silicon anode 80.
2, a silicon quantum well 806, an oxide tunneling barrier 808, a silicon cathode 810, and metal contacts for the anode and cathode. 16-18 show plan views of various lattices possible as tunneling oxide 804. The grating has a period of about 20 nm and a separation of less than about 4 nm as the grating aperture. Diffusion of wave packets that describe electrons in a periodic potential (ie, electrons in the single crystal silicon of anode 802, quantum well 806, or cathode 810) is roughly speaking:
It is the inverse of the spread of the waveform vectors that make up the wave packet. Thus, for small wave vector spreads compared to the dimensions of the Brillouin zone (which is required for any resonances with respect to the wave vector), the wave packet spread spans many crystal simple cells. The diffusion of wave packets in silicon is at least about 4 nm greater than seven simple cells. The diameter of each of the openings in the tunneling barrier oxide 804 may be no more than 4 nm, or smaller. Therefore, the tunneling barrier 804 is
For electrons (wave packets), it appears as if there is no continuous piercable opening.

The diode 800 has a second
It can be manufactured by modifying the preferred embodiment.
The method according to the second preferred embodiment is carried out until the step of growing the second oxide to a thickness of about 4 nm. next,
Insert the wafer into the ion beam lithography machine and
The oxide is removed from the top oxide using a KeV proton beam (hydrogen ions) to form 4 nm diameter openings in a grid pattern as shown in FIGS. 16-18. The ion beam is focused on a spot size of less than 4 nm, and a raster scan is performed on the wafer with this ion beam. It should be pointed out that this beam need not be matched to anything, and any pattern of apertures narrow enough to exclude circles with a diameter of 4 nm can be generated. The low pressure inside the ion beam machine desorbs approximately one layer of SiO-shaped oxide from the top from the areas that are not removed by sputtering. SiO
Redeposition is minimized. In fact, vapor deposition at low pressure results in the loss of nearly a single layer of SiO, and the silicon beneath the sputtered oxide openings is also sputtered away by the formation of water vapor. Due to the low beam energy, crystal damage is less severe and annealing will remove this damage in later temperature cycles. Referring to FIG. 19, the crystal damage represented by the wavy line, the silicon substrate 1010, the oxygen-implanted tunneling barrier 1008, and the silicon quantum well 10 are shown.
06 and a grown oxide tunneling barrier 1004 with openings 1020 is shown.

Next, the wafer was taken out from the ion beam machine, washed again with a cleaning material containing HF / NH ₄ F and water, and natural oxidation grown on the silicon exposed by the openings 1002 of the lattice-shaped oxide 1004 was performed. Remove things. It also removes about 100 nm of oxide 1004, leaving only a tunneling barrier whose thickness is only 2 nm more than desired. Again, a HF / NH ₄ F rinse forms a hydroxide monolayer and stabilizes the oxide-free silicon surface exposed by the oxide 1004 openings. Next, the wafer is subjected to molecular beam epitaxy (MBE).
It is inserted into a growth chamber, hydrogen is desorbed, crystal damage caused by an ion beam is removed by annealing in a short temperature cycle of 800 ° C. or higher, and then undoped epitaxial silicon is grown at 500 ° C. The short high-temperature cycle anneals away residual crystal damage without depositing a large amount of oxide, which is typical for MBE.
In the desorption of the natural oxide by the method, 1000 to 1250 ° C. is used. Epitaxial growth requires oxide openings 1020
Starting on the silicon exposed by, eventually spread laterally across the oxide 1004. Oxide 1004
Continue to grow until the top silicon is 6 nm thick. The growth of doped silicon is then switched on by adding a beam of antimony or arsenic or phosphorus to the silicon beam. Alternatively, the wafer is removed from the MBE system and an epitaxial layer of doped silicon is grown by MOCVD of LPCVD.

After silicon growth, photolithographic patterning and etching is performed to form the mesa structure and deposit contact metal to complete the diode.

Usually, high temperature separation annealing
During the e segregation anneal) the oxygenated oxide is generally lumpy with apparent openings.
It should be pointed out that it becomes a (lumpy) layer, that is, it looks like a lattice oxide 1004. As discussed with respect to the lattice oxide tunneling barrier, the collapsing layer is
If all the openings are small enough to prevent direct electron conduction rather than tunneling, then it will function properly as a tunneling barrier. In fact, the implantation of oxygen is not uniform and promotes biased segregation, which is more efficient and results in a better oxide / silicon interface. In fact, for a crushed layer, the average layer thickness is greater than an equivalent uniform layer, yet the effective tunneling barrier height and thickness are the same.

Double-Injection Tunneling Barrier In the method of manufacturing diode 400 according to the third preferred embodiment, two injections with different energies are performed to avoid quantum well growth. Specifically, also here, about 3.5 KeV
Steps (1) to (3) of the method for manufacturing the diode 400 according to the first embodiment, except that the peak oxygen concentration is positioned about 8 nm below the surface and the projection straggle is set to about 6 nm using the implantation energy of. Follow Next, a rapid thermal annealing process is applied in an inert atmosphere to rapidly raise the temperature in the vicinity of the surface region to 1400 ° C., and oxygen is introduced into the oxide layer having a thickness of 2 nm centered about 8 nm below the surface. To separate. Then, as in step (3) of the first preferred embodiment, oxygen is injected again (dosage of about 1 × 10 ¹⁶ / cm 3).
² and about 1 KeV energy), about 2.2 from the surface
There is a peak oxygen concentration below 1 nm and struggle is about 1.6
constitutes the nm region of oxygen. Then, a rapid thermal anneal again separates the shallow oxygen into the 2 nm thick second oxide layer. This layer is centered about 2 nm below the surface.
This rapid thermal anneal only improves the oxide 8 nm below the surface. This results in approximately 1 nm of single crystal silicon on the double barrier (2 nm oxide tunneling layer on each side of the 4 nm single crystal silicon quantum well) on the substrate. Either epitaxial silicon or another conductor can be deposited on top of this 1 nm silicon to form the anode of the diode.

Third Embodiment FIG. 20 shows a cross-sectional view of a silicon / oxide resonant tunneling diode 1100 according to the third embodiment. The resonant tunneling diode 1100 has a diode 400 in that it has oxide isolation rather than mesa type mesa isolation.
And 800. In fact, the diode 11
00 may be manufactured along the process of either diode 400 or diode 800 and the final mesa etch replaced by thermal oxidation with masking or the formation of isolation oxide 1150 by oxygen implantation. Such thermal oxidation may be combined with or enhanced with an anneal to separate the implanted oxygen into a tunneling barrier. Otherwise, oxide tunneling barriers 1104/1108 and silicon quantum well 11
06 and the silicon anode 1102 and cathode 1110 are either the diode 400 or the diode 800.
Have the same properties as any corresponding part of

Multi-Peak Resonance Expanding the preferred embodiment into a larger number of series quantum wells by simply growing further tunneling barriers and quantum wells on the structure of the preferred embodiment, a resonant tunneling diode with multiple resonant peaks. Can be formed. In fact, by growing a quantum well and a tunneling diode in continuous contact, a superlattice structure similar to the Tu patent cited in the prior art can be obtained.

Applications The diodes of the preferred embodiment can be incorporated into a variety of structures, such as the memory cells shown in FIGS. Specifically, FIG. 21 schematically illustrates a static random access memory (SRAM) cell 1200, coupled to a bit line 1210 by a pass gate 1208 of a silicon field effect transistor controlled by the voltage on word line 1212, It includes resonant tunneling diodes 1202 and 1204 in series (RTD 1202 acts as a load for RTD 1204). The bistability of the node 1206 of the cell 1200 is obtained from the bias voltage Vdd set a little larger than the current valley of each RTD so that one RTD operates in that valley and the other RTD operates with a small bias. . FIG. 22 shows the current-voltage curves for RTDs 1202 to 1204 superimposed on each other.
The TD has the characteristics shown in FIG. Intersection (node 12
The pair for a voltage close to Vdd on 06 (high) and the voltage on node 1206 for a low) show stable series operating points. The cell 1200 can then be brought to the desired stable state by accessing node 1206 via pass gate 1208 with a large drive source that transitions node 1206 high or low. on the other hand,
Node 120 through the pass gate by the sense amplifier
By accessing 6, the state of the cell can be detected without interruption. Of course, if the RTD peak-to-valley ratio is greater than that shown in FIG. 2, stable high and low voltages near Vdd and 0, respectively, can be formed at node 1206.

FIG. 23 is a perspective view of the structure of FIG. 21 using a single silicon field effect transistor and the RTD of the preferred embodiment. By arranging the RTDs in parallel on the drain of the field effect transistor, etching is performed in a mesa shape to define the position of the RTDs, and at the same time,
It should be pointed out that manufacturing is possible.

Modifications and Advantages The preferred embodiment retains one or more features of epitaxial alignment of the anode, cathode, and quantum well layers due to barrier layer openings for epitaxial growth and such resonant tunneling heterostructures. While it can be modified in many ways.

For example, the tunneling barrier and quantum well dimensions and lattice patterns can be varied. Thin tunneling barrier for higher currents,
It is also possible to change the thickness of the tunneling barrier and to change the thickness of the quantum well to adjust the resonance level up and down. The oxide lattice pattern can be varied or irregular (non-periodic), provided that the diameter of the openings is not too large. Inert gas ions such as helium, neon, argon, krypton, or xenon can also be used in ion beam removal of oxides to form the tunneling barrier lattice. These are selectable momentum transfer efficiencies.
Due to ransfer efficiency, high mass ions (l
arger mass ion) and a neutral product for vapor deposition. It is also possible to manufacture a heterojunction bipolar transistor in which a resonant tunneling diode is embedded in an emitter and a silicon-germanium base is used, or a homogeneous junction bipolar transistor in which a resonant tunneling diode is embedded in an emitter.

By implanting oxygen and nitrogen, oxynitride (o
Other tunneling barrier materials such as xynitride) can also be formed. The silicon-germanium compound is
It can be used for substrates or epitaxial growth, or both.

The tunneling barrier oxide by implantation is
The advantage is that a resonant tunneling structure can be obtained with a standard silicon / oxide material system. Further, in transistors and circuits, the resonant tunneling structure has an advantage of increasing the number of logic circuits and memories operating per unit area. For example, when a full-adder circuit is configured using a resonant tunneling bipolar transistor in which the emitter of the conventional bipolar transistor is a resonant tunneling element, the number of transistors is 1/3 that of a normal transistor and the gate delay is 1/3 that of the conventional technique. Decreased to 3.

With respect to the above description, the following items will be further disclosed. (1) A method for manufacturing a resonant tunneling diode, comprising: (a) providing a layer of semiconductor material; (b) injecting a first dose of seeds into the layer; and (c) providing the donor. Separating into a first tunneling barrier located in the layer, and (d) forming a second tunneling barrier in the layer away from the first tunneling barrier, thereby forming the first and second tunneling barriers. Forming a quantum well therebetween. (2) In the first term, (a) the semiconductor material is silicon, (b) the seed is oxygen, and (c) the first.
The method characterized in that the tunneling barrier is silicon oxide. (3) In the first aspect, (a) the formation of the second tunneling barrier in step (d) of (1) is carried out by: A substep of adding a semiconductor material; (ii) a step of injecting a second dose of a second species into the layer; and (iii) a step of separating the second dose into the second tunneling barrier. A method comprising: and. (4) In claim 1, (a) forming the second tunneling barrier of step (d) of claim 1 comprises: (i) substep of implanting a second dose of the second species into the layer; (i
i) substep of separating the second species into the second tunneling barrier. (5) In the fourth item, (a) the second species is oxygen, and (b) the first donation amount and the second donation amount are equal to each other.

(6) A method of manufacturing a resonant tunneling diode, comprising: (a) providing a layer of semiconductor material; (b) injecting a first dose of seed into the layer; and (c) the donation. Separating the quantity into a first tunneling barrier located in the layer, and (d) the first tunneling barrier.
Forming a quantum well between the first and second tunneling barriers by forming a second tunneling barrier on the surface of the layer adjacent to the tunneling barrier, spaced from the first tunneling barrier. A method characterized by comprising. (7) In item 6, (a) the semiconductor material is silicon, (b) the seed is oxygen, and (c) the first.
The method characterized in that the tunneling barrier is made of silicon oxide. (8) In claim 7, (a) the formation of the second tunneling barrier in step (d) of claim 6 is performed by growing silicon oxide on the surface, and then forming terminals on the grown silicon oxide. Forming a. (9) In claim 7, (a) the formation of the second tunneling barrier in step (d) of (6) comprises (i) a substep of growing silicon oxide on the surface, and (ii) the growth. A method of forming at least one opening in the grown silicon oxide; and (iii) epitaxially growing silicon in the at least one opening and on the grown silicon oxide.

(10) (a) a first terminal; (b) a first tunneling barrier adjacent to the first terminal; (c) a quantum well adjacent to the tunneling barrier; and (d) a quantum well. An adjacent second tunneling barrier,
(E) a second terminal adjacent to the second tunneling barrier, and (f) the interface of the first terminal with the first tunneling barrier is the first tunneling barrier of material from the first terminal. A resonant tunneling diode formed by separation into (11) In claim 10, (a) the first terminal is made of silicon, (b) the first tunneling barrier is made of silicon oxide, and (c) the substance is oxygen.
A diode characterized in that. (12) In the tenth item, (a) the interface between the second terminal and the second tunneling barrier is formed by separation of a substance from the first terminal into the first tunneling barrier. A diode to do.

(13) Silicon quantum well (406) and silicon oxide tunneling barrier (404, 408)
Resonant tunneling diode (40
0). The tunneling barrier is characterized by being formed by separating the injected oxygen into an oxide layer.

Citations to Related Applications This patent application is US patent application Ser. No. 08/14, filed Oct. 29, 1993, the same assignee as this application.
It is a partial continuation application of No. 5,267.

[Brief description of drawings]

FIG. 1 is a band diagram of a known resonant tunneling diode.

FIG. 2 is a diagram showing current-voltage characteristics.

FIG. 3 is a band diagram of a known resonant tunneling diode.

FIG. 4 is a band diagram of a known resonant tunneling diode.

FIG. 5 is a cross-sectional view showing a resonant tunneling diode according to a first preferred embodiment.

FIG. 6 is a plan view showing a resonant tunneling diode according to the first preferred embodiment.

FIG. 7 is a band diagram when various biases are applied to the diode of the first preferred embodiment.

FIG. 8 is a band diagram when various biases are applied to the diode of the first preferred embodiment.

FIG. 9 is a band diagram when various biases are applied to the diode of the first preferred embodiment.

FIG. 10 is a sectional view showing a manufacturing step in a manufacturing method according to the first preferred embodiment.

FIG. 11 is a sectional view showing a manufacturing step in a manufacturing method according to the first preferred embodiment.

FIG. 12 is a sectional view showing a manufacturing step in a manufacturing method according to the first preferred embodiment.

FIG. 13 is a sectional view showing a manufacturing step in a manufacturing method according to the first preferred embodiment.

FIG. 14 is a sectional view showing another preferred embodiment.

FIG. 15 is a sectional view showing another preferred embodiment.

FIG. 16 is a view showing a pattern of lattice-shaped tunneling oxide.

FIG. 17 is a view showing a pattern of lattice-shaped tunneling oxide.

FIG. 18 is a view showing a pattern of lattice-shaped tunneling oxide.

FIG. 19 is a sectional view showing a method according to another preferred embodiment.

FIG. 20 is a sectional view showing a diode according to another preferred embodiment.

FIG. 21 is a diagram showing a case where the diode of the preferred embodiment is applied to a memory cell.

22 is a current-voltage characteristic diagram of the embodiment of FIG.

FIG. 23 is a perspective view showing the structure of the embodiment shown in FIG. 21.

[Explanation of symbols]

 400 Resonant Tunneling Diode 402 Silicon Anode 404 Tunneling Barrier 406 Silicon Quantum Well 408 Tunneling Barrier 410 Silicon Cathode 422 Anode Metal Contact 420 Cathode Metal Contact 430 Mesa Structure

Claims (2)

[Claims] 1. A method of manufacturing a resonant tunneling diode, comprising: (a) providing a layer of semiconductor material; (b) injecting a first dose of seed into the layer; (c) the donor. Separating into a first tunneling barrier located in the layer, and (d) forming a second tunneling barrier in the layer away from the first tunneling barrier.
Forming a quantum well between the first and second tunneling barriers. 2. (a) a first terminal; (b) a first tunneling barrier adjacent to the first terminal; (c) a quantum well adjacent to the tunneling barrier; and (d) adjacent to the quantum well. And (e) a second terminal adjacent to the second tunneling barrier, and (f) an interface of the first terminal with the first tunneling barrier is formed from the first terminal. A resonant tunneling diode formed by the separation of a substance into the first tunneling barrier.