JPH0844705A - Digital data encoding device - Google Patents

Abstract

PURPOSE:To decrease the circuit scale of the encoding device which generates digital data to be displayed with a floating point. CONSTITUTION:An exponent part data generating circuit 11 generates exponent part data bm,n from input data Xm,n. On the basis of the exponent part data bm,n a write data shift circuit 13 shifts the input data Xm,n in the low-order bit direction and intermediate data am,n are written in a mantissa part memory 14. The intermediate data am,n read out of this mantissa data memory 14 are further shifted in the low-order bit direction in response to control data cm,n supplied from a shift control circuit and outputted as mantissa data Am,n. Here, the digits of the mantissa part data Am,n are standardized so that the sum of the shift quantity of the write data shift circuit 13 and the shift quantity of a read data shift circuit 17 becomes constant in one block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data coding device for obtaining digital data displayed in floating point by unifying the decimal point positions for every fixed number of data.

[0002]

2. Description of the Related Art In digital audio equipment, various conversion processes such as Fourier transform and cosine transform are applied to audio data so that the audio data can be efficiently recorded on a recording medium. In a signal processing device that performs such conversion processing, a memory that functions as an input / output buffer is provided together with an arithmetic circuit for conversion processing. Then, the data required by the arithmetic circuit is read from the memory and taken into the arithmetic circuit, and the data output from the arithmetic circuit as the arithmetic result is written again in the memory.

Data handled by these arithmetic circuits and memories are generally displayed in floating point in order to prevent deterioration of the S / N ratio and to secure a dynamic range. That is, in the case of data displayed in fixed point, if the decimal point position is fixed to the lower bit, the ratio of the error generated by the calculation becomes large for the data with a small value, and the error becomes noise and is superimposed on the data. S / N
The ratio deteriorates. Also, if the decimal point position is fixed to the upper bits, the data having a large value cannot be represented and the dynamic range is reduced. Therefore, when the data value is small, the decimal point position is set to the high-order bit, and conversely, when the data value is large, the decimal point position is set to the low-order bit.

However, in the case of displaying the data in floating point, it is necessary to store the data separately in the mantissa part and the exponent part. Therefore, a memory for storing each data and its peripheral circuit are required, and the data amount increases. Then, there arises a problem that the circuit scale becomes large. In addition, when performing arithmetic operations on floating-point displayed data, it is necessary to make the decimal point positions of a plurality of data points to be arithmetically coincident with each other, which complicates various arithmetic processing steps and further increases the circuit scale. It has become a factor to increase.

Therefore, the S
The applicant of the present application has proposed Japanese Patent Application No. 5-16393 as an encoding device capable of preventing deterioration of the / N ratio and ensuring a sufficient dynamic range. In this encoding device, continuous data is divided into a plurality of blocks in units of a predetermined number, and the decimal point position of the data is set uniformly for each block.

FIG. 3 is a block diagram showing the structure of an encoding device in which the decimal point position of data is fixed and displayed for each block, and FIG. 4 is a time change of data input to the encoding device. It is a figure which shows an example. Input register 1
Stores the input data X _{m, n} (m block, nth), which is continuously input, for each block including an appropriate number of data. The input data X _{m, n} for one block stored in the input register 1 may be data on the time axis divided at constant time intervals, or may be data on the frequency axis with a predetermined value. The data may be divided for each band. The exponent part data generation circuit 2 receives the input data X for one block stored in the input register 1.
The maximum value of _{m, n} is detected, and the exponent part data B _m designating the decimal point position is generated according to the detected value. This exponent part data B _m is input data X _{m, n} according to the number of bits assigned to the mantissa part of the digital data displayed in floating point.
Is generated so that it can represent the maximum value of. For example, when the mantissa is assigned to 3 bits, the exponent is designated so that a point deviated by 3 bits to the lower side from the most significant bit indicating “1” at the maximum value of the input data X _{m, n} is designated as the decimal point position. Part data B _m is generated. Then, the exponent part data memory 3 stores the exponent part data B _m set for each block in the exponent part data generation circuit 2, and outputs the exponent part data B _m to the circuit of the next stage at a predetermined timing.

In response to an instruction from the exponent part data generation circuit 2, the data shift circuit 4 shifts the input data X _{m, n} read from the input register 1 in the lower bit direction, extracts a specific bit and outputs the mantissa part. Data A _{m, n} is generated. That is, the mantissa data A _{m, n} are input a decimal point position specified by the exponent part data B _m by a predetermined number of bits as the least significant bit data X _m, the input data to retrieve the _n X _{m , n} , correspondingly generated. The mantissa part data memory 5 stores one block of mantissa data A _{m, n} output from the data shift circuit 4, and combines it with the exponent part data B _m from the exponent part data memory 3 at a predetermined timing. Output to the circuit.

In this way, one exponent part data B _m is determined for each block, and 1 is set for a plurality of mantissa part data A _{m, n} .
By associating the individual exponent part data B _m , the amount of data required to represent the same information is greatly reduced. At the same time, the decimal point positions of the data are the same in the same block, and the process of arithmetic processing using these data can be simplified. However, the resolution represented by each data is
It decreases as the number of bits of the exponent part data B _m decreases.

Here, when the 3-bit mantissa data A _{m, n} is to be obtained from the 6-bit input data X _{m, n} , 1
Consider a case where two data are processed as one block. First, it is assumed that 12 pieces of input data X _{1,1 to} X _1,12 as shown in Table 1 are input to the input register 1 in the first period T ₁ . FIG. 4 shows these input data X _{1,1 to} X.
The values of _1,12 are represented on the time axis between times t _1,0 and t _2,0 .

[0010]

[Table 1]

For each input data X _{1,1 to} X _1,12 , the exponent part data generation circuit 2 inputs the input data X _1,11 showing the maximum value.
(= 29), all input data X _{1,1 to} X _1,12 can be represented by 3 bits by shifting each input data X _{1,1 to} X _1,12 by 2 bits in the lower bit direction. Therefore, the exponent part data B ₁ is set to “10” (= 2). The exponent part data B ₁ is stored in the exponent part data memory 3 and at the same time supplied to the data shift circuit 4 as control information. As a result, the data shift circuit 4 shifts each input data X _{1,1 to} X _1,12 by 2 bits in the lower bit direction,
The lower 3 bits are stored in the mantissa data memory 5 as mantissa data A _{1,1 to} A _1,12 .

Similarly, it is assumed that 12 pieces of input data X _{2,1 to} X _2,12 as shown in Table ₂ are input to the input register in the second period T ₂ . FIG. 4 shows these input data X
The values of _{2,1 to} X _2,12 are shown on the time axis between times t _2,0 and t _3,0 .

[0013]

[Table 2]

For each of the input data X _{2,1 to} X _2,12 , the exponent part data generation circuit 2 inputs the input data X _2,9 indicating the maximum value.
From (= 55), the exponent part data B ₂ is set to “11” (= 3). The exponent part data B ₂ is stored in the exponent part data memory 3 and at the same time supplied to the data shift circuit 4 as control information. Then, the data shift circuit 4
Each input data X _{2,1 to} X _2,12 is shifted by 3 bits in the lower bit direction, and the lower 3 bits are converted to mantissa data A _{2,1 to} A.
_The numbers _{2 and 12} are stored in the mantissa data memory 5.

Therefore, 12 for one block in each period T _m
Twelve mantissa data A _{m, n} and one exponent data B _m can be obtained corresponding to the input data X _{m, n} . In this case, one block of 72-bit (6 bits x 12 data) data is converted into 38 bits (3 bits x 12 data).
Data + 2 bits) can be compressed.

[0016]

When the common exponent part data B _m is set for each block, one block of data is stored and the maximum value in the same block is detected from this data. It is necessary. Therefore, the circuit scale of the register 1 that stores the input data X _{m, n} for one block must be increased, which increases the circuit scale of the entire apparatus. In addition, input data for one block X _{m, n}
Is temporarily stored to set the exponent part data B _m and then the mantissa part data A _{m, n} is generated. Therefore, the mantissa part data A _m and the exponent part are input after the input data X _{m, n} is input. It takes a long time to obtain the data B _{m, n} , which makes it difficult to cope with high-speed operation.

Therefore, an object of the present invention is to operate a circuit at high speed while reducing the circuit scale.

[0018]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and its characteristic is that it corresponds to the first digital data displayed in a fixed point continuously input. In the digital data encoding device for obtaining the second digital data represented by the floating point consisting of the mantissa part and the exponent part, the exponent part for designating the decimal point position of each data according to the content indicated by the first digital data. Means for generating data, means for shifting the first digital data in the lower bit direction based on the exponent part data to selectively extract a specific bit to generate intermediate data, and the first digital Corresponding to a first memory circuit that stores the intermediate data extracted from the data for each fixed number of data, and a plurality of the intermediate data stored in the first memory circuit A second memory circuit for storing a plurality of the exponent part data, and the second memory circuit based on a difference between the maximum value of the plurality of exponent part data stored in the second memory circuit and each exponent part data. And a means for generating mantissa data by shifting the intermediate data read from the first memory circuit in the lower bit direction so that one exponent data is associated with a plurality of mantissa data. This is to obtain the second digital data.

[0019]

According to the present invention, since the data is shifted in the writing stage and the reading stage of the intermediate data, it becomes possible to directly generate the exponent data from the input data that is continuously input. At the same time, the intermediate data obtained for each data is stored in the memory circuit as it is. Therefore, when generating the exponent part data, an input register for temporarily storing one block of input data is not required, and the circuit scale is reduced. Since each data is written and read once in the process, the time required to obtain the mantissa data and exponent data after the input data is input is shortened, and the digital data input at high speed is reduced. Will also be able to support.

[0020]

1 is a block diagram showing the configuration of a digital data encoding apparatus according to the present invention, and FIG. 2 is a diagram showing an example of a time change of data input to the encoding apparatus. The exponent part data generation circuit 11 expresses the input data X _{m, n} with the mantissa part data A _{m, n} with respect to the input data X _{m, n} (m block, n-th) that is continuously input. It is determined how many bits should be shifted in the lower bit direction, and the exponent part data b _{m, n} is generated from the determination result. In the exponent part data generation circuit 11, the judgment standard for the input data X _{m, n} is set stepwise, and the input data X _{m, n}
Is set so that the exponent part data b _{m, n} is sequentially increased by "1" every time when exceeds these judgment criteria. At the same time, even if the input data X _{m, n} having a large value is once input and the value of the exponent part data b _{m, n} becomes large, even if the input data X _{m, n} having a small value is input, the exponent part data b _{m, n}
Remains large. The exponent part data generation circuit 11 uses a predetermined number of input data X forming one block.
Each time _{m, n} is input, when the input data X _{m, n} of the next block is newly received, the exponent part data b _{m, n} is set to the minimum value “00” (= 0). .

The input register 12, the input data X _m continuously _inputted, captures _n for each data, the exponent part data b _m of the input data X _m, the _n from the exponent part data generating circuit _{11, n} Output at the timing that matches the output of. The input register 12 is simply the exponent part data generation circuit 11
This is for matching the operation timings of and, and can be omitted. Write data shift circuit 1
3 shifts the input data X _{m, n} in the lower bit direction based on the exponent part data b _{m, n} output from the exponent part data generation circuit 11 to generate the intermediate data a _{m, n} . The mantissa data memory 14 stores the intermediate data a _{m, n} output from the write data shift circuit 13 for each block according to the instruction of the address data supplied from the address generation circuit 15. The exponent part data memory 16 is a mantissa part data memory in which the exponent part data b _{m, n} generated by the exponent part data generation circuit 11 is written with intermediate data a _{m, n} corresponding to each exponent part data b _{m, n.} It is stored together with address data indicating 14 addresses. This exponent part data memory 16
, It is not necessary to store a plurality of exponent part data b _{m, n} having the same value. If the exponent part data b _{m, n} has the same value, the exponent part data b _{m, n} that first indicates that value are stored _. Only _n should be stored. That is, when the exponent part data b _{m, n} gradually increases as the value of the input data X _{m, n} increases, the exponent part data b _{m, n} and the exponent part data b at the timing when the exponent part data b _{m, n} increase. _m, configured to store the address of intermediate data a _m, mantissa data memory _{14 n} are stored corresponding to _n. The read data shift circuit 17 shifts the intermediate data a _{m, n} read from the mantissa data memory 14 in the lower bit direction in response to the control data c _{m, n} generated by the shift control circuit 18,
The mantissa part data is output as A _{m, n} . Shift control circuit 1
8, the number of shift bits of the input data X _{m, n in} the write data shift circuit 13 and the read data shift circuit 1
The control data c _{m, n} is generated so that the sum of the intermediate data a _{m, n in} 7 and the number of shift bits is unified in the same block. As a result, the digits of the mantissa data A _{m, n} output from the read data shift circuit 17 are unified within the same block.

The output register 19 fetches and stores the final value of the plurality of exponent data b _{m, n} stored in the exponent data memory 16 as the exponent data B _m . Then, together with the mantissa data A _{m, n} output from the read data shift circuit 17, the exponent data B _m is output to the circuit of the next stage at a predetermined timing. As a result, one exponent part data B _m is associated with a plurality of mantissa part data A _{m, n} .

As described above, the write data shift circuit 13 is provided on the write side and the read side of the mantissa data memory 14.
By providing the read data shift circuit 17 and the read data shift circuit 17, respectively, the input data X _{m, n} continuously input can be directly stored in the mantissa data memory 14. Therefore, it is not necessary to temporarily store one block of input data X _{m, n} at the input stage, and the circuit scale is reduced. Although the read data shift circuit 17 and the shift control circuit 18 are increased as compared with the conventional encoding device of FIG. 3, the scale of the input register 12 is greatly reduced, and the circuit scale of the entire device is increased. Is reduced. In particular,
When the number of bits of the input data X _{m, n} is large or the number of data of one block is large, the effect of reducing the circuit scale of the input register 12 is great.

Here, when trying to obtain 3-bit mantissa data A _{m, n} for 6-bit input data X _{m, n} , 12 pieces of data are processed as one block, and 12 pieces of data are processed. The case where one exponent part data B _m is associated with the mantissa part data A _{m, n} will be described. First, it is assumed that 12 pieces of input data X _{1,1 to} X _1,12 of the first block as shown in Table 3 are input to the input register 1 in the first period T ₁ . In FIG. 2, these input data X _{1,1 to} X
The values of _1,12 are represented on the time axis between times t _1,0 and t _2,0 .

[0025]

[Table 3]

The exponent part data generation circuit 11 receives each input data X _1,1 for the first three input data X _{1,1 to} X _1,3 .
Since ~ X _1,3 can be represented by 3 bits without shifting, exponent part data b _1,1 is set to “00” (= 0). For the following four input data X _{1,4 to} X _1,7 , each input data X _{1,4 to} X _1,7 can be represented by 3 bits by shifting by 1 bit in the lower bit direction. The copy data b _1,4 is set to “01” (= 1). Each input data X ₁ for five input data X _{l, 8} to X _{1, 12 remain,} 8 ~
Since X _1,12 can be represented by 3 bits by shifting 2 bits in the lower bit direction, the exponent part data b _{1,8 is set} to “1”.
0 ”(= 2). At this time, input data X _1,9
The input data X _1,9 is smaller by one digit, and can be represented by 3 bits by shifting 1 bit to the lower bit side. However, the exponent part data b _1, once set to “10” _{, 9} never returns to "01". This first
In the case where the exponent part data b _{m, n} changes in three steps, as in the block, the three exponent part data b _1,1 , b _1,4 , b
_{1, 8} are stored in the exponent data memory 16 together with the corresponding address data.

In response to the exponent part data b _1,1 , the write data shift circuit 13 takes out the lower 3 bits of the input data X _{1,1 to} X _1,3 without shifting them and outputs the data a _1,1. ~
Outputs a _1,3 . Similarly, each index data b _1,4 ,
In response to b _1,8 , input data X _{1,4 to} X _1,7 are shifted by 1 bit to the lower bit side, and input data X _{1,8 to} X _1,12 are shifted by 2 bits to the lower bit side. And the lower 3 of each
The bits are extracted and the intermediate data a _{1,4 to} a _1,7 and the intermediate data a _{1,8 to} a _1,12 are output. The shift control circuit 18 also controls the control data c _{1,1 to} c _1,3 and c _{1,4 to} c so as to correspond to the exponent part data b _1,1 , b _1,4 and b _{1,8. 1,7} and c _{1,8 to} c _1,12 are “10” (= 2) and “0”, respectively.
1 ”(= 1) and“ 00 ”(= 0) are set. As a result, the read data shift circuit 17 causes the intermediate data a
_{1,1 to} a _1,3 are shifted by 2 bits to the lower bit side, and data a _{1,4 to} a _1,7 are shifted by 1 bit to the lower bit side. As a result, the digits of all the data a _{1,1 to} a _1,12 are unified and output as the mantissa data A _{1,1 to} A _1,12 . Then, the final value of the exponent part data b _{1,1 to} b _1,12 is output as the exponent part data B ₁ .

[0028] Similarly, the input data X _2,1 12 pieces of the second block, as shown in Table 4 in the second period T ₂ to X _{2, 12}
Shall be input to the input register. In FIG. 2, the values of these input data X _{2,1 to} X _2,12 are represented by time t _2,0 to t.
It is shown on the time axis between _3,0 .

[0029]

[Table 4]

The exponent data generating circuit 11, the input data _{X 2,1 ~X 2,2, X 2,3 ~X} 2,5 and X _{2, 6} respectively index with respect to X _{2, 12} part data b _2,1 , b _2,3 and b _2,6 are set to “0
1 ”(= 1),“ 10 ”(= 2) and“ 11 ”(= 3)
And set. These exponential part data b _2,1 , b _2,3 and b
₂ , ₆ , the write data shift circuit 13 receives the input data X _{2,1 to} X _2,2 , X _{2,3 to} X _2,5 and X _{2,6 to} X _2,12 by 1 bit and 2 respectively. Shift by 3 bits and 3 bits toward lower bit. In response to this, shift control 18
Is control data c _{2,1 to} c _2,2 , c _{2,3 to} c _2,5 and c _2,6.
~ C _2,12 are "10" (= 2) and "01" (=
1) and “00” (= 0) are set, and read for receiving these control data c _{2,1 to} c _2,2 , c _{2,3 to} c _2,5 and c _{2,6 to} c _2,12. The data shift circuit 17 shifts the intermediate data a _{2,1 to} a _2,2 and the intermediate data a _{2,3 to} a _2,5 read from the mantissa data memory 14 by 2 bits and 1 bit in the lower bit direction, respectively. _Therefore , the digits of all the intermediate data a _{2,1 to} a _2,12 are unified and the mantissa data A _{2,1 to} A are
Output as _2,12 . At this time, the exponent part data B ₂ is “1” which is the final value of the exponent part data b _2,1 , b _2,3 , b _2,6.
1 ”is output.

Mantissa data A generated in this way
_{The m, n} and the exponent part data B _m coincide with the mantissa part data A _{m, n} and the exponent part data B _m shown in Tables 1 and 2, so that the encoding device shown in FIG. , It is understood that the same encoding process as that of the encoding device shown in FIG. In the above embodiment, the case where 3-bit mantissa data is obtained for 6-bit input data is illustrated, but the number of bits of input data and the number of mantissa data are not limited to this. Even if the number of bits is further increased, the encoding can be performed by the same process. As a matter of course, the number of bits of the exponent part data may be 2 bits or more. Further, it is possible to easily realize that the number of data in one block is 12 or more by changing the operation timing of each unit.

[0032]

According to the present invention, since the data shift circuits are provided on the write side and the read side of the memory for storing the intermediate data, the continuously input data is stored for one block at the input stage. It is no longer necessary, and it is possible to directly determine the mantissa data and the exponent data and obtain the data. Therefore, the circuit scale of the device is reduced, and the size and cost of the device can be reduced. Also, temporarily store one block of input data at the input stage,
Moreover, since it is not necessary to determine the maximum value of the data, the time required for the encoding process of the input data can be shortened, and the input data input at high speed can be dealt with.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital data encoding device of the present invention.

FIG. 2 is a diagram showing an example of a change with time of input data.

FIG. 3 is a block diagram showing a configuration of a conventional digital data encoding device.

FIG. 4 is a diagram showing an example of temporal change of input data.

[Explanation of symbols]

 1, 12 Input Register 2, 11 Exponent Data Generation Circuit 3, 16 Exponent Data Memory 4 Data Shift Circuit 5, 14 Mantissa Data Memory 13 Write Data Shift Circuit 15 Address Generation Circuit 17 Read Data Shift Circuit 18 Shift Control Circuit 19 Output register

Claims (3)

[Claims] 1. A digital data encoding device for obtaining floating-point-displayed second digital data composed of a mantissa part and an exponent part, corresponding to fixed-point-displayed first digital data which is continuously input. A means for generating exponent part data for designating a decimal point position of each data according to the content of the first digital data, and the first digital data is shifted in the lower bit direction based on the exponent part data. Means for selectively extracting a specific bit to generate intermediate data, a first memory circuit for storing the intermediate data extracted from the first digital data for every fixed number of data, and A second memory circuit for storing a plurality of the exponent part data corresponding to the plurality of intermediate data stored in one memory circuit; and a second memory circuit. Based on the difference between the stored maximum value of the exponent part data and each exponent part data, the intermediate data read from the first memory circuit is shifted in the lower bit direction to generate mantissa part data. And a means for associating one exponent part data with a plurality of mantissa part data to obtain the second digital data. 2. A digital data encoding device for obtaining second digital data represented by a floating point consisting of a mantissa part and an exponent part, corresponding to the first digital data represented by a fixed point continuously input. In the above, a judgment criterion is specified in which the decimal point position of each data is designated according to the content indicated by the first digital data that is continuously input, and the content indicated by the first digital data is set stepwise. An exponent part data generation circuit that generates exponent part data that sequentially shifts the designation of the decimal point position by one digit to the upper bit side every time it exceeds
A first shift circuit that shifts the first digital data in the lower bit direction based on the exponent part data to selectively extract specific bits to generate intermediate data; and a first shift circuit that is extracted from the first shift circuit. A first memory circuit for storing the intermediate data for every fixed number of data, an address generating circuit for generating address data for designating a write address and a read address of the first memory circuit, and an exponent part data generating circuit Of a plurality of the exponent part data generated by and the intermediate data corresponding to the exponent part data are stored in association with each other, the address data indicating the address of the first memory circuit.
Memory circuit and the intermediate data read from the first memory circuit based on the difference between the maximum value of the plurality of exponent part data stored in the second memory circuit and each exponent part data sequentially read out. A second shift circuit for generating mantissa data by shifting in the direction of lower bits, wherein a plurality of mantissa data are associated with one exponent data to obtain the second digital data. Digital data encoding device. 3. The first device from which the intermediate data is read out.
7. The exponent part data stored in the second memory circuit in association with the address data designating the address of the second memory circuit is read as shift control information of the second shift circuit. Item 1. The digital data encoding device according to item 1.