JPH08340260A - Code error correction circuit - Google Patents

Abstract

PURPOSE: To reduce a hardware scale and to shorten processing time. CONSTITUTION: A data generator 3 generates 2M pieces of M-bit data, the inspection bits of N bits are added to the M-bit data in an encoding circuit and the block code of (M+N) bits is generated. An error addition circuit 5 generates the random error of P bits to the block code and performs output as an error addition code. In a memory 2, the M-bit data are written with the error addition code as a write address. At the time of performing a decoding processing, the check bits of N bits are added to the transmission data of M bits, a block encoded block code string is received as a reception block code string and a shift register 1 accesses the memory with the block code as a read address for the respective block codes of the reception block code string and reads stored data as error correction data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code error correction circuit used for data communication and correcting a code error generated in a transmission line.

[0002]

2. Description of the Related Art Generally, a decoding circuit for receiving and decoding a block code such as a BCH code is provided with a code error correction circuit. Such block codes (eg BC
When decoding H code), the following method is generally used.

Now, assume that the code polynomial c (X) is sent from the transmitting side. Then, the polynomial e that represents the error pattern
(X) is added, and the receiving polynomial r (X) = c (X) + e
It is assumed that (X) is obtained. First, the syndrome is obtained from r (X), and the error locator polynomial is obtained from the syndrome. After that, the root of the error locator polynomial is obtained, and the error is corrected by this. When performing such error correction, a large number of adders and shift registers are generally required.

[0004]

As described above, when performing error correction in the block code decoding circuit,
There is a problem that a large number of adders and shift registers are required, which increases the hardware scale. On the other hand, if an attempt is made to perform error correction by software processing, there is a problem in that the processing time becomes long because an extremely large amount of addition processing and data shift processing have to be performed.

An object of the present invention is to provide a code error correction circuit which requires a small hardware scale and can shorten the processing time.

[0006]

According to the present invention, N-bit (N-bit) data is transmitted for M-bit (M is a positive integer) transmission data.
Is a positive integer) and is used in a decoding device that receives a block code string block-coded by adding a check bit of the received block code string and decodes the received block code string,
A memory in which a plurality of predetermined M-bit data different from each other is stored as storage data, and for each block code of the received block code sequence, the block code is used as a read address to access the memory to access the storage data as error correction data It is possible to obtain a code error correction circuit having a reading means for reading as.

The code error correction circuit further includes a data generator for generating 2 ^M M-bit data different from each other, and N (M + N) -bit data by adding N check bits to the M-bit data. An encoding circuit for encoding into a block code, and an error adding circuit for generating a P-bit (P <N) random error with respect to the (M + N) -bit block code and outputting as an error-added code,
The M-bit data is written in the memory using the error addition code as a write address.

The reading means may be, for example, (M +
A switch for connecting the data generator to the memory and the error addition circuit to the memory when writing the M-bit data to the memory. Means are provided, and the switch means is connected to the shift register and to the output terminal when the error correction data is generated.

[0009]

According to the present invention, M-bit data is written in the memory by using the error addition code as the write address, and the memory is accessed by using the block code as the read address for each block code of the received block code string to read the stored data as the error correction data. Therefore, when the code error correction process is performed, the hardware scale is small and the processing time can be shortened.

[0010]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, a code error correction circuit according to the present invention includes a shift register 1, a memory 2, a data generator 3, an encoding circuit 4, an error adding circuit 5, and a switch 6a.
And 6b, the switches 6a and 6c are interlocked.

Now, the block code is represented by the number M of data bits.
(M is a positive integer) and the number of check bits N (N is a positive integer) will be described as having an error correction capability up to P bits (P <N). Note that, here, for the sake of convenience, all the data are assumed to be binary.

When the illustrated code error correction circuit is activated,
The switches 6a and 6b are switched to the a terminal side. The data generator 3 generates all combinations for M-bit codes. That is, 2 ^M data strings are generated. These data strings are sequentially stored in the memory 2 via the switch 6a as described later.

On the other hand, the data string output from the data generator 3 is encoded into a block code by the encoding circuit 4. That is, the data string is encoded into a block code of (M + N) bits. Then, the block code is given to the error adding circuit 5.

The error addition circuit 5 adds an error to a block code of (M + N) bits for all combinations of random errors up to P bits and outputs it as an error addition code. Then, these error addition codes are given to the memory 2 as write addresses via the switch 6b. As a result, the above-mentioned data string is sequentially written in the memory 2 according to the write address.

The above-described processing is performed for one data string
A block code of (M + N) bits is generated, and errors are added to this block code for all combinations of errors up to P bits. Therefore, the same data string is stored at different addresses.

When all the data strings are stored in the memory 2, the switches 6a and 6b are switched to the b terminal side. As a result, the code error correction circuit is ready for decoding,
Received code strings (block code strings) are sequentially input to the shift register 1 (the shift register 1 is a (M + N) -bit shift register). When one block of code is input to the shift register 1, the memory is accessed using the contents of the shift register 1 as a read address. As a result, the stored data string corresponding to this read address is read from the memory 2 as read data.

As described above, since the data string is written in the memory 2 using the error addition code as the write address, the read data described above becomes the error correction data of the received code.

When the generator polynomial is changed, the encoding circuit 4 may be changed. Further, when a plurality of data communications are simultaneously performed using the same code, a shift register and a memory are simply added. It is possible to support a plurality of data communications. If the generator polynomial is invariant, the circuit scale (hardware scale) can be further reduced if the memory is read-only memory (ROM) and the data is written in the ROM in advance by the above-described method.

In the above embodiment, the case where the data is binary has been described, but the present invention can be similarly applied to the multilevel code.

[0021]

As described above, according to the present invention, a plurality of M-bit data different from each other corresponding to a predetermined write address are stored in the memory as storage data, and the blocks of the reception block code string are stored. Since the memory is accessed as the error correction data by accessing the memory using the block code as the read address for each code, the hardware scale is small when performing the code error correction process, and the processing time can be shortened. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a code error correction circuit according to the present invention.

[Explanation of symbols]

 1 shift register 2 memory 3 data generator 4 encoding circuit 5 error addition circuit 6a, 6b switch

Claims (3)

[Claims] 1. A block code string block-coded by adding N-bit (N is a positive integer) check bit to M-bit (M is a positive integer) transmission data as a reception block code string. A memory used in a decoding device that receives the received block code string, stores a plurality of M-bit data different from each other as storage data corresponding to a predetermined write address, and a block of the received block code string. A code error correction circuit comprising: a read unit that accesses the memory by using the block code as a read address for each code and reads the stored data as error correction data. 2. The code error correction circuit according to claim 1, further comprising a data generator that generates 2 ^M M-bit data different from each other and an N-bit check bit for the M-bit data. An encoding circuit for adding and encoding into a block code of (M + N) bits;
P bits (P <N) for N) bit block code
Error-adding circuit for generating a random error and outputting it as an error-adding code, and the M-bit data is written in the memory using the error-adding code as a write address. circuit. 3. The code error correction circuit according to claim 1, wherein the reading means is a (M + N) -bit shift register, and the data generator is stored in the memory when the M-bit data is written in the memory. Switch means for connecting the error addition circuit to the memory is provided, and the switch means is connected to the shift register and the output terminal when the error correction data is generated. A code error correction circuit characterized by the above.