JPH08339345A - Information processing system - Google Patents

Abstract

PURPOSE: To connect a bus adapter capable of split transfer to a system bus without unnecessary degradation of performance by suppressing the succeeding transaction of the bus adapter capable of split transfer, which is in the middle of split read transaction processing, based on a read or write request destination address discriminating means. CONSTITUTION: This information processing system consists of processors 1 and 2, a system controller 3, a bus control means 4, a main storage 5, bus adapters 6 to 9, processor busses 11 and 12, a memory bus 13, a system bus 14, I/O busses 15 to 18, and I/O devices 21 and 22. The bus control means 4 is provided in the system controller 3. The bus control means 4 is provided with the read or write request destination address discriminating means and a means which suppresses the succeeding transaction of the bus adapter capable of split transfer, which is in the middle of split read transaction processing, based on this address discriminating means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system in which information processing devices such as workstations are mutually connected via a system bus, and a split transfer capable of dividing a read access start cycle and a response cycle is provided. The present invention relates to a technique effectively applied to an information processing system having a supporting system bus.

[0002]

2. Description of the Related Art In an information processing system in which information processing devices such as workstations are connected to each other via a system bus, when PIO access, DMA transfer, etc. compete with each other, one I / O device having a slow access time, etc. Of the above module exists on the system, the other bus transaction cannot be issued and is kept waiting due to the slow read access to that one module, which lowers the response and throughput of the system bus. In the following description, a module is a CPU
It refers to functionally integrated hardware such as I / O devices and bus adapters.

Therefore, if a split transfer is supported as a system bus protocol so that another bus master can issue a transaction between a read access start cycle and a response cycle, a slow read access to one module can be performed. It is possible to prevent waiting for other bus transactions that cannot be issued.

In this case, the read data is transferred to the read request issuing source by the module that has received the read request acquiring the bus right and sending it to the bus.

For the above reasons, it is common in information processing systems to employ a system bus that supports split transfer as a system bus to improve the response and throughput of the system bus in the event of transaction conflict. Is coming.

An information processing system that employs a system bus that supports the split transfer is described in, for example, Japanese Patent Application Laid-Open No. 5-233528.

In the information processing system described in the above-mentioned publication (Japanese Patent Laid-Open No. 5-233528), a bus control means capable of simultaneously issuing a plurality of split read requests to a specific bus adapter is provided to process the system bus. It has improved performance.

[0008]

However, as a bus adapter, for example, in order to effectively utilize an existing I / O bus and I / O device, it is possible to accept a subsequent transaction during split read transaction processing. It is assumed that an existing bus adapter that cannot be used is used.

In this specification, a bus adapter capable of accepting a subsequent transaction during split read transaction processing is hereinafter referred to as a bus adapter capable of accepting split transfer, and a bus adapter not capable of accepting the same transaction is split transferred. It is called a bus adapter that cannot be accepted.

The above-mentioned publication (Japanese Patent Laid-Open No. 23352/1993)
In the information processing system described in No. 8), if the specific bus adapter is a bus adapter that cannot accept split transfer, the same bus adapter and the above I
The I / O bus and the I / O device could not be connected to the system bus supporting split transfer.

That is, only under the condition that the number of processors is 1 and the processors do not issue a plurality of split read transactions at the same time, the split transfer cannot be accepted on the system bus supporting the split transfer. Although it was possible to connect a bus adapter, under the conditions other than the above, a subsequent transaction is issued during the split read transaction processing, so the bus described in the above-mentioned publication (JP-A-5-233528). If the control means is connected to the processor via a bus that does not support split transfers,
In a multiprocessor system having a plurality of processors, since a subsequent transaction is issued during the split read transaction processing, there is a problem that the split transfer unacceptable bus adapter cannot be connected to the system bus.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to cause unnecessary performance degradation in an information processing system having a system bus that supports split transfer. It is an object of the present invention to provide a technology that enables a bus adapter that is not capable of split transfer to be connected to a system bus without a need.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0014]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) A system bus that supports split transfer, a bus control unit that is connected to the system bus and performs transaction transmission, transaction acceptance, and arbitration of bus usage right to the system bus, and the system bus. And an information processing system having one or more bus adapters for sending and receiving transactions to and from the system bus, wherein the bus control means can issue a plurality of split read transactions and write transactions. In the information processing system, at least one of the bus adapters is a bus adapter that cannot accept split transfer and cannot accept a subsequent transaction while processing a split read transaction. The bus control unit has a read or write request destination address determination unit, and a unit for suppressing a subsequent transaction to the bus adapter that is incapable of split transfer during processing of a split read transaction based on the address determination unit. Is characterized by.

[0016]

According to the above-mentioned means, the bus control means succeeds after issuing a read transaction to the bus adapter that cannot accept split transfer or the module connected under the same bus adapter based on the determination result of the read or write request destination. Suppress sending of transactions for the same bus adapter or module to the system bus.

Then, after the response to the preceding read request is returned, the subsequent transaction is sent to the system bus and the operation corresponding to the transaction is executed.

When the preceding read request is for a bus adapter capable of accepting split transfer or a module connected under the same bus adapter, the preceding read request is sent on the system bus without waiting for a subsequent transaction. It is sent out and the operation according to the transaction is executed.

As a result, it is possible to connect a bus adapter that is not capable of split transfer to a system bus that supports split transfer, and to operate it without any functional inconvenience, resulting in unnecessary performance degradation on the system bus. It becomes possible to prevent it.

Furthermore, even if there are a plurality of bus adapters that cannot perform split transfer, split transfer is performed on the system bus as long as the read request destination addresses of the preceding read access and the subsequent read access are different. It becomes possible.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a block diagram showing a schematic configuration of an information processing system which is an embodiment of the present invention.

In FIG. 1, 1 and 2 are processors, 3 is a system controller, 4 is a bus control means, 5 is a main memory, 6, 7, 8, and 9 are bus adapters, 11 and 12 are processor buses, and 13 is a memory. Bus, 14 is system bus,
15, 16, 17, 18 are I / O buses, 21, 22 are I
/ O device.

A bus control means 4 is provided in the system controller 3, and the system controller 3 controls an interface between the processors (1, 2), the main memory 5, and the system bus 14.

Further, the processor buses (11, 12) are
The processors (1, 2) and the system controller 3 are connected to each other, and the memory bus 13 connects the main memory 5 and the system controller 3 to each other.

Further, I / O devices (21, 22) are connected to the bus adapters (6, 7, 8, 9) via I / O buses (15, 16, 17, 18), respectively. The adapters (6, 7, 8, 9) connect the system bus 14 and the I / O buses (15, 16, 17, 18), respectively.

Although only two I / O devices (21, 22) are shown in FIG. 1, it goes without saying that a larger number of I / O devices may be connected. 1, the I / O bus (16, 17, 1
The I / O device connected to 8) is omitted.

In the processor (1, 2),
“# 0, #m” is a processor number and indicates that there are a total of (m + 1) processors from “# 0” to “#m”.

The processor buses (11, 12) are
Although shown individually for each processor (1, 2), all the processors (1, 2) and the system controller 3 may be connected to a common processor bus.

Similarly, the bus adapters (6, 7, 8, 9) are also the total (n + 1) from the "# 0" th to the "#n" th.
There are bus adapters.

In the information processing system of this embodiment,
The processor (1, 2) is connected to the processor bus (11, 1
2), read / write access to the main memory 5 can be performed via the system controller 3 and the memory bus 13, and via the processor bus (11, 12), the system controller 3 and the system bus 14, P for I / O devices under the bus adapter (6, 7, 8, 9)
IO read / write access can be performed.

The bus adapter (6, 7, 8, 9) can receive the PIO read / write access from the processor (1, 2) and perform the read / write access to the subordinate I / O device. Further, it is possible to receive a request from the subordinate I / O device and perform a DMA read / write access to the main memory 5 via the system controller 3 and the memory bus 13.

The system bus 14 supports split transfer, and also the processor bus (11, 12).
Does not support split transfers.

Further, for the bus adapters (6, 7, 8, 9) and the following, for convenience of explanation, the bus adapter 6 and the I / O bus 15 and I / O devices (21,
22) does not support split transfer, and the bus adapters (7, 8, 9) and the I / O buses under them, I / O buses
It is assumed that the O device supports split transfer.

Next, read and write transactions on the system bus 14 will be described.

FIG. 2 is a time chart showing an example of a read transaction on the system bus 14 in the information processing system shown in FIG.

FIG. 3 is a time chart showing an example of a write transaction on the system bus 14 in the information processing system shown in FIG.

FIG. 4 is a time chart showing an example of the information processing system shown in FIG. 1 in the case where another transaction enters between the read transaction activation cycle and the response cycle.

In FIGS. 2, 3, and 4, BREQ
(I), BREQ (j), BREQ (k) are bus right request signals, and (i, j, k) indicate the module number on the system bus 14 that is the bus right request source.

BGRT (i), BGRT (j), BGR
T (k) is a bus right permission signal output by the bus control means 4.

LSTCYCL is a signal indicating the last cycle of the bus right grant cycle.

ADR / DATA is an address and data in each transaction.

Information indicating the transaction type is also transferred during the address transfer cycle.

AVALID and DVALID are an address valid signal and a data valid signal, respectively.

The TID indicates the issue of the read or write transaction by the module number on the system bus 14.

TACK is a signal indicating that the request destination of the read or write transaction has accepted the transaction.

In FIG. 2, the left side of the broken line shows the read transaction activation cycle and the right side shows the response cycle.

The read request source is the bus right request signal (BRE
Q (i)) requests the bus right, and the bus control means 4
Grants the bus right by the bus right grant signal (BGRT (i)).

The read request source asserts a signal (LSTCYCL) in the same cycle as the address output, whereby the bus control means 4 releases the system bus 14.

Thereafter, the read request destination requests the bus right by the bus right request signal (BREQ (j)), and the bus control means 4 grants the bus right by the bus right grant signal (BGRT (j)). , The read request destination outputs the read data, and the signal (LSTCYCL) is output in the last cycle of the data.
Assert.

As a result, the bus control means 4 releases the system bus 14.

In FIG. 2, the data output cycle is 4
Although it is a cycle, this is an example and the signal (L
Depending on the position (STCYCL), longer or shorter data output cycles are possible.

In FIG. 3, the write request source requests the bus right by the bus right request signal (BREQ (i)), and the bus control means 4 grants the bus right by the bus right grant signal (BGRT (i)). Then, the write request source outputs the address and the data, and outputs the signal (LSTC in the last cycle of the data.
YCL) is output.

As a result, the bus control means 4 releases the system bus 14.

The length of the data output cycle shown in FIG. 3 is an example, and the length of the data output cycle is the same as in the case of FIG. 2 by the signal (LSTCYCL).
Depending on the position of, longer or shorter data output cycles are possible.

FIG. 4 shows an example of a time chart in which a write transaction is inserted between the read transaction activation cycle and the response cycle, and the individual operations of the read activation cycle and the response cycle and the write transaction. Is the same as the description of FIGS. 2 and 3.

Next, whether or not the bus adapter can accept split transfer will be described.

FIG. 5 is a diagram for explaining the transaction sending / accepting address / data buffer in each module on the system bus 14 in the information processing system shown in FIG.

In FIG. 5, only the bus adapter 6 and the bus adapter 9 are shown to simplify the description.

The system controller 3 has p address / data buffers (101), and once sets the transactions from the processors (1, 2) here, sends them to the system bus 14.

Therefore, it is possible that p transactions are sent to the bus adapter side at the same time.

Further, the bus adapter 6 has an address / data buffer (10) for accepting a transaction.
Since there is only one in 2), only one split transfer request from the system controller 3 having p buffers can be accepted.

Although the number of address / data buffers (102) is one in FIG. 5, if the number is less than p, similarly, only the number of buffers can be accepted.

On the other hand, the bus adapter 9 has p address / data buffers (103) like the system controller 3 and can accept p transactions at the same time.

Therefore, the split transfer request can be accepted.

Next, the bus adapter 6 that cannot accept split transfer and the I / O devices (21, 22) under it
The operation when a read transaction is issued will be described.

In this case, the bus control means 4 operates as follows.

When a read transaction is issued from the processor (1, 2) to the bus adapter 6 or the I / O device (21, 22) under it, the system controller 3 sends this transaction to the system bus 14. After sending, when it is confirmed that the read request has been received, the fact that the read transaction has been issued to the bus adapter 6 is stored.

Thereafter, before the read data from the bus adapter 6 is returned to the system controller 3, a read or write transaction for the bus adapter 6 is issued again from the processor (1, 2) to the system controller. If the bus bus request signal (BREQ (i)) is suppressed, the system bus 14
Transaction is not sent to.

On the other hand, when the above-mentioned second transaction is for another bus adapter (7, 8, 9), the bus right request signal (BR
The transaction is sent to the system bus 14 without suppressing EQ (i)).

FIG. 6 is a diagram showing an example of a concrete circuit configuration of the bus control means 4 in the information processing system shown in FIG.

In FIG. 6, 201 is a compare circuit (comparator), 202 is an address / data buffer input / output pointer control unit (hereinafter referred to as control unit), 203, 204,
207, 209, 210 are AND circuits, 205, 208
Is a flip-flop (hereinafter referred to as FF), 20
6, 211 are selectors.

The compare circuit 201 includes a processor (1,
The address of the read / write transaction from 2) and the comparison address which is the address at the time of read or write access to the bus adapter 6 and the I / O devices (21, 22) under it which cannot accept split transfer. Compare.

Further, the control unit 202 determines the address / data buffer (1) according to the input / output pointer value of the address / data buffer (101) in the system controller 3.
01) write control and read control are performed.

Further, AND (203, 204) are p, which is the same as the number of the address / data buffers (101), but they are shown collectively in the drawing.

In addition, F. F. (205) is the bus adapter 6 that cannot accept split transfer and the I / O under it
This is a flip-flop that indicates that access to the device (21, 22) has occurred.

This F. F. (205) is p, which is the same as the number of address / data buffers (101).
It is set and reset by the ND circuit (203, 204).

That is, the address / data buffer (10
When a transaction is registered in 1), the corresponding F. F. (205) is set, the same transaction is output from the address / data buffer (101),
After being transmitted to the system bus 14, the bus right permission signal (B
It is reset by GRT (i)).

The selector 206 has p. F. (20
It is a selector for selecting and outputting one of 5) according to the output pointer value.

There are (m + 1) ANDs 207 corresponding to the processors (1, 2). F. The set signal of (208) is generated.

F. F. (208) is a flip-line indicating that the read access to the bus adapter 6 that cannot accept split transfer or the I / O devices (21, 22) under it is accepted. This is a flop and is reset when read data is returned from the bus adapter 6 to the system controller 3.

The AND 209 is an (m + 1) AND circuit corresponding to the processors (1, 2) and generates a mask signal for suppressing the BREQ request signal.

The AND circuit 210 is an (m + 2) input AND
The circuit is a circuit, and when even one output of (m + 1) AND209 is asserted, the BREQ request signal is suppressed, the BREQ request signal is asserted, and
The bus right request signal (BREQ (i)) is asserted only when the outputs of the (m + 1) ANDs 209 are all negated.

As described above, the bus adapter 6 that cannot accept split transfer or the I / O device (2
1, 22) when the read access is accepted, F.
F. (208) is turned on, and then the same bus adapter 6 or I / O devices (21, 22) under it
When a read / write access is issued to
In the AND circuit 209, the F. F. (205) output and F. F. By taking the logical product with the output of (208),
It is possible to create a signal that inhibits the transaction transmission to the system bus 14.

FIG. 7 is a time chart showing an example of the operation of the circuit shown in FIG.

In FIG. 7, the BREQ request signal "#"
"0" and "# 1" correspond to the 0th and 1st of the p address / data buffers (101).

F. F. (205) "# 0" and "#
The same applies to "1" and "0 to 2" on the output / input pointer / output pointer line of the compare circuit 201.

The BREQ request signal (# 0) is "#
The bus adapter 6 or the I / O device under it (2
It corresponds to the read request transaction to
The BREQ request signal (# 1) corresponds to a read request transaction from the "# 1" th processor to the bus adapter 6 or the I / O devices (21, 22) under the same that cannot accept split transfer. I shall.

In addition, the F. F. “# 0” and “# 1” in (208) correspond to the processor number of the transaction issuer.

When the read request transaction as described above is issued from the "# 0" th processor while the input pointer and the output pointer both indicate "0", the system controller 3 After accepting the address and data of the transaction in the "0" th address / data buffer (101), the bus control unit 4 issues a BREQ request signal (# 0) and counts up the input pointer to "1". And

At this time, since the read request destination address specifies the bus adapter 6 that cannot accept split transfer or the I / O devices (21, 22) under it,
The addresses match in the address compare circuit 201, and the output of the compare circuit 201 becomes "1", which causes the "0" th address / data buffer (101).
Corresponding to F. F. (205) is set.

Since the output pointer is "0",
The output of the selector 206 is the F.S.C. corresponding to the “0” th address / data buffer (101). F. (205) is selected, the output of the selector 206 becomes "1", and AN
When the AND condition of the D circuit 207 is satisfied, the AND circuit 207
Output becomes "1" and the F.S. F. (208) is set.

Further, BREQ is output to the output of the selector 121.
Since the request signal (# 0) is selected, the BREQ request signal (# 0) is sent to the bus right request signal (BREQ (i)).

Next, the output pointer is counted up by the bus right permission signal (BGRT (i)) and becomes "1".

At this point of time, the read request transaction to the bus adapter 6 that cannot accept split transfer or the I / O devices (21, 22) under it is already issued from the "# 1" th processor.

Therefore, the system controller 3 accepts the address and data of the transaction in the "1" th address / data buffer (101), and then the BREQ request signal (# 1) in the bus control means 4.
Is issued, and the input pointer is counted up to "2".

In this case as well, in the subsequent transaction as well, since the addresses match, the output of the compare circuit 201 becomes "1", and the F corresponding to the "1" th address / data buffer (101). ． F.
(205) is set.

At this time, since the output pointer is "1", the "1" th address /
F.D. corresponding to the data buffer (101). F. (20
5) is selected, and the output of the selector 206 becomes "1".

Therefore, the AND condition of the AND circuit 209 corresponding to the "# 0" th processor is satisfied, and AN
The output of the D circuit 209 becomes "1", the output of the AND circuit 210 becomes "0", and thereafter, the read data return display signal indicating that the read data has been returned from the bus adapter 6 to the system controller 3 is issued. Until it is issued, the bus right request signal (BREQ (i)) is suppressed, and the subsequent transaction is kept waiting.

As described above, according to this embodiment,
A plurality of transactions, for example, a read transaction after a read transaction or a write transaction after a read transaction is issued to the bus adapter 6 or the I / O devices (21, 22) under it that cannot accept split transfer. In this case, the issuance of the bus right request signal (BREQ (i)) is suppressed.

This makes it possible to prevent a plurality of transactions from being issued to the bus adapter 6 or the I / O devices (21, 22) under the bus adapter 6 that cannot accept split transfer with a relatively small amount, and unnecessary performance is required. It is possible to connect a bus adapter with / without split transfer support to the system bus 14 that supports split transfer without causing a decrease.

FIG. 8 is a diagram showing an example of a concrete circuit configuration of the bus control means 4 in the information processing system having two bus adapters which cannot accept split transfer.

In FIG. 8, 201 and 201a are compare circuits (comparators), 202 is a control unit, and 203 and 203.
a, 204, 204a, 207, 207a, 209, 2
09a and 210 are AND circuits, and 205, 205a and 20
8, 208a is a flip-flop, 206, 206
Reference numerals a and 211 are selectors.

In the circuit shown in FIG. 8, the AND circuit (2
03a, 204a, 207a, 209a,) and F.I.
F. (205a, 208a) are the AND circuits (203, 204, 207, 209) shown in FIG. F.
The circuit configuration is similar to (205, 208).

The compare circuit (201, 201a)
As the comparison addresses of the two, the addresses at the time of read or write access to the two bus adapters that cannot accept split transfer and the I / O devices under them are set.

The circuit shown in FIG. 8 has a (2m + 3) input AN.
In the D circuit 210, the BREQ request signal and the output of the AND circuit (209, 209a) are logically ANDed, and a plurality of transactions, for example, a read transaction after the read transaction is performed for each bus adapter that cannot accept the split transfer. , Or when the write transaction after the read transaction is issued, the operation is the same as the circuit shown in FIG. 6 except that the issue of the bus right request signal (BREQ (i)) is suppressed. Therefore, detailed description will be omitted.

If there are three or more bus adapters that cannot accept split transfer, the part (A) enclosed by the dotted line in the circuit shown in FIG. 8 corresponds to a plurality of bus adapters that cannot accept split transfer. It should be installed.

Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0110]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, it is possible to connect either bus adapter to a system bus supporting split transfer regardless of whether split transfer is supported or not. Due to some unsupported bus adapters, it is possible to prevent unnecessary performance degradation that would make split transfer of the entire system bus impossible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an information processing system that is an embodiment of the present invention.

FIG. 2 is a bus 1 in the information processing system shown in FIG.
4 is a time chart showing an example of a read transaction on the No. 4 server.

3 is a time chart showing an example of a write transaction on a system bus 14 in the information processing system shown in FIG.

FIG. 4 is a time chart showing an example of the information processing system shown in FIG. 1 in the case where another transaction enters during a read transaction activation cycle and a response cycle.

5 is a diagram for explaining a transaction sending / accepting address / data buffer in each module on the system bus 14 in the information processing system shown in FIG. 1. FIG.

6 is a diagram showing an example of a specific circuit configuration of a bus control means 4 in the information processing system shown in FIG.

FIG. 7 is a time chart showing an example of the operation of the circuit shown in FIG.

FIG. 8 is a diagram showing an example of a specific circuit configuration of a bus control unit 4 in an information processing system having two bus adapters that cannot accept split transfer.

[Explanation of symbols]

1, 2 ... Processor, 3 ... System controller, 4 ...
Bus control means, 5 ... Main memory, 6, 7, 8, 9 ... Bus adapter, 11, 12 ... Processor bus, 13 ... Memory bus, 14 ... System bus, 15, 16, 17, 18 ... I
/ O bus, 21, 22 ... I / O device, 101, 10
2, 103 ... Address / data buffer, 201, 20
1a ... Compare circuit, 202 ... Address / data buffer input / output pointer control unit, 203, 203a, 204,
204a, 207, 207a, 209, 209a, 21
0 ... AND circuit, 205, 205a, 208, 208a
... flip-flops, 206, 206a, 211 ... selectors.

Claims (1)

[Claims] 1. A system bus that supports split transfer, a bus control unit that is connected to the system bus and that performs transaction transmission, transaction acceptance, and arbitration of bus usage right to the system bus, and is connected to the system bus. An information processing system having one or more bus adapters for sending and receiving transactions to and from a system bus,
The bus control means can issue a plurality of split read transactions and write transactions, and at least one of the bus adapters cannot accept a subsequent transaction during the processing of the split read transaction. In an information processing system including a bus adapter that is not capable of split transfer, the bus control means is based on the read or write request destination address determining means and the address determining means, and the split transfer is not possible while the split read transaction is being processed. An information processing system comprising means for suppressing a subsequent transaction to a bus adapter.