JPH08339175A - Character display device - Google Patents

Abstract

PURPOSE: To always read out correct data with a peripheral circuit held in a miniaturized state, by dividing a storage means into a first and a second storage areas and accessing the first and second storage areas during the first and the remaining second processing period of each machine cycle. CONSTITUTION: A storage area or a storage means 6 is divided into a first storage area storing a program data and a second storage area storing a character data in the same address space. Further, the first and second storage areas of the storage means 6 are made possible to be accessed at different timings during a specified processing period which is a plurally divided period of each machine cycle. Also, a latch circuit 14 is provided which holds a character code of a video RAM 1 at a position where a display character is replaced by another one in the horizontal scanning direction. Consequently, the peripheral circuits are prevented from expanding, and also since the first and second storage areas cannot simultaneously be accessed, correct data can always be read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character display device suitable for use in a so-called closed caption system for displaying characters on a television screen.

[0002]

2. Description of the Related Art Recently, there are many TV receivers and VTRs equipped with a so-called on-screen function for displaying various information such as channel and volume on the screen according to the will of the viewer. The on-screen function is realized by including a video RAM and a character ROM inside the microcomputer. The video RAM stores a character code corresponding to a display character at an address corresponding to a display portion of a television screen, and is accessed according to horizontal scanning of a television signal. Further, the character ROM is configured to store all characters that can be displayed on the television screen in a dot pattern of a specific character font and to be accessed by the character code read from the video RAM.
On-screen display is realized by subjecting the character data read from the character ROM to signal processing for display.

By the way, inside the microcomputer, a ROM storing program data for controlling arithmetic operations and the like and a character ROM storing character data are integrated on a chip independently of each other. .

[0004]

Generally, the above-mentioned R
The OM and the character ROM are integrated using a mask, but when both ROMs are integrated using an EEPROM (electrically erasable memory), two EEs are integrated.
Since the PROM is used, a peripheral circuit for performing address control and the like becomes large, and as a result, there is a problem that the chip itself becomes large.

Therefore, one EEPROM is divided into two address spaces, the program data is stored in one address space, and the character data is stored in the other address space, thereby miniaturizing the peripheral circuit. Techniques are also conceivable. In this case, one address space of the EEPROM is accessed in synchronization with the operating clock of the CPU, and the other address space of the EEPROM is accessed in synchronization with the horizontal scanning of the television signal. That is, the program data and the character data can be asynchronously read from the EEPROM.
However, there is a problem that correct data cannot be read when both address spaces of the EEPROM are accessed in an overlapping manner.

Therefore, according to the present invention, even when one storage means is divided into two storage areas and the program data is stored in one storage area and the character data is stored in the other storage area, An object of the present invention is to provide a character display device that can always read correct data while keeping the peripheral circuit in a miniaturized state.

[0007]

The present invention has been made to solve the above problems, and is characterized in that program data for controlling the operation of a controlled portion is stored. A first storage area and a second storage area in which character data of a predetermined font to be displayed on the display unit is stored; first address means for accessing the first storage area of the storage means; Second address means for accessing the second storage area of the storage means, and in each machine cycle divided into a plurality of processing periods, the first address means stores the first storage of the storage means in the first processing period. Address switching means for permitting access to the area and permitting the second address means to access the second storage area of the storage means during the remaining second processing period; Record Lies in that and a data processing means for causing the character displayed on the display unit processes the character data read out from the area.

[0008]

According to the present invention, the storage means is divided into first and second storage areas, and the first and second storage areas are accessed in the first and remaining second processing periods of each machine cycle. Configured. As a result, the program data can be read from the first storage area of the storage means and the character data can be read from the second storage area of the storage means in a correct state at all times.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a character display device of the present invention. FIG.
In (1) is a video RAM, the character code corresponding to the display character is stored in the address corresponding to the display portion of the TV screen, and the attribute code indicating the modification information such as the color, shape and background color of the display character is It is stored at the address immediately before the character code corresponding to the first display character to be modified. Particularly, when a part or all of the displayed characters are continuously displayed in the same modified state on the TV screen, the video RAM (1) is an address where the character code of the first character whose modified state is changed is stored. Only the attribute code is stored at the address immediately before. Further, in this embodiment, the video RAM
Each address in (1) shall consist of 8 bits,
The most significant bit MSB is allocated for determining the character code or attribute code, and the remaining 7 bits are allocated as the content of the character code or attribute code. For example, if the most significant bit is “0”, this means the determination of the character code, and if the most significant bit is “1”, this means the determination of the attribute code. 00-7F "H (H
128 hexadecimal) character codes can be stored in the video RAM (1), and "80-FF"
128 types of H attribute codes are video RAM
The data can be stored in the remaining addresses of (1). Then, by reading the stored code from the video RAM (1) and simultaneously decoding the most significant bit, it is possible to determine what kind of code the code is.

Now, one of the above-mentioned microcomputers
The machine cycle is a CPU that performs a write / read operation of the video RAM (1) based on the decoding result of the program.
Video RAM regardless of timing and CPU operation
OSD (ON SCREE) that performs the read operation of (1)
N DISPLAY) timing. Specifically, one machine cycle consists of 6 states in which CPU timing for 3 periods and OSD timing for 3 periods are alternately repeated. Since the video RAM (1) is independently accessed at the CPU timing and the OSD timing, a single port having a simple structure will suffice.

(2) is, for example, the above-mentioned CPU that performs 8-bit arithmetic processing, and the purpose is to perform a logical operation or write to the video RAM (1) according to the decoding result of the program data read from the EEPROM described later. Address data, character codes, attribute codes, etc. are transferred via the data bus (3), and video RA
The code is taken in via the data bus (3) for the purpose of confirming the contents already written in M (1). (4) is a row address register,
Video R during the CPU timing of each machine cycle
The row address of AM (1) is addressed by the row address register (4). Row address data is set in the row address register (4) from the CPU (2) through the data bus (3). Similarly,
(5) is a column address register, and the column address of the video RAM (1) is addressed by the column address register (5) during the CPU timing of each machine cycle. Column address data is set in the column address register (5) from the CPU (2) through the data bus (3).

(6) is an EEPROM (storage means), and each byte has an 8-bit structure in accordance with the 8-bit arithmetic processing of the CPU (2).
Inside, the number of addresses corresponding to 128 kinds of character fonts is allocated to the second storage area for storing character data, and the remaining addresses are the first storage area for storing program data for controlling operation of the microcomputer. Is allocated to. Particularly, in the second storage area of the EEPROM (6), dot patterns of all characters to be displayed on the television screen are stored in advance. For example, when each display character that the viewer sees on the television screen is formed in a specific character font (vertical m dots × horizontal n dots), each character in the second storage area is expanded with the character font. The dot pattern that will be stored will be stored. Specifically, one character font is specified by the character code read from the video RAM (1), and the vertical address in one character font is specified according to horizontal scanning.
As a whole, data for n dots in the horizontal direction is read n times in the vertical direction.

(7) is a vertical position control circuit for detecting the vertical start position of the displayed character, and the video RAM (1) is addressed by the vertical position control circuit (7) during the OSD timing of each machine cycle. . The vertical position control circuit (7) has a first counter function of counting the rising of the horizontal synchronizing signal Hsync in binary after being reset by the rising of the vertical synchronizing signal Vsync existing in the television signal, and the horizontal scanning is a display character. First, the number of horizontal synchronization signals Hsync is set in advance in binary from the CPU (2) when the start position in the vertical direction is reached.
It has a register function. Then, the vertical position control circuit (7) increments row address data every time the rising edge of the horizontal synchronizing signal Hsync is applied m times from the time when the first counter function counts the value of the first register function. To occur. The vertical position control circuit (7) uses the binary count value of the rising of the m horizontal sync signals Hsync every time the row address data is incremented, and sets the value in the second storage area of the EEPROM (6). In order to control, it is applied to the address switching circuit (15) described later. Therefore, this second storage area is accessed by the character code of the video RAM (1) and the vertical address of the character font corresponding to the horizontal scanning,
The horizontal n-dot data of each display character can be read m times in the vertical direction.

(8) is a state control circuit, which generates various signals for controlling the operation of the circuit shown in FIG. 1 based on the oscillation clock LC. That is, the dot clock DCLK that repeats the cycle for each horizontal dot of the character data is generated based on the oscillation clock LC, and the character switching pulse CCP is generated for each horizontal n dots of the character data based on the dot clock DCLK. To occur. Furthermore, the state control circuit (8) is also connected to the CPU (2) via the data bus (3), and switches the text mode or the caption mode based on an instruction from the CPU (2).

(9) is a horizontal position control circuit for detecting the horizontal start position of the displayed character, and the video RAM (1) is addressed by the horizontal position control circuit (9) during the OSD timing of each machine cycle. It Inside the horizontal position control circuit (9), a second counter function for counting the rising of the dot clock DCLK in binary after being reset by the rising of the horizontal synchronizing signal Hsync existing in the television signal, and the dot clock DCLK Has a second register function in which the number of dot clocks DCLK when the display character is started to the horizontal start position is set in advance in binary. The horizontal position control circuit (9) has the second counter function of the second
From the time when the value of the register function is counted, the column address data that is incremented every time the dot clock DCLK is applied n times is generated. Reference numeral (10) is an address switching circuit, which responds to the timing switching signal C / O by a row address register (4) and a vertical position control circuit (7).
One of the row address data is switched and output. Here, the timing switching signal C / O is
This signal is a high level at the CPU timing and a low level at the OSD timing. That is, the address switching circuit (10) switches and applies the data held in the low address register (4) to the video RAM (1) when the timing switching signal C / O is at the high level, and the timing switching signal C / O changes. At the low level, the data held by the vertical position control circuit (7) is switched and applied to the video RAM (1). Similarly, (11) is also an address switching circuit, and when the timing switching signal C / O is at high level, the data held in the column address register (5) is stored in the video RAM (1).
Further, when the timing switching signal C / O is at a low level, the data held by the horizontal position control circuit (9) is switched and applied to the video RAM (1). Therefore, video R
The AM (1) is accessed by the combined data of the row address register (4) and the column address register (5) at the CPU timing, and the combined data of the vertical position control circuit (7) and the horizontal position control circuit (9) at the OSD timing. Will be accessed at.

Reference numeral (12) is a data switching circuit for writing / reading a character code and an attribute code to / from the video RAM (1) according to the timing switching signal C / O. For example, in the CPU timing, when writing to the video RAM (1) in each machine cycle consisting of six states as shown in FIG. 2, the timing switching signal C / O in the sixth state of each machine cycle is used. Video R during the high level period of
CPU to the accessed address of AM (1)
From (2) to the data bus (3) and the data switching circuit (1
A character code or an attribute code is written via 2). On the contrary, the video RAM (1) is used for the purpose of confirming the write contents.
When reading from (1), the character code or the attribute code is obtained from the accessed address of the video RAM (1) during the high level period of the timing switching signal C / O in the fourth state of each machine cycle. CPU via (12) and data bus (3)
It is taken in by (2), which allows the CPU (2) to analyze the code. On the other hand, at the OSD timing, the video RAM is in the read state.
When (1) is accessed an address corresponding to both data of the vertical position control circuit (7) and the horizontal position control circuit (9), a character code or an attribute code is output from this address of the video RAM (1). Switching signal C
They are read during the low level period of / O, and these are output to the MSB determination circuit described later at the timing when the low level of the timing switching signal C / O switches to the high level.

(13) is the above-mentioned MSB determination circuit, which is connected to the video RAM via the data switching circuit (12).
It is determined whether the code read from (1) is a character code or an attribute code. That is, as described above, the video RAM (1)
Since the most significant bits of the character code and the attribute code stored in are respectively determined to be “0” and “1”, the MSB determination circuit (13) determines the most significant bit of the applied code, When it is determined to be "0", this code is regarded as a character code and is applied to a latch circuit which will be described later, and when it is determined to be "1", this code is regarded as an attribute code and is applied to an attribute control circuit which is described later.

(14) is the above-mentioned latch circuit,
The character code output from the SB determination circuit (13) is latched in synchronization with the rising edge of the character switching pulse CCP. (15) is an address switching circuit, C
The so-called address data that is output from a program counter (not shown) inside the PU (2) and that accesses the first storage area of the EEPROM (6) and the so-called address data that accesses the second storage area of the EEPROM (6). The character code latched in the latch circuit (14) and the vertical address data of the character font corresponding to the horizontal scanning are switched and output in synchronization with the timing switching signal P / C. Here, the timing switching signal P / C is a signal that becomes high level only in the first and fourth states of each machine cycle, as shown in FIG. 2, and this high level period is CP.
It is a period during which the passage of address data from U (2) is permitted, and the remaining low level period combines the character code latched by the latch circuit (14) and the vertical address data of the character font according to horizontal scanning. This is the period during which the address data is passed.

Reference numeral (16) is an attribute control circuit, and the MSB determination circuit (1) at the timing when the timing switching signal C / O rises from low level to high level.
The attribute control data for character-modifying each display character is generated based on the attribute code output from 3). A data switching circuit (17) switches and outputs the data read from the EEPROM (6) based on the timing switching signal P / C. Specifically, during the high level period of the timing switching signal P / C (first state of each machine cycle), the EEPROM is
The program data stored in the first storage area (6) can be directly fetched into the CPU (2) to execute data arithmetic processing and the like. Further, while the timing switching signal P / C is at the low level, the character font data stored in the second storage area of the EEPROM (6), that is, the n-bit data for n dots corresponding to the horizontal scanning (for example, "1"). Is displayed, and "0" is a non-displayed bit pattern)
Is sequentially applied to a latch circuit described later.

Reference numeral (18) is the n-bit latch circuit described above, which latches n bits of the font data for one character output from the data switching circuit (17) during the low level period of the timing switching signal P / C. It is a thing. (1
9) is an n-bit shift register, which sets the n-bit data latched by the latch circuit (18) in synchronization with the character switching pulse CCP, and then the dot clock D
The operation of serially outputting n-bit data in synchronization with CLK is repeated. (20) is a register,
The attribute control data output of the attribute control circuit (16) is set in synchronization with the character switching pulse CCP. Reference numeral (21) is an output processing circuit, which processes the n-bit character data output from the shift register (19) and the attribute control data output from the register (20) to output an RGB signal. .

The operation of the character display device shown in FIG. 1 will be described below. In particular, the time code of FIG. It demonstrates using. EE
Regarding the character data stored in the second storage area of the PROM (6), the horizontal direction of the character font is 8 dots per character.

A character switching pulse C is generated every 8 clocks of the dot clock DCLK having a predetermined frequency and the dot clock DCLK in synchronization with the horizontal scanning of the television signal.
When CP is generated from the state control circuit (8), the horizontal position control circuit (9) outputs column address data which is incremented at each rising edge of the character switching pulse CCP. The horizontal address shown in FIG. 2 is the above-mentioned column address data, and n-1, n, n + 1, n + 2 ...
Is a video RAM because there is no change in vertical address
The address of (1) is shown. On the other hand, each machine cycle MC for operating the CPU (2) consists of 6 states, and becomes low level during the first, third, and fifth processing periods of each machine cycle MC, and the second, fourth, and sixth processing are performed. A timing switching signal C / O that is at a high level is generated during the period. That is, during the low level period of the timing switching signal C / O, the address data output from the vertical position control circuit (7) and the horizontal position control circuit (9) are respectively transferred to the video via the address switching circuits (10) and (11). It can be loaded into RAM (1), and the timing switching signal C / O
In the high level period of, the address data of the low address register (4) and the column address register (5) are transferred to the video R via the address switching circuits (10) and (11) respectively.
It can be taken into AM (1). Note that O and C shown in the video RAM access period shown in FIG. 2 are the access period by the address data output from the vertical position control circuit (7) and the horizontal position control circuit (9) and the row address register (4 ) And the access period by the address data of the column address register (5).

Therefore, since the video RAM (1) is accessed based on the address data output from the vertical position control circuit (7) and the horizontal position control circuit (9) during the low level period of the timing switching signal C / O. The output of the data switching circuit (12) for the horizontal address in FIG. 2 changes every period from the rising of the timing switching signal C / O to the next rising. When the output of the data switching circuit (12) is the attribute code as a result of the determination by the MSB determination circuit (13), the attribute code is applied to the attribute control circuit (16) at the same time as the output from the data switching circuit (12), The attribute control data is held in the register (20) in synchronization with the rising edge of the character switching pulse CCP and applied to the output processing circuit (21). That is, since the processing for character modification is performed at the timing of switching the character display, subsequent characters are subjected to predetermined modification. On the other hand, as a result of the determination by the MSB determination circuit (13), when the output of the data switching circuit (12) is character data, the character data is n-bit data for each horizontal scanning in synchronization with the rising edge of the character switching pulse CCP. It is latched by the latch circuit (14).

The address switching circuit (15) outputs the contents of the program counter of the CPU (2) or the character code output of the latch circuit (14) and the vertical position control circuit (7) according to the timing switching signal P / C. ), The contents of the vertical address of the character font output from
Output for OM (6) access. Specifically, assuming that the value of the program counter is incremented in the high level period of the first state of each machine cycle, the output of the EEPROM (6) outputs the timing switching signal P.
The data in the first and second storage areas are read alternately according to / C. Incidentally, the EEPROM (6) shown in FIG.
The outputs m, n, etc. mean the data output corresponding to the address data latched in the program counter and latch circuit (14). Then, the latch circuit (1
The input of 8), that is, the output of the data switching circuit (17) is switched by the timing switching signal P / C, and changes in accordance with the rise of the timing switching signal P / C as shown in FIG. By setting the contents of the latch circuit (18) in the shift register (19) at the rising edge of the character switching pulse CCP and applying it to the output processing circuit (21) in synchronization with the dot clock DCLK, a certain modified state is obtained. Character display is realized in synchronization with horizontal scanning.

As described above, according to the present invention, the EEPROM
The storage area of (6) has the same address space as a first storage area for storing program data for controlling the operation of the microcomputer and a second storage area for storing character data for displaying characters. Further, the first and second storage areas of the EEPROM (6) can be accessed at different timings in a predetermined processing period obtained by dividing each machine cycle period of the microcomputer into a plurality of parts.
As a result, even when the EEPROM is used, it is possible to prevent the peripheral circuit from increasing in size, and since the first and second storage areas are not accessed at the same time, correct data can always be read.

In this embodiment, the storage means is EEPRO.
Although described as M (6), it is needless to say that the present invention is not limited to this, and may be, for example, a mask ROM or an ultraviolet erasable EPROM. In addition, the above-described embodiments are merely examples of the present invention, and various modifications can be made as necessary, and the present invention described in the claims is
It includes all those changes.

[0027]

According to the present invention, in the storage area of the storage means, the first storage area for storing the program data for controlling the operation of the controlled portion and the character data for displaying the character are stored. Allocated to the second storage area in the same address space, and further, the first and second storage areas of the storage means are allocated in a predetermined processing period obtained by dividing each machine cycle period for the operation of the controlled unit into a plurality of parts. Made it possible to access at different times. As a result, even when an EEPROM is used as the storage means, it is possible to prevent the peripheral circuit from increasing in size, and since the first and second storage areas are not accessed at the same time, it is possible to always read correct data. can get. Further, according to the present invention, the second address means is provided with a latch circuit for holding the character code of the video RAM at the character switching eye position of the display character in the horizontal scanning direction in order to output the address. The same read address can be supplied to the address switching means while reading one horizontal scan of the font.

[Brief description of drawings]

FIG. 1 is a diagram showing a character display device of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

[Explanation of symbols]

 (1) Video RAM (2) CPU (6) EEPROM (14) (18) Latch circuit (15) Address switching circuit (19) Shift register (21) Output processing circuit

Claims (4)

[Claims] 1. A memory comprising a first storage area in which program data for controlling the operation of a controlled portion is stored, and a second storage area in which character data of a predetermined font to be displayed on the display portion is stored. Means, a first address means for accessing the first storage area of the storage means, a second address means for accessing the second storage area of the storage means, and in each machine cycle divided into a plurality of processing periods. so,
The first address means is allowed to access the first storage area of the storage means during the first processing period, and the second address means is the second storage area of the storage means during the remaining second processing period. Address switching means for permitting access to the memory, and data processing means for processing the character data read from the second storage area of the storage means and displaying the characters on the display unit. Character display device. 2. The second address means includes a video RAM in which a character code for accessing the second storage area of the storage means is stored, and the video RAM is at a horizontal scanning position of a television signal. The character display device according to claim 1, wherein the character display device generates a corresponding character code. 3. The second address means comprises a latch circuit for holding a character code of the video RAM at a horizontal display start position of each character during horizontal scanning of the television signal. The character display device according to claim 2. 4. The second address means comprises a latch circuit for holding an address for accessing a second storage area of the storage means at a display character change start position. Character display device described.