JPH08336105A - Image data display control method and image display controller using same - Google Patents

Abstract

PURPOSE: To exclude the irregularities of an image without using a video RAM of two image by providing a converter which converts image data to a video signal by reading out of two areas of the video RAM alternately and a controller which writes the image data on a selected area. CONSTITUTION: The image data of one frame is developed on a work RAM 16 by a CPU 15. Thence, it is judged whether or not a scanning line exists in the center of the screen from the count value of the horizontal synchronizing signal of a counter in an arithmetic circuit by a second VDP 21, and when it is true, the upper half area of the VRAM 24 is controlled in a non-display mode. Thence, the upper half of the image data developed on the RAM 16 is transferred to the video RAM 24, and the front half area of the VRAM 24 is set in a display mode. Moreover, the VDP 21 judges whether or not the scanning line arrives at a vertical synchronizing signal period, and when it is true, the latter half area of the VRAM 24 is set in the non-display mode. The image data of lower half developed on the RAM 16 is transferred to the VRAM 24. Such operation is repeated in the period of image display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data display control device. In particular, it is characterized in that image data is stored in a video RAM, which is sequentially read out and converted into a video signal for display and writing of the image data into the video RAM and control of reading out the image data from the video RAM. The present invention relates to an image data display control device.

[0002]

2. Description of the Related Art FIGS. 9A and 9B show image data stored in a video RAM (VRA for simplification in the figure).
A conventional technique for storing image data in the video RAM and writing the image data to the video RAM and reading the image data from the video RAM in a device for converting the video signal into a video signal for display will be described. It is a figure.

In FIG. 9 (A) and FIG. 9 (B), 50,
Reference numeral 51 denotes a first and second video RAM # 1, each of which has a capacity to store one screen (frame) of image data.
# 2. Reference numeral 52 is a monitor device for converting the image data read from the video RAMs 50 and 51 into a video signal by means not shown and sequentially scanning and displaying.

FIG. 9A shows a state in which one screen (frame) of image data has already been stored in the first video RAM 50 and is sequentially read in order to display this on the monitor device 52. ing. At this time, one of the second videos R
The AM 51 is in a state where image data for displaying the next screen (frame) is sequentially stored.

In FIG. 9B, the display of the image data stored in the first video RAM 50 is completed, and at the same time, the storage of the image data for one frame in the second video RAM 51 is completed. It shows a state in which the state is switched from the state of (A), the image data stored in the video RAM 51 is read, and the storage of the image data of the next frame in the first video RAM 50 is started.

As described above, in the conventional apparatus shown in FIGS. 9A and 9B, the video RAM for two screens is required, and the video RAM is switched alternately for writing and reading the image data. It was something to do.

On the other hand, FIG. 10 is a diagram for explaining control in another conventional apparatus. In this conventional example, the video RA
It has M for one screen. FIG. 10A shows a video signal in which image data is read from the video RAM and converted for display. V _SYNC is a vertical sync signal.

In this conventional device, the video RA is controlled by DMA (direct memory access) transfer control.
Writing of image data to M and reading of image data from the video RAM are performed at high speed. FIG. 10B shows
The transfer timing of the image data A and the image data B to be DMA-transferred is shown.

The DMA transfer of the image data A and B is as follows.
As shown in FIG. 10A, the vertical synchronization signal V _SYNC
During the period of. In addition, in FIG.
(I) and (II) are 1/60 second periods in which the image data A and B are displayed, respectively.

Accordingly, the image data is written in the video RAM in the vertical synchronizing signal V _SYNC period, the next display period following the vertical synchronizing signal V _SYNC period or a horizontal synchronizing signal H
_{During the SYNC} period, the image data is read from the video RAM, converted into a video signal and displayed. In the conventional apparatus shown in FIG. 10, one screen of video RA
Just prepare M.

On the other hand, in recent years, full-color image display of 16 million colors or the like has been performed in personal computers, video game devices and the like. In such a device, FIG.
As shown in FIGS. 9A and 9B, two screens of video R are displayed.
With AM, full-color display is possible. This is because it is possible to use two screens of video RAM and write to the other video RAM while one is being read. Therefore, it is possible to secure a sufficient writing time even for full-color data, which has a large data transmission capacity.

Having two screens of video RAM is not advantageous in terms of cost and device scale.
When the display is performed by the video RAM for one screen, the display control as described in FIG. 10 is performed.

However, in the case of displaying an image with 16 million colors as described above, the image data for one frame (320 × 224 pixels) is stored in the video RAM during the vertical synchronizing signal V _SYNC period (non-display period). Sometimes it is difficult to transfer. In such a case, the image data is transferred to the video RAM during the display period, which causes screen disorder.

[0014]

SUMMARY OF THE INVENTION Therefore, the first object of the present invention is to provide an image display control method which avoids preparing two screens of video RAM among the problems of the conventional device. Especially.

Further, an object of the present invention is to solve the problem in the conventional apparatus that the image data cannot be transferred during the vertical synchronizing signal period when the video RAM for one screen is prepared and the screen is disturbed. It is to provide a display control method.

Another object of the present invention is to provide an image display device adopting such an image display control method.

Furthermore, the present invention is to provide a video game device adopting such an image display control method.

[0018]

An image display device according to claim 1 for solving the above-mentioned problems of the present invention is a video RAM having first and second areas, and is operatively connected to the video RAM. A converter configured to alternately read the image data from the first and second areas of the video RAM and convert the image data into a video signal, operatively connected to the video RAM, Alternately selecting the first and second regions, and selecting the selected one region while the converter is not accessing the selected one of the first and second regions. It has a controller configured to write the image data.

Further, the image display device of the present invention according to claim 2 is a video RAM having a memory area corresponding to at least one frame of image data, and is operatively connected to the video RAM to store the image data. A converter for converting to a video signal, a reading means for continuously reading the image data from the video RAM and transferring the read image data to the converter, and the reading means for the video RAM.
And a unit for writing image data to the one area while the one area is not being accessed.

The image display apparatus of the present invention according to claim 3 is a video RAM having a memory area corresponding to one frame of image data, and is operatively connected to the video RAM and read from the video RAM. A converter that converts the output image data into a video signal and a converter that is operatively connected to the video RAM so that writing and reading of the image data are alternately controlled every 1/2 frame of the memory area. And a controller for controlling writing of image data to the memory area of the video RAM and reading of image data from the memory area.

Furthermore, the image display device of the present invention according to claim 4 is a video RAM having a memory area for storing image data, and is operatively connected to the video RAM and read from the video RAM. A converter for converting the captured image data to a video signal, and operatively connected to the video RAM for transferring a second portion of the image data from the second area of the video RAM to the converter. A controller writes the first portion of the image data to a first area of the video RAM during transfer.

An image display device according to a fifth aspect of the present invention is the image display device according to the first, second, third, or fourth aspect, further including a CPU for generating the image data, The controller continuously writes the image data generated by the CPU in the area of the video RAM in which the image data already sent to the converter has been written.

An image display device according to the present invention is a CPU for generating image data, a video RAM having an area for storing the image data, and the video RA.
A conversion circuit for converting the image data read from M into a video signal, and an area for storing the image data in the video RAM, which is divided into a first area and a second area. It has a control unit that controls to alternately switch writing of image data from the CPU and reading of image data to the conversion circuit.

Further, the image display device of the present invention according to claim 7 is the image display device according to claim 6, further comprising counting means for counting the number of scanning lines for displaying the video signal. The control unit detects the timing when the number of scanning lines of the video signal counted by the counting unit reaches a predetermined value, and controls the writing and reading at the detected timing. And

The image display device of the present invention according to claim 8 is the image display device according to claim 7, wherein the timing at which the number of scanning lines reaches a predetermined value is the scanning line required for displaying one screen. It is characterized in that the value is set to 1/2 of the number.

Furthermore, the image display device of the present invention according to claim 9 is a CPU, a video RAM having an area for storing image data, a background image generation section, and a display connected to the background image generation section. A video processor that includes a control unit, sequentially reads out image data of an image to be displayed by accessing the video RAM, and generates background image data under the control of the CPU. It is characterized in that the area for storing the image data of the video RAM is divided into two areas, and writing and reading are alternately performed.

An image display device according to a tenth aspect of the present invention is the image display device according to the ninth aspect, wherein the video processor further counts the number of scanning lines for displaying the video signal. And detecting the timing when the number of scanning lines of the video signal counted by the counting means reaches a predetermined value, and controlling the switching between the writing and reading at the timing. .

Furthermore, the image display device of the present invention according to claim 11 is the image display device according to claim 10, wherein the timing at which the number of scanning lines reaches a predetermined value is a scan required for displaying one screen. It is characterized in that the value is set to 1/2 of the number of lines.

Further, the image display control method of the present invention according to claim 12 is a display control method of image data for writing image data in a video RAM and reading image data from the video RAM. From the image data, the step of transferring the read image data to a converter, the converter converting the transferred image data into a video signal, and further converting Writing the image data to a second area of the video RAM while transferring the data read from the one area to the converter.

The image display control method of the present invention according to claim 13 is the image display control method according to claim 12, further comprising the step of generating image data, and the generated image data, In the area of the video RAM where the image data already sent to the converter has been written,
It has a step of writing continuously.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same or similar parts will be described with the same reference numerals and symbols.

FIG. 1 is a block diagram for explaining the outline of a video game device to which the image data display control method of the present invention is applied.

Here, in order to understand the image data display control method of the present invention applied to the video game apparatus of the embodiment of FIG. 1 more correctly, the image processing technique adopted in a general video game apparatus will be described first. The description will be given based on the explanation given in the specification of the patent application [Application under the Patent Cooperation Treaty (International Patent Publication Number: W095 / 01630)] that the assignee of the present application previously issued.

In the video game device, a foreground image displaying a character appearing in the game (hereinafter referred to as "sprite") is superimposed on a background image of the ground, sea surface, sky, outer space, etc., and the result is used as a monitor device. indicate.

The game player advances the game by operating and controlling the movement of the sprite, which is the foreground image on the screen, from an input device such as an input pad. The movement of the sprite can be displayed by moving the foreground image and the background image relatively.

In this case, it is possible to fix the background image and move the foreground image vertically and horizontally and rotate it, or to fix the foreground image and move the background image vertically and horizontally and rotate it. Furthermore, the function of moving the background image vertically or vertically or rotating it is called a scroll function.

Conventionally, in addition to the scroll function, there are a window function and a priority function as image display control. The window function is a function of setting a transparent image area called a window and dividing the screen inside and outside the window to display different images.

Further, the priority function is a function of displaying only one of the images in accordance with a predetermined priority when the display overlaps with the background image or another window screen.

Further, the scroll function will be described. The scroll screen displayed by the scroll function is a technique in which the foreground screen side on which the sprite is displayed is fixed at the substantial center of the screen screen, while the background image is moved.

The screen screen format includes a cell format and a bitmap format. When displaying a cell-type scroll screen on the screen, for example, 8 x 8
Background image data is formed by combining a plurality of cell pattern data composed of image data of pixels (repeat the same one or combine different patterns as necessary) and spread them on the screen screen.

The pattern data of the cell image and the spread position of the cell image on the screen are designated by data called pattern name data. The pattern data and pattern name data of the cell image are stored in the video RAM which is an image memory.

In the video game device, when a background image is displayed, image information is written in the video RAM from the cassette ROM or the CD-ROM under the control of the CPU in advance, or the image information processed by the CPU is written. Be done.

The pattern name data is first read from this video RAM, the video RAM is accessed again using this pattern name data, the pattern data of the cell image is read, and this is displayed on the screen of the monitor device.

On the other hand, image data (referred to as pattern data) of a sprite (for example, an airplane in a flight simulation game) displayed in the foreground image is stored in the video RAM in dot units. Therefore, the video RAM is accessed for each dot and the sprite is displayed on the screen screen.

Returning to FIG. 1, the area 10 surrounded by a broken line is the main body of the video game apparatus, to which the control pad 34 which is an input device for the player to operate the game is connected.

The control pad 34 may be in the form of being fit in a player's hand which is pulled out by a cord from the main body of the video game device, or as an input button integrally attached as a part of the video game device.

The control pad 34 is further provided with an SMPC (System Manager & Peripher) functioning as an I / O controller.
al Control) 33 to a first bus (C-BUS) connected to the CPU 15 of the video game apparatus body 10.

The SMPC 33 has a reset management function for the entire video game device and an interface function with an external device such as the control pad 34.

A cartridge 35 is detachably attached to the video game apparatus body 10 through a connector.
The cartridge 35 includes a read-only semiconductor memory (RO
The game program is written and stored in M).

Therefore, the cartridge 35 is accessed from the apparatus main body 10 and the data read from the cartridge 35 is input to the apparatus main body 10 through the second bus (A-BUS).

The CPU 15, RAM 16, and ROM 17 are also S
Like the MPC 33, it is connected to the first bus (C-BUS). The CPU 15 is a ROM in the cartridge 35.
It reads and executes the game program stored in and controls the entire video game device. Also, CPU1
5 is composed of, for example, a 32-bit RISC type high-speed CPU.

The bus controller 18 includes a DMA controller (dynamic memory access control device) and an interrupt controller, and has a function as a coprocessor of the CPU 15.

The sound processor 36 uses the voice (PCM
/ FM), the D / A converter 37 converts a digital signal into an analog signal, and outputs a voice 38 from a speaker (not shown).

A third bus (B-BU) in the main body of the apparatus
In S), together with the bus controller 18 and the sound processor 36, a first video display processor (VDPI) 20 for controlling the display of characters displayed in the foreground of the screen such as sprites appearing in the game, and the displayed characters are displayed. A second video display processor (VDPII) 21 that controls scrolling of the background screen, such as fixing the background screen, rotating the background screen up and down, and rotating or moving the screen to the left and right, is connected to give a relative motion.

First video display processor 20
Is the command RAM 22 and the frame buffer memory 2
3 are connected. The first video display processor 20, the command RAM 22, and the frame buffer memory 23 constitute a first image information processing for performing image processing of sprite display which is a foreground screen.

Furthermore, the first video display processor 20 can be formed on a semiconductor chip as an IC chip. The first video display processor 20 includes a command RAM (for example, a DRAM
And a two-sided frame buffer memory 23
(For example, each has a memory capacity of 2 Mbits)
Is connected.

The command RAM 22 stores command data sent from the CPU 15 and image data as an original image of the foreground image. Further, in the frame buffer 23, character screen data such as a sprite which is a foreground image is expanded.

The CPU 15 executes the program in the ROM 17 to send command data (drawing command) to the first video display processor 20. The first video display processor 20 writes the sent command data in the command data RAM 22 as a command table.

The written command data is selected and read out, and sprite correction processing such as rotation, enlargement, reduction, and color calculation is performed. Next, the data is written into a predetermined address of the frame buffer 23, and the image data of the foreground image for one frame is expanded.

First video display processor 20
Sequentially reads the image data for one frame written in the frame buffer 23, and supplies this image data to the second video display processor 21. Here, the information for controlling the drawing is set in a system register (not shown) inside the first video display processor 20.

Here, one pixel of the image data processed by the first video display processor 20 is represented by 16 bits as shown in FIG. The lower 11 bits are a color code bit for designating a color and are used for the color RAM 2
5 is used as a read address.

Bits D11 to D14 are the priority code. When a plurality of images are displayed in an overlapping manner, the priorities of the pixels of the overlapping images are compared with each other, and the pixels of high priority are displayed in preference to the pixels of low priority.

The image data of such a foreground picture is input from the first video display processor 20 to the terminal 40 in FIG. Among the input foreground image data, the window flag of the most significant bit D15 is supplied to the sprite window detection unit of the second video display processor 21, which will be described later.

The remaining lower 15 bits D0 to D14 of color code and priority code are supplied to the display controller of the second video display processor 21.

Second video display processor 21
Is a video RAM 24 and a color RA which are objects of the present invention.
It becomes a background image together with M25. A second image information processing unit that performs image processing of the scroll screen is configured. The second video display processor 21 can be formed on a semiconductor chip like the first video display processor 20.

The second video display processor 21 has a built-in register (not shown in FIG. 1) in which data for generating image data is set, and a predetermined memory in which a color code is recorded. A capacity color RAM 25 and a video RAM 24 are connected.

Second video display processor 21
Reads out the data stored in the video RAM 24 according to the setting of the built-in register (not shown) described above, determines the priority according to the setting of the image data register of the scroll screen, and generates the image data.

The generated image display data is converted into display color data, converted into an analog signal through the D / A converter 31, and output to a display device (not shown). Here, the image display data is set in the video RAM 24 and the color RAM 25 through the bus controller 18.

As will be described later, the video RAM 24 has a capacity of one screen (frame) according to the features of the present invention, as an embodiment. Further, one screen is switched for each sub-frame area of 1/2 frame having the same capacity, and writing and reading of image data are alternately performed.

In the frame area of the video RAM 24, pattern data, which is the data of cells of 8 × 8 pixels in the vertical and horizontal directions, and m × n cells are laid out to form a background image for one frame. Pattern name data (address indicating the storage position of the pattern data stored in the color RAM 25) that indicates which cell defined in the color RAM 25 is used corresponding to the position is stored.

Therefore, the foreground screen data from the first video display processor 20 and the background screen data from the second video display processor 21 are combined to form the above-mentioned image display data.

The configuration of the second video display processor 21 will be further described with reference to FIG.

In FIG. 3, the sprite window detector 42 is connected to the first video display processor 20 through the terminal 40. The sprite window detection unit 42 detects whether or not the most significant bit D15 included in the sprite image data (see FIG. 2) read from the frame buffer 23 of the first video display processor 20 has been changed.

If the value is "1", it means that the pixel including this is a window pixel, and if the value is "0", that pixel is not a window pixel.
The window pixel means a transparent pixel.

The display control unit 43 is connected to the background image generation unit 41 and the window control unit 44, and controls the image data so as to combine the sprite image data and the background image data.

The display control unit 43 includes switches 50 and 51.
Is provided. During the period in which the switch signal FGSW is on, that is, in order to open the window because it is a transparent pixel, the switch 50 switches the color code of the image data of the foreground image (displayed as FG in FIG. 3) to 00H.
(H indicates hexadecimal), and the switching signal F
In the period in which the GSW is off, that is, in the period instructing not to open the window, the image data of the foreground image FG is output as it is.

Here, the switching on / off of the switching signal FGSW indicates that the video display processor 20 has the most significant bit D15 included in the sprite image data (see FIG. 2) read from the frame buffer 23.
Is output from the window control unit 44 in accordance with whether the value of is "1" or "0".

Similarly, the switch 51 outputs the switch signal BG.
While 0SW is on, the color code of the image data of the background image (indicated by BG0 in FIG. 3) is replaced with 00H, and while the switching signal BG0SW is off, the image data of the background image BG0 is output as it is. .

A priority circuit 54 is connected to the switches 50 and 51. This priority circuit 5
4 is a foreground image F output through the switches 50 and 51.
Input the image data of G and the background image BG0.

The priority circuit 54 determines whether or not the color code of the input image data of the foreground image FG and the background image BG0 is 00H. In case of 00H,
Consider this transparent. For image data other than 00H, the priorities are compared and the image data corresponding to the highest priority code is selected and output.

A colorization circuit 55 is connected to the priority circuit 54. The colorization circuit 55 accesses the color RAM 25 by a color code when the image data output by the priority circuit 54 is in the palette format.

Then, the RGB data representing each level of the three primary colors RGB stored in the address corresponding to the color code is obtained from the color RAM 25 and is output from the terminal 56. Further, when the image data is in RGB format, it becomes display color data as it is and is output from the terminal 56.

The RGB data output from the terminal 56 is
As shown in FIG. 1, it is converted into an analog signal by the D / A converter 31 and output as an RGB video signal from the terminal 32 and displayed on a monitor device (not shown).

The window control unit 44 has the same configuration as in FIG.
It has a function of sending the sprite image data to the display control unit 43 as a window signal having the shape of the sprite image based on the most significant bit (D15) of the image data shown in FIG.

The window control unit 44 is provided with a control register 45. The contents of the control register 45 can be rewritten by the CPU 15 through the terminal 46. The following 1 to 5 information is set in the control register 45.

That is, the first is an inside / outside control bit indicating whether the window is opened inside or outside the window shape designated by the window flag of the foreground picture.

The second is a sprite window control word consisting of 3-bit enable bits for instructing whether to open the foreground image FG and the background image BG0 for each pixel.

The third is rectangular window position information representing XY two-dimensional coordinates indicating the rectangular window start position and end position.

The fourth is a rectangular window control word consisting of inner and outer bits and an enable bit for a rectangular window.

The first to fourth bits and information are designated for each of the plurality of sprite windows and rectangular windows.

Further, the fifth is a sum-of-products control word for instructing which of a logical sum area and a logical product area of a plurality of sprite windows and a rectangular window should be opened.

The window control unit 44, according to the contents of the control register 45, the foreground image FG and the background image BG0.
For each of them, the switching signals FGSW and BG0SW for instructing the position to open the window mentioned above are generated and supplied to the display control unit 43.

Next, the background image generator 41 to which the method of the present invention is applied will be described. A block diagram of a configuration example of the background image generation unit 41 is shown in FIG. The background image generation unit 41 is for generating the background image BG0. The pattern name data is read from the video RAM 24.

Video R is generated by this pattern name data.
The pattern data is read from the AM24 and the background image BG
0, image data of BG1 is obtained. This image data is composed of 15 bits excluding the window flag D15 of FIG.

The background image generator 41 is composed of an image signal conversion processing circuit 410, a video RAM access circuit 411, and vertical and horizontal counters 412 and 413. FIG.
In the above, the image signal conversion processing circuit 410 performs calculation for coordinate conversion processing by moving and rotating image data.

This operation is a predetermined matrix operation for moving and rotating the image data, as described in the PCT application previously filed by the applicant.

Further, the image signal conversion processing circuit 410 is based on the two-dimensional coordinate data of the image signal subjected to the coordinate conversion processing, and in synchronization with the horizontal count value from the horizontal synchronization counter 412, the coordinates X, Y of the scroll screen. To calculate. Then, this is supplied to the video RAM access circuit 411.

Here, the horizontal synchronization counter 412 is a CPU
Count the clocks input from 15 to the terminal 47,
The horizontal synchronization counter 412 outputs the horizontal synchronization signal timing. Further, the horizontal synchronizing signal timing is counted by the vertical synchronizing counter 413 to generate the vertical synchronizing signal timing.

On the other hand, the video RAM access circuit 411
Accesses the video RAM 24 using the coordinates X and Y of the input scroll screen as the pixel address of the background image.
The lower 3 bits of each of the coordinates X and Y (when the size of the cell is 8 × 8 dots in the vertical and horizontal directions) becomes the pixel position address in the cell. Further, a combination of bits other than the lower 3 bits of X and Y, a total of 6 bits, corresponds to the pattern name address for storing the pattern name data.

The video RAM access circuit 411 reads pattern name data from the video RAM 24 based on this pattern name address. Then, the color code pattern data is read from the video RAM 24 by the pattern data address and the pixel position address in the pattern name data.

Further, the video RAM access circuit 411.
Adds the priority code in the pattern name data to the pattern data of the color code read from the video RAM 24 to form the pixel data of the format shown in FIG. 2 and outputs the background image BG0 from the terminal 79.

The background image BG0 from the terminal 79 is shown in FIG.
As described above, the image data is output through the priority circuit 54.

Here, the video RAM access circuit 4
11 to 11 illustrate access operations according to the present invention for writing and reading to and from the video RAM 24.
Will be described with reference to.

FIGS. 5A and 5B are diagrams for explaining control of transfer and read of image data to and from the video RAM 24 as the first image data display control method. Figure 5
In (A), the video RAM 24 is 1 as an example.
It has a capacity for frames.

Further, the video RAM 24 has at least first and second regions divided by electrical control for one frame, for example, the first half region 24a and the second half region 24b.
Have.

In FIG. 5A, reference numeral 16 is a work RA.
This is the content of M16 (see FIG. 1) and shows a state in which image data A and B for two fields are stored. Further, the first half area 24a of the video RAM 24 shows a state in which the image data A to be displayed next is transferred from the CPU 15 and is being written, that is, a rewriting state of the image data A to the video RAM.

On the other hand, the latter half area 24 of the video RAM 24
From b, the already written image data B is read out and displayed on the monitor device 7.

That is, while the image data in the first area (the first half area 24a in the embodiment) is being scanned by the display device, the CPU 15 writes the image data following the image data in the first area by the CPU 15. Second of the video RAM 24
Is controlled so as to be accessible to the area (the latter half area 24b in the embodiment).

Further, the image data is read from the second area of the video RAM 24, and while the image data is being read by the display device, the CPU 15 can access it to write the image data in the first area. Become.

In a specific embodiment, in the present invention, when one frame screen of the monitor device 7 is composed of 224 scanning lines, when the display position reaches up to 112 scanning lines, which is half of that, a video is displayed. Two areas of the RAM 24, that is, the first half area 24a and the second half area 24b are alternately switched between writing and reading.

FIG. 5B shows a state in which writing and reading of the first half area 24a and the second half area 24b shown in FIG. 5A are switched. Image data A from the first half area 24a
Is read, and the image data A is displayed until the timing of displaying 0 to 112 scanning line regions.

Therefore, the second half area 24b of the video RAM 24 is in a state of transferring and writing the image data from the work RAM 16 of the CPU 15.

In FIG. 5A, the scanning line 112
Up to 224 display areas are being displayed.

FIGS. 6A and 6B are diagrams for explaining the relationship between the video signal (FIG. 6A) and the image data transfer (FIG. 6B) according to the present invention. In FIG., V _{SY NC} indicates the timing of the vertical synchronization signal from the vertical synchronization counter 413.

In the present invention, one frame period is divided into two as an example, and the image data A and B are divided into these two parts.
Image data for displaying the first half and the second half of one divided frame period.

In FIGS. 6A and 6B, the image data A
However, in the latter half period of the previous frame displaying the image data B, the bus controller 18 DMA-transfers the video data to the video RAM 24.

When a predetermined number, that is, the 112th horizontal synchronizing signal is counted, the image data A is read from the video RAM 24 and displayed on the display device 52 in the first half of the next frame.

On the other hand, the image data B is data to be displayed in the latter half period of the frame divided into two, and is shown in FIG.
As shown in, during the period of the vertical synchronization signal V _SYNC , DMA transfer from the work RAM 16 is performed by the bus controller 18 and writing to the video RAM 24 is started.

Then, writing is completed at least before the start of the latter half period, which requires reading for display.

Then, the 112th scanning line is detected (the number of horizontal scanning lines from the horizontal synchronizing counter 412 is counted by the counter in the arithmetic circuit 410, and when the predetermined count value 112 is detected. ) And video RA
The writing and reading of the first half area 24a and the second half area 24b of M24 are switched, the image data B is read from the video RAM 24, and the latter half of the frame is displayed.

During the display period of the image data B, the transfer of the image data A from the work RAM 16 to the video RAM 24 is performed as described above.

When the 112th horizontal synchronizing signal is counted, the switching is performed again, and the image data B is read from the video RAM 24 and the image data A is written. In this way, the transfer and display of the image data A and B are alternately repeated.

Thus, according to the present invention, the image data can be displayed on the monitor device with the video RAM capacity for one screen (frame) without causing the screen disturbance.

FIG. 7 is a flow chart showing the operation of the present invention described above to facilitate understanding. That is, in FIG. 7, when the operation of the apparatus is started, the CPU 15
The image data for the frame is expanded in the work RAM 16 (step S1).

Next, in the second video display processor 21, it is determined from the count value of the horizontal synchronizing signal of the counter in the arithmetic circuit 410 whether the scanning line is at the center of the screen, that is, one screen is composed of 224 scanning lines. If you do, 11
It is determined whether or not the second scanning line has been reached (step S2).

When the 112th scanning line is reached, the upper half area 24a of the video RAM 24 is controlled so as not to be displayed (step S3). Then, the image data A of the upper half of the image data for one screen expanded in the work RAM 16 is transferred to the video RAM 24 and written (step S4).
Further, the first half area 24a of the video RAM 5 is set to the display mode (step S5).

In this process, the video display processor 21 further determines whether or not the scanning line has reached the vertical synchronizing signal period (step S6). When the scanning line reaches the vertical synchronizing signal period, the second half area 24b of the video RAM 24 is set to the non-display mode (step S7).

Then, the image data B of the lower half of the image data of the one screen portion expanded in the work RAM 16 is transferred to the video R.
The data is transferred to the AM 24 (step S8). Further, when the transfer is completed, the second half area 24b of the video RAM 24 is set to the non-display mode (step S9). This operation is repeated and continued during the image display period.

FIGS. 8A and 8B are diagrams for explaining control of transfer and read of image data to and from the video RAM 24 as the second image data display control method according to the present invention. That is, in the first image data display control method shown in FIGS. 5A and 5B, the image data is alternately written and displayed from the CPU 15 in a half area of one screen as an embodiment. This is a control method for switching the reading of image data to the device.

In such control, the CPU 15 has already
Even if one frame of image data has been created, the transfer of that image data to the video RAM 24 is
It is necessary to wait until the reading of 1/2 frame of the image data of the previous frame to the display device is completed.

On the other hand, in order to speed up the display control, it is required to transfer the image data to the video RAM 24 as fast as possible.

Therefore, the second image data display control method shown in FIGS. 8A and 8B is a control method corresponding to such a request. That is, from the CPU 15 to the video R
The point of time when the image data is transferred to the AM 24 can be adaptively controlled by software.

In FIG. 8A, the work RAM 16
Shows a state in which an image to be displayed is formed. The video RAM 24 is in the middle of transferring the image data B of the previous frame to the display device 52, and the first area I
Is an area that has already been transferred to the display device 52. The second area II is a part of the image data to be further transferred to the display device 52.

As a second embodiment of the present invention, the CPU 15 can access the first area I for writing, and the second area II can be accessed for reading. is there.

In FIG. 8B, the transfer of the image data to the display device 52 further progresses, and in synchronization with this transfer, the first area I where the CPU 15 can access for writing.
Indicates an increased state.

That is, according to FIGS. 8 (A) and 8 (B),
According to the transfer of the image data from the video RAM 24 to the display device 52, write access from the CPU 15 to the first area I becomes possible sequentially.

Further, when the transfer of the image data B of the previous frame to the display device 52 for display on the display device 52 is completed, the area I indicated by hatching in the video RAM 24 is completed.
Then, the transfer of the image data written from the CPU 15 to the display device 52 is sequentially started, and the write and transfer processes are sequentially repeated in the same manner as described above.

Therefore, also in the second embodiment, the video RAM 24 has the first area I and the second area II, and when the first area is writable, the second area becomes When the first area is in the transfer state, that is, in the reading state, and the first area is in the reading state, the second area is writable.

Here, the switching between writing and reading of the first area I and the second area II can be performed as follows.

That is, the video RAM access circuit 4 of FIG.
A read access signal is sent to the video RAM 24 for the transfer of the image data to the display device 52 by 11. Therefore, by sending the timing of this read access signal to the CPU 15, it is easy for the CPU 15 to recognize that a writable area has occurred by software control.

As a result, if the CPU 15 has completed the generation of image data and is ready to transfer to the video RAM 24, the write access to the writable area is performed in synchronization with the read access signal for the video RAM 24. Done.

[0142]

As described above according to the embodiments of the present invention, the present invention has one video RAM unlike the conventional example having two video RAMs.

A large amount of image data that cannot be transferred during the vertical synchronizing signal period even with one video RAM, for example, a full screen is (320 × 224) and is 160
Even in the case of displaying the full color of 0,000 colors, it can be transferred to the video RAM without disturbing the screen.

Further, the scope of protection of the present invention is not limited to the above embodiments. The scope of protection is defined by the appended claims. Further, the scope of protection of the present invention also includes those within the scope equivalent to the claims.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a video game device to which an image data display control method of the present invention is applied.

FIG. 2 is a diagram illustrating a configuration example of image data.

FIG. 3 is a block diagram illustrating a configuration example of a VDP 21 in FIG.

4 is a block diagram showing a configuration of a background image generation unit in FIG.

FIG. 5 is a diagram illustrating data transfer to a video RAM according to the first image data display control method of the present invention.

FIG. 6 is a diagram illustrating the relationship between the transfer of a video signal and image data according to the first image data display control method of the present invention.

FIG. 7 is an operation flow corresponding to the first embodiment of the image data display control method of the present invention.

FIG. 8 is a diagram illustrating a relationship between transfer of a video signal and image data according to a second image data display control method of the present invention.

FIG. 9 is a diagram illustrating an example of a conventional display control method having a video RAM for two frames.

FIG. 10 is a diagram illustrating another display control method of the conventional example, in which image data is transferred during a vertical synchronization signal period.

[Explanation of symbols]

10 video game device main body 15 CPU 16 RAM 17 ROM 18 bus controller 20 first video display processor (V
DPI) 21 Second video display processor (V
DPII) 22 Command RAM 23 Frame buffer memory 24 Video RAM 25 Color RAM 31, 37 D / A converter 32, 40, 56 Terminal 33 SMPC (SystemManager & Peripheral C)
ontrol) 34 control pad 35 cartridge 36 sound processor 38 audio output

Claims (13)

[Claims] 1. A video RAM having first and second areas.
And a converter operatively connected to the video RAM and configured to alternately read image data from first and second regions of the video RAM and convert the image data to a video signal. Operatively connected to the video RAM to alternately select the first and second regions, the converter not accessing a selected one of the first and second regions An image display control device having a controller configured to write image data in the selected one region. 2. A video RAM having a memory area corresponding to at least one frame of image data, a converter operatively connected to the video RAM and converting the image data into a video signal, Image data is read continuously,
A read means for transferring the read image data to the converter; and a means for writing the image data in the one area of the video RAM while the read means is not accessing the one area of the video RAM. A characteristic image display control device. 3. A video RAM having a memory area corresponding to one frame of image data, and a converter operatively connected to the video RAM and converting the image data read from the video RAM into a video signal. , One of the memory areas operatively connected to the video RAM
A controller for controlling writing of image data to the memory area of the video RAM and reading of image data from the memory area so that writing and reading of the image data are alternately controlled every 2 frames. An image display control device comprising: 4. A video RAM having a memory area for storing image data, a converter operatively connected to the video RAM, and converting the image data read from the video RAM into a video signal. The image in the first area of the video RAM during transfer of a second portion of the image data from the second area of the video RAM to the converter to the converter. An image display controller comprising a controller for writing a first portion of data. 5. The CPU according to claim 1, further comprising a CPU for generating the image data, wherein the controller already sends the image data generated by the CPU to the converter. The image display control device is characterized in that the image data is continuously written in the area of the video RAM in which the image data is written. 6. A CPU for generating image data, a video RAM having an area for storing the image data, a conversion circuit for converting the image data read from the video RAM into a video signal, and the video RAM. The area for storing image data is divided into a first area and a second area, and writing of image data from the CPU and reading of image data from the conversion circuit are alternately performed for each area. An image data display control device having a control unit for controlling to switch to. 7. The method according to claim 6, further comprising counting means for counting the number of scanning lines for displaying the video signal, wherein the control section scans the video signal counted by the counting means. An image data display control device, which detects a timing at which the number of lines reaches a predetermined value and controls the writing and reading at the detected timing. 8. The image data display according to claim 7, wherein the timing at which the number of scanning lines reaches a predetermined value is set to a value which is ½ of the number of scanning lines required to display one screen. Control device. 9. A CPU, a video RAM having an area for storing image data, a background image generation section, and a display control section connected to the background image generation section, and accessing and displaying the video RAM. A video processor that sequentially reads out image data of an image to be reproduced and generates background image data under the control of the CPU, and the video processor divides an area for storing the image data of the video RAM into two parts. The image data display control device is characterized in that control is performed so that writing and reading are alternately performed in each area. 10. The video processor according to claim 9, further comprising counting means for counting the number of scanning lines for displaying the video signal, and the scanning lines of the video signal counted by the counting means. An image data display control device, which detects a timing when the number reaches a predetermined value and controls the switching between the writing and the reading at the timing. 11. The image data display according to claim 10, wherein the timing at which the number of scanning lines reaches a predetermined value is set to a value that is ½ of the number of scanning lines required to display one screen. Control device. 12. A display control method of image data for writing image data in a video RAM and for reading image data from the video RAM, comprising: reading the image data from the video RAM; Transferring the transferred image data, and converting the transferred image data into a video signal in the converter, and transferring the data read from the first area of the video RAM to the converter. To the video RA
And a step of writing the image data in the second area of M. 13. The method according to claim 12, further comprising the step of generating image data, and the generated image data in the area of the video RAM in which the image data already sent to the converter has been written. An image display control method comprising a step of continuously writing.