JPH08331066A - Voice signal processing unit for bs tuner - Google Patents

Abstract

PURPOSE: To prevent production of noise unpleasant to ears by continuing bit replacement without stopping it even when an error flag number is decreased in the case of much deteriorated C/N. CONSTITUTION: When a radio wave state is deteriorated and an error flag number Ne reaches continuously a setting value TH1 or over in a voice noise reduction circuit 6, an operation control circuit 61e identifies a position of a synchronizing signal bit and a range bit being an output of a bit counter 61b to allow a frame synchronizing signal generating circuit 61f and a range data generating circuit 61g to replace the synchronizing signal bit and the range bit respectively and the replacement is continued till stop of replacement is commanded by passing a bit stream. Thus, even when the C/N is deteriorated, out of synchronism takes place or a range is in error, no large noise is outputted. Furthermore, when the C/N is deteriorated furthermore during the replacement and the Ne reaches a setting value TH2 or over, voice muting is applied, the output of the voice is blocked. When the Ne reaches the TH2 or below during muting, the muting is released and bit replacement is started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing device for a BS tuner, and more particularly to an audio signal for a BS tuner provided with an audio noise reduction control function and an audio mute control function when the condition of the satellite broadcast radio wave becomes poor. Regarding a processing device.

[0002]

2. Description of the Related Art In satellite broadcasting, a transmitting station uses a synchronization signal, a control code, range data, data-compressed M channels, and N sampling audio data for each frame (M = 4, N = 32 as described later). Or M = 2, N = 4
8) is included in the audio signal, and the audio signal is 5.727272MH.
DPSK modulation (Differential Phase Shift Key)
ing: differential phase modulation), the DPSK modulated signal is multiplexed with a 4.5 MHz video signal, and a 14 Hz main carrier is FM-modulated by the multiplexed signal and transmitted to a broadcasting satellite. The broadcasting satellite frequency-converts the radio wave from the transmitting station, amplifies it, and radiates it again toward the ground. The satellite broadcast receiver receives the broadcast radio waves sent from the broadcast satellite, separates the video signal and the audio signal after FM detection, and then performs a predetermined process to convert the video signal and the audio signal into the video device and the audio device. Output to.

FIG. 8 is a frame structure diagram of an audio signal.
One frame consists of 2048 bits and 1000 times per second
(The frame frequency is 1 KHz, and the cycle is 1 ms). The first 16-bit code in the frame structure indicates the beginning of the frame and is a synchronization signal for facilitating the reproduction of the bit clock on the receiving side.
It has a bit pattern of "001001101011110". The next 16-bit code of the frame synchronization signal is a control code (control signal), and as shown in FIG. 9, distinguishing between A and B modes, distinguishing between TV sound and independent sound, distinguishing between stereo and monaural, and mode switching. This is for distinguishing whether or not there is control for suppressing unnecessary noise that occurs when switching between program transmission stations and the like.

In the A mode, an analog audio signal for one channel is quantized into 14-bit data at a sampling frequency of 32 KHz, and then quasi-instantaneously compressed to 10-bit data (described later), and four channels are transmitted in one frame. The transmission speed is 32 KHz × 10 (bits) × 4 (channels) = 1280 Kb / s. Since 1 frame is 1ms, 1 in A mode
32 quantized data per channel (PC
M voice data) is included. In the B mode, an analog audio signal for one channel is quantized into 16-bit data at a sampling frequency of 48 KHz, and two channels are transmitted in one frame. The transmission rate is 48 KHz x 16 (bits) x 2 (channels) = 1536 Kb / s, and one frame contains 48 quantized data (PCM audio data) per channel. Since independent data and codes for error correction as well as voice data are transmitted, the code transmission rate including these codes is 2048 in both A and B modes.
Kb / s. FIG. 10 is a table for explaining the specifications of the voice coding method in the A and B modes.

Returning to FIG. 8, the next 32 bits (A mode) and 16 bits (B mode) of the control code are range bits, and as shown in FIG.
Bits are allocated bit by bit. Of the 8 bits, the first 3 bits are the range bits corresponding to the range number, the next 4 bits are the bits for correcting the range bit error that occurred during transmission, and the remaining 1 bit is empty.

As described above, in the A mode, quantization is performed with 14 bits, and quasi-instantaneous compression is performed with 10 bits for transmission. In this quasi-instantaneous compression method, as shown in FIG. 12 (A), it is determined in which range, 0 to range 4, the 14-bit audio signal level exists, and as shown in FIG. 12 (B),
It is a method of compressing 14-bit data into 10-bit data by (1) the range, (2) upper 9 bits of 14-bit audio data, and (3) 1-bit code. That is, 1
The maximum level of the audio signal is detected for each channel, it is determined which range of the range 0 to range 4 the maximum level exists, the existing range is expressed by 3 bits, and the audio signal level of the channel is determined. Expressed in 10 bits. In the B mode, the sound is 2 channels, so
The range bits are 16 bits which is half of the A mode, and the range bit portions corresponding to channels 3 and 4 of the A mode are used as independent data.

After the range bit, in the A mode, four channels of audio data are arranged for 32 samplings per channel, and then independent data and error correction code are arranged to form one frame. In the B mode, audio data for two channels is arranged for 48 samplings per channel, and then independent data and error correction code are arranged to form one frame. The last 7 × 32 bit error correction code of the frame has a high error correction effect and a BCH (6
3,56) code is adopted. In this code, 56 bits of the bit length 63 are information, and the remaining 7 bits are used for error correction. Among 56 bits, 1 bit error that occurred in the transmission path can be corrected and 2 bit error can be detected. It is like this.

The codes (2048
(Bit) is rearranged in units of 32 bits when transmitted (interleave). FIG. 13 is an interleaved matrix showing the sorting rules. The upper row is for A mode and the lower row is for B mode.
It is composed of 64 (= 2048) squares. Each frame of 2048-bit data is written in the memory in order in the horizontal direction, and one subframe is composed of 64 bits in the horizontal direction, has 32 subframes in total, and is read out from the memory in order in the vertical direction (arrow direction). Send. A subframe consists of one sync signal bit or control signal bit, one range bit,
Each is composed of 10 4-channel audio data, 15 independent data, and 7 error correction codes.
The 7-bit BCH (63,56) code is added to 56-bit information data excluding the sync signal bits or control signal bits to correct errors in these 56-bit information data. Errors in signals and control signals cannot be corrected. The reason for interleaving is
This is because even if a code is continuously lost or erroneous during transmission, the error is dispersed when the code is rearranged in the original order on the receiving side, and error correction (interpolation) is facilitated.

The code transmitted by bit interleaving may be consecutive 0 or 1 depending on the signal content. Even in such a case, a pseudo random signal is added so that 0 or 1 appears irregularly in order to facilitate the reproduction of the bit clock on the receiving side (scramble processing). The receiving side can descramble and restore using the same pseudo-random signal as the transmitting side. Then 5.72 with the scrambled digital signal
The 7272MHz subcarrier is DPSK-modulated, and the DPSK-modulated signal is adjusted to 4.5.
It is multiplexed with a video signal of MHz, and the 14 GHz main carrier is FM-modulated from the multiplexed signal and transmitted to a broadcasting satellite.

FIG. 14 is a block diagram of the transmitting side. Reference numeral 1 is a sampling circuit, which quantizes four channels of analog audio signals in the A mode, and quantizes two channels of analog audio signals in the B mode, and 2 represents audio data by a quasi-instantaneous compression method. 8 is a multiplexing circuit for multiplexing the audio data of each channel to form and outputting the frame shown in FIG. 8, 4 is an interleave circuit for performing bit interleaving processing, and 5 is a pseudo random signal. Scramble circuit for performing scramble processing by 6
Is a 4-phase DPSK circuit that DPSK-modulates the 5.727272MHz subcarrier with a scrambled digital signal, and divides the digital signal into groups of 2 bits each, (0,0), (1,0), (1,1 ),
The phase of the subcarrier is changed by associating (0, 1) with 0 ⁰ , 90 ⁰ , 180 ⁰ , -90 ⁰ . Reference numeral 7 is a synthesizing section for multiplexing a DPSK modulated signal with a 4.5 MHz video signal, and 8 is an FM modulating section for FM-modulating a 14 GHz main carrier from the multiplexed signal.

FIG. 15 is a block diagram of a satellite broadcast receiving apparatus, which is mounted on a vehicle. 11 is a BS antenna, 12 is a 12 GHz band satellite broadcast signal captured by the BS antenna at 1 GHz
A BS converter that converts to a band BS-IF signal (first frequency conversion) and then amplifies to a signal level required by the BS tuner. 13 extracts a video signal and an audio signal from the BS converter output signal. A BS tuner that controls a direction of a BS antenna while outputting after performing predetermined video processing and audio processing, 15 is a video device such as a television, 1
Reference numeral 6 is an audio circuit, 17 is a speaker, and 18 is a motor for changing the direction of the BS antenna, for example, a stepping motor.

In the BS tuner 13, 13a is a frequency conversion section (second frequency conversion section) for mixing a local oscillation signal determined by tuning and a BS-IF signal and converting it into a second intermediate frequency signal, and 13b is an intermediate frequency conversion section. An intermediate frequency amplification unit that amplifies the frequency signal, 13c performs FM detection, a video signal is separated by a 4.5MHz low pass filter, and an audio signal is separated by a 5.73MHz band pass filter. 13d is a video signal. A video signal processing unit that outputs a video signal by performing a predetermined process on the audio signal processing unit 13e, an audio signal processing unit 13e that performs a predetermined process on the audio signal and outputs an audio signal
Is a CN ratio detector for detecting a CN ratio (Carrier to Noise ratio). The CN ratio is the ratio of the magnitudes of the carrier signal and the noise signal contained therein, and indicates the radio wave condition. Reference numeral 13g is an antenna control unit for controlling the BS antenna 11 so as to face the broadcasting satellite, 13g-1 is a microcomputer, and 13g-2.
Is a gyro that detects the traveling direction of the vehicle, and 13g-3 is a motor controller. When the CN ratio falls below the threshold level, the microcomputer 13g-1 rotates the BS antenna 11 and directs the BS antenna in the direction in which the CN ratio becomes the largest.
Also, the microcomputer 13g-1 will change when the vehicle changes direction.
A change in the traveling direction is obtained from the gyro 13g-2, and the BS antenna 11 is rotated in the direction opposite to the changing direction so that the antenna is controlled to face the satellite.

FIG. 16 is a block diagram of the audio processing unit 13e, in which 21 is a 5.73 MHz bandpass filter for extracting the audio PCM subcarrier, and 22 is a bitstream signal which is a data string by phase-detecting the audio PCM subcarrier. Demodulate
A QPSK demodulator, which detects the phase of an input modulated signal with two quadrature carriers synchronized in phase with the modulated signal, converts the signal obtained by phase detection into a digital signal with a data strobe circuit, and then outputs the differential signal. The decoding circuit operates to restore the original signal. Reference numeral 23 is a PCM demodulation unit, 24 is a digital filter, and 25 is a DA for converting a digital audio signal into an analog signal.
It is a converter. The PCM demodulation unit 23 is the QPSK demodulation unit 22.
The descrambling circuit 23 receives the data stream signal from the descrambling circuit 23 and performs descrambling, deinterleaving, error correction, data decompression, and the like on the contrary to the transmitting side.
a, deinterleave circuit 23b, error detection and correction circuit 2
3c, companding decoding unit 23d, range bit extraction error correction circuit 23e, synchronization signal detection protection circuit 23f, control signal detection unit 23g, signal separation circuit 23h for separating an audio signal, and an error of 2 bits or more in audio data is detected. In this case, it has an error correction circuit 23i that interpolates and outputs the preceding and following audio data without using the audio data.

The sync signal detection protection section 23f detects the sync signal and protects it by using the correctly detected sync signal when the sync signal cannot be detected. The signal processing standard is a synchronization signal indicating the beginning of a frame, which is transmitted for each frame. If this frame synchronization signal cannot be detected correctly, all operations cannot be performed accurately.
Therefore, when it cannot be correctly detected due to noise or the like, the correctly detected synchronizing signal is used to generate a synchronizing signal to prevent malfunction of the synchronizing signal that has not been detected or lost. The control signal detector 23g detects a 16-bit control code (control signal). Since the control code is sent frame by frame, the control signal detection unit 23g makes a majority decision using the control code of n (for example, 36) frames to identify the control code and protect it against an error. For example, 3
When the A mode is detected 19 times or more among the 6 frames, the mode A is determined. The control code is used to detect the mode, the state of voice being transmitted, the presence or absence of scramble, and the like, and is used for voice mode display, video, and voice mute. Further, the A / B mode signal is input to the DA converter 25 to execute the DA conversion processing in synchronization with the sampling frequency according to the mode.

[0015]

In the BS tuner, when the radio wave is weak, a harsh voice noise is generated. This noise is mainly caused by an error in the range bit and a loss of the sync signal. Therefore, the following controls have been proposed. That is, the range bits are changed so that the range becomes 3 or 4 (range with low audio level) when the radio wave weakens and the CN ratio deteriorates.
When the CN ratio is good, the position of the synchronization signal is stored and C
When the N ratio deteriorates, the sync signal bits are replaced with the correct sync signal pattern. When the CN ratio further deteriorates, the audio mute is applied, when the CN ratio improves, the audio mute is released, and when the radio wave condition improves and the CN ratio becomes good, the replacement of the range bit and the synchronization signal bit is stopped. ing. According to this method, CN
Even if the ratio deteriorates, unpleasant voice noise can be reduced. It is the A mode that noise can be reduced by changing the range bit.

By the way, in the proposed method, CN
Focusing on the fact that the number of code error detections increases as the ratio deteriorates, switching is started and stopped based on the number of error detections (the number of error flags) per frame (1 ms period). The number of error flags is related to the CN ratio, but in a frame (1 ms), the number of error flags may be small even though the CN ratio is considerably deteriorated. In such a case, even if the CN ratio is poor, bit replacement is stopped, and there is a problem that noise that is offensive to the ear occurs. In the proposed method, bit replacement (voice noise reduction operation) is started when the number of error flags exceeds the first set value, and the second set value (> first set value) or more is started. When it becomes, the bit replacement is stopped and the audio is muted. However, according to such a method, there is a problem that the audio mute is applied even in a state where the audio with the noise reduced by the audio noise reduction operation can be output. This is because the relationship between the number of error flags and the deterioration of the CN ratio is not linear.

Furthermore, in the proposed method, bit replacement (voice noise reduction operation) is started when the number of error flags exceeds the first set value, and the second set value (>).
When the value exceeds the first set value), bit replacement is stopped and audio mute is performed. However, in such a method, even when the radio wave condition is relatively good during the voice noise reduction operation, if there is a sudden interruption of the radio wave due to a utility pole,
There is a problem that noise called "sersa" stands out. This is because the condition for applying audio mute is constant regardless of the sudden interruption of radio waves.

From the above, the first object of the present invention is not to stop the bit replacement operation (voice noise reduction operation) even if the number of error flags is small when the CN ratio is considerably deteriorated, and it is audible to the ear. To prevent the generation of noise. A second object of the present invention is to accurately judge the radio wave condition in which noise is annoying when outputting a voice to enable audio mute, and to mute the audio when noise is not annoying. Instead, it is to output the voice as long as possible. A third object of the present invention is to prevent the generation of noise by detecting a sudden cutoff of radio waves and muting audio.

[0019]

SUMMARY OF THE INVENTION According to the present invention, the above object is to provide a synchronization detection unit for detecting a frame synchronization signal from a bit stream and an error detection number detected by an error detection / correction process during a predetermined time. An error detection frequency monitoring unit for monitoring, a frame synchronization signal generation unit for internally generating a frame synchronization signal, a range data generation unit for internally generating predetermined range data, and a synchronization signal bit in the bit stream. A replacement timing generating unit that generates a replacement timing and a replacement timing of a range bit, and a range bit in the bit stream according to a bit replacement instruction, and the range data output from the range data generating unit at the range bit replacement timing The sync signal bit in A synchronizing signal and a range bit replacement unit replace the synchronization signal replacement timing synchronization signal output from the period signal generator, bit replacement start / stop on the basis of the error detection count and synchronization detection state,
And an audio signal processing device of a BS tuner having an operation control unit for controlling start / stop of audio mute.

[0020]

In the first aspect of the invention, the operation control unit instructs the bit replacement when the number of error detections exceeds the set value, and the bit when the number of error detections continuously falls below the set number of times. Instruct to stop the replacement operation. By doing so, it is possible to prevent the bit replacement operation (voice noise reduction operation) from being stopped even if the number of error flags happens to be small when the CN ratio is considerably deteriorated, so that noise that is annoying to the ear is generated. Can be prevented.

In the second invention, when the number of error detections exceeds the first set value TH1, the operation control unit instructs the bit replacement, and when the number of error detections is the first set value or more, the second control is performed. When the set value is equal to or less than TH2 (> TH1), the audio mute is performed when the synchronization loss is detected N1 times continuously, and when the number of error detections is the second set value or more, N2 (< N1) Audio mute is applied when out-of-sync is detected. By monitoring the number of times out of continuous synchronization, it is possible to accurately judge the radio wave condition where noise is annoying when outputting voice and mute the audio, so in a state where the output of voice does not cause annoyance. Can output audio as long as possible without muting audio. Further, in the third invention, the operation control unit instructs the bit replacement when the number of times of error detection becomes equal to or more than the first set value, and at least the second set value (> the first set value) or more. When the number of error detections this time is more than a predetermined value than the number of error detections last time, the audio mute is instructed even if the number of error detections is less than the second set value. To do. By doing so, it is possible to detect the sudden cutoff of the radio wave and perform the audio mute, and to prevent the generation of noise due to the sudden cutoff of the radio wave.

[0022]

【Example】

(A) First Embodiment of the Present Invention (a) Audio Signal Processing Device for BS Tuner FIG. 1 is a block diagram of an audio signal processing device for a BS tuner according to the present invention. Reference numeral 51 is an audio signal processing unit, which extracts an audio PCM subcarrier from the BS-IF signal output from the BS converter and performs QPSK demodulation, descrambling, deinterleaving, BCH error detection and correction processing, range bit correction processing, and audio data. Expansion (restoration) processing, mute control,
A unit that executes DA conversion processing, etc. 61 is a voice noise that replaces a range bit and a sync signal bit when the radio wave condition deteriorates to reduce voice noise, and instructs a voice mute when the radio wave condition further deteriorates. It is a reduction circuit.

In the audio signal processing unit 51, 51a is a 5.73 MHz bandpass filter for extracting an audio PCM subcarrier, and 51b is a QPSK demodulation unit for phase-detecting the audio PCM subcarrier and demodulating a bit stream signal which is a data string. , 51c receives a data stream signal from the QPSK demodulation unit 51b, and performs a descrambling circuit which performs a descrambling process in reverse to the transmitting side, 51d represents a deinterleave circuit,
51e is a BCH error detection / correction circuit, 51f is a companding decoding unit for expanding 10-bit audio data to 14 bits, 51g is an audio mute circuit, 51h is a DA converter, 51i is a BCH correction circuit for range bits, and 51j is synchronous. Reference numeral 51k is a control code detection unit that detects a signal and performs a synchronization protection operation when synchronization is lost. On the output side of the companding decoding unit 51g, there are provided a signal separation circuit for separating an audio signal, an error correction circuit for interpolating the preceding and following audio data when an error of 2 bits or more is detected in the audio data, a digital filter, etc. Exists but omitted.

(B) Audio Noise Reduction Circuit (b-1) Configuration FIG. 2 is a configuration diagram of the audio noise reduction circuit. 61a is Q
A synchronization detection circuit that detects a frame synchronization signal from the bit stream output from the PSK demodulation unit 51b, 61b is a 2048-bit counter that counts the clock signal reproduced from the received signal, and the detection timing of the frame synchronization signal when the radio wave condition is good Count the clock in synchronization with
A bit position in the frame of the received bit is output, 61c is an error flag comparator for identifying an error flag output from the BCH error detection / correction circuit 51e when an error is detected, and 61d is detected during one frame (1 ms). An error flag counter that counts the number of error flags Ne and is reset by a synchronization signal.
The error flag number Ne is related to the radio wave condition and tends to increase as the CN ratio deteriorates.

An operation control circuit 61e controls ON / OFF of the bit replacement operation and ON / OFF of the audio mute based on the error flag number Ne. That is, the operation control circuit 61e determines that the error flag number Ne is the first set value TH.
When it becomes 1 or more, bit replacement (voice reduction operation ON) is instructed, and the number of error flags N during voice reduction operation
When e has become equal to or less than the first set value TH1 a predetermined number of times in succession, an instruction to stop the bit replacement is made, and the error flag number Ne is set to the second set value TH2 (>) during the voice noise reduction operation.
When TH1) or more, the voice reduction operation is instructed to be stopped and the voice mute is instructed. When the error flag number Ne becomes the second set value TH2 or less during the voice mute, the voice mute is released. And the start of the voice reduction operation.

Reference numeral 61f is a frame synchronization signal generation circuit for internally generating a frame synchronization signal pattern "0001001101011110", and 61g is range data 11010010 or 00 indicating the lower range of the audio level (for example, range 3 or 4).
This is a range data generator that internally generates data obtained by multiplying 111010 by a scrambled bit string. Reference numeral 61h is a first switch, which normally passes the bit stream output from the BCH error detection / correction circuit 51e, but the synchronization output from the frame synchronization signal generation circuit 61f only when replacement of the synchronization signal is instructed. 61i is a second switch, which normally passes the bit stream output from the first switch 61h, but only when the replacement of range bits is instructed. The range data output from 61g is passed. 61f-61i
Thus, a synchronization signal and range bit replacement unit is formed.

Reference numeral 61j is a replacement timing generation circuit for generating the replacement timing of the range bit and the synchronization signal bit. The replacement timing generation circuit 61j is
When the bit replacement is instructed from the operation control circuit 61e, the sync signal bit position is identified from the bit position output from the bit counter 61b to replace the sync signal bit with the frame sync signal generation circuit 61f and the first switch 61h. To the range data generation circuit 61g and the second switch 61i.
Instruct.

(B-2) Operation Control Circuit FIG. 3 is a block diagram of the operation control circuit 61e. 71 is the number of error flags Ne, the first set value TH1, and the second set value T
This is a comparison unit that compares the magnitude of H2 (> TH1) and outputs the comparison result. Reference numeral 72 is a counter that stores the number n of times that the error flag number Ne has continuously become equal to or less than the first set value TH1, and is cleared when Ne> TH1 and Ne <
When it reaches TH1, it counts up by 1. Reference numeral 73 denotes a CN ratio deterioration / recovery determination unit which determines deterioration / recovery of the CN ratio based on the comparison result and the number of times n and instructs bit replacement ON / OFF and audio mute on / off. The CN ratio deterioration / recovery determination unit 73, when notified of Ne> TH1 from the comparison unit 71, instructs the replacement timing generation circuit 61j to start bit replacement (replacement operation ON), and Ne> T.
When H2 is notified, the mute circuit 51g is instructed to perform audio mute (audio mute on), and the replacement timing generation circuit 61j is instructed to stop bit replacement (replacement operation off). Further, the CN ratio deterioration / recovery determination unit 73 causes the comparison unit 71 to output Ne <TH2 during the audio mute.
Is notified, the mute circuit 51g is instructed to cancel the audio mute (audio mute off), and the replacement timing generation circuit 61j is instructed to start the bit replacement (replacement operation on). Further, the CN ratio deterioration / recovery determination unit 73 continuously sets the setting value Ns (for example, Ns = 3) or more during the bit replacement (during voice reduction operation), Ne <TH1.
When, ie, n ≧ Ns, the replacement timing generating circuit 61j is instructed to stop bit replacement (off replacement operation).

(C) Operation When the radio wave condition is good and the number of error flags is small, the bit stream output from the QPSK demodulation unit 51b is descrambled through the first and second switchers 61h and 61i. , Deinterleave circuit 51d descrambles and deinterleaves, and further BC
Companding decoding unit 51f via H error detection and correction circuit 51e
And the BCH correction circuit 51i for range bits. The BCH correction circuit 51i corrects an error in the range bit and notifies the companding decoding unit 51f of the range. The companding decoding unit 51f expands 10-bit audio data into 14-bit audio data based on the notified range and outputs the 14-bit audio data to the DA converter 51h. The DA converter 51 converts the audio data into an analog audio signal and inputs it to an external audio circuit.

When the radio wave condition deteriorates and the error flag number Ne exceeds the first set value TH1, the operation control circuit 61e instructs the replacement timing generation circuit 61j to start bit replacement (replacement operation ON). According to the instruction, the replacement timing generation circuit 61j causes the bit counter 61
The sync signal bit position is identified from the bit position output from b and the frame sync signal generation circuit 61f and the first switch 61h are instructed to replace the sync signal. The frame synchronization signal generation circuit 61f immediately generates a synchronization signal pattern, and the first switch 61h allows the synchronization signal pattern to pass therethrough, and thereafter allows the bit stream to pass therethrough. In addition, the replacement timing generation circuit 61j includes a bit counter 61
The range bit position is identified from the bit position output from b and the range data generation circuit 61g and the second switch 61i are instructed to replace the range bit. The range data generation circuit 61g immediately generates range data,
The switch 61i of (1) passes the range data, and thereafter passes the bit stream. The replacement timing generation circuit 61j controls the replacement of the synchronization signal bits and the range bits until the replacement is stopped, and replaces the synchronization signal bits and the range bits with the internally generated synchronization signal and predetermined range data. As a result, the signal condition deteriorates, and large noise is not output even if synchronization is lost or the range is incorrect.

During the replacement operation, when the CN ratio further deteriorates and the error flag number Ne becomes equal to or larger than the second set value TH2 (Ne> TH2), the operation control circuit 61e instructs the mute circuit 51g to mute the audio ( Audio mute on). As a result, the mute circuit 51g (FIG. 1) blocks the audio data output from the companding decoder 51f and blocks the audio data from being input to the DA converter 51h. Further, during the replacement operation, when the CN ratio becomes good and Ne <TH1 is continuously set value Ns (= 3) times or more (n ≧ Ns) (n ≧ Ns), the operation control circuit 61e transfers the bit to the replacement timing generation circuit 61j. Instruct to stop (replacement operation off). As a result, thereafter, the bit stream output from the QPSK demodulator is descrambled and deinterleaved by the descrambling circuit 51c and the deinterleaving circuit 51d via the first and second switching devices 61h and 61i, and the BCH error detection and correction are performed. Circuit 51e, companding decoder 51f, and BCH correction circuit 5 for range bits
Input to 1i.

During the mute operation, when the radio wave condition improves and the error flag number Ne becomes equal to or less than the second set value TH2 (Ne <TH2), the operation control circuit 61e instructs the mute circuit 51g to cancel the audio mute ( Along with the audio mute being turned off, the switching timing generating circuit 61j is instructed to start bit switching (switching operation on). As a result, the bit replacement operation described above is started. that's all,
According to the first embodiment, when the CN ratio is considerably deteriorated, even if the number of error flags is reduced, the bit replacement operation (voice noise reduction operation) is not stopped but continued, so that noise that is annoying to the ear is generated. Occurrence can be prevented.

(B) Second Embodiment (a) Configuration FIG. 4 is a configuration diagram of an audio noise reduction circuit of the second embodiment. The same parts as those of the audio noise reduction circuit of the first embodiment of FIG. 2 are the same. The code is attached. In FIG. 4, the first of FIG.
The difference from the embodiment is that the synchronous / asynchronous detection signal SDT is output from the synchronous detection circuit 61a, and the configuration and operation of the operation control circuit 61e '. The operation control circuit 61e 'controls ON / OFF of the bit replacement operation and ON / OFF of the audio mute based on the number of error flags Ne and the number of synchronous / asynchronous detections. That is, the operation control circuit 6
1e ′ indicates that the error flag number Ne is the first set value TH1.
When it becomes the above, the bit replacement is instructed, and when the error flag number Ne is not less than the first set value and not more than the second set value TH2 (TH2>Ne> TH1), N1 (for example, N1 = 16) When the loss of synchronization is detected, the audio mute is instructed and the bit replacement is stopped, and when the error flag number Ne is the second set value TH2 or more (Ne> TH2), N2 (for example, N
2 = 4) times audio mute is instructed when out of sync is detected and bit replacement is instructed to be stopped, and audio mute is continuously performed N3 times (for example, N3 = 36) during audio mute when a sync signal is detected. And release
When bit replacement is instructed and the number of error flags Ne becomes equal to or less than the first set value TH1 during bit replacement (N
e <TH1), and gives an instruction to stop the replacement operation.

FIG. 5 is a block diagram of the operation control circuit 61e '. Reference numeral 81 is an asynchronous detection counter, which counts the number m of times when synchronization is lost continuously, and is reset by the synchronization detection. Reference numeral 82 denotes a synchronization detection counter, which counts the number s of consecutive detections of the synchronization signal and is reset by the loss of synchronization detection. Reference numeral 83 denotes a noise reduction / mute operation control unit for controlling bit switching operation ON / OFF and audio mute ON / OFF based on the number of error flags Ne and the number of synchronous / asynchronous detections s and m.

(B) Operation FIG. 6 is a processing flow of the operation control circuit 61e '. The operation control circuit 61e 'monitors whether the number of error flags Ne has become equal to or greater than the first set value TH1 (step 101), and Ne
When> TH1, it is instructed to start bit replacement (voice reduction operation). As a result, the synchronization signal bit and the range bit are replaced (step 102). During such a voice reduction operation, the operation control circuit 61e 'is set to N
It is monitored whether e ≦ TH1 (step 103) and Ne ≦
When it becomes TH1, the audio noise reduction operation is stopped (step 104). However, if Ne> TH1, it is checked whether the error flag number Ne is not less than the first set value TH1 and not more than the second set value TH2 (step 1
05), if TH2>Ne> TH1, then N1 continuously.
(For example, N1 = 16) It is checked whether the synchronization loss is detected (step 106). If Ne> TH2, it is continuously checked whether the synchronization loss is detected N2 (eg N2 = 4) times or more (step 107). . Step 10
If the number m of consecutive out-of-synchronizations is 6 or less in 6 or if the number of consecutive m-out-of-synchronizations is 4 or less in step 107, the processing subsequent to step 102 is performed without stopping the audio noise reduction operation. repeat.

On the other hand, if the number of consecutive out-of-synchronizations m is 16 or more in step 106, or if the number of consecutive out-of-synchronizations m is 4 or more in step 107, the bit replacement operation (voice noise reduction operation). And the audio mute is instructed (step 10).
8). During the audio mute, it is checked whether or not the sync signal is continuously detected N3 (N3 is, for example, 36) times or more (step 109). If the sync signal continuous detection number s is not N3 times or more, the audio mute is continued, and N3 If it is more than once,
Cancel audio mute (step 110), step 1
Jump to 02 to start the audio noise reduction operation. As described above, according to the second embodiment, by monitoring the number of continuous out-of-synchronizations, it is possible to accurately determine the radio wave condition in which noise is annoying when audio is output and to mute the audio. If the sound is not annoying even if it is output, the sound can be output as long as possible without muting the sound.

(C) Third Embodiment (a) Configuration FIG. 7 is a composition of an operation control circuit in a third embodiment of the present invention. The audio noise reduction circuit in the third embodiment is shown in FIG.
Although it is the same as the second embodiment in the block diagram, the configuration and function of the operation control circuit are different. In the operation control circuit 61e ″, 91 is a comparison unit, 92 is an error flag count difference calculation unit that calculates a difference DF between the present error flag number and the previous error flag number, 93 is a rapid state change detection unit, and 94 is an OR gate. The comparison unit 91 determines that the error flag number Ne
Is instructed to change the bit (replacement operation is ON) when the value exceeds the first set value TH1 and the second set value TH
When the value exceeds 2 (> TH1), the audio mute is instructed (audio mute on), the bit replacement is stopped (replacement operation off), and when the second set value TH2 or less is reached during the audio mute. In addition to instructing to cancel audio mute (audio mute off), instructing bit replacement (replacement operation on), and instructing stop bit replacement when the first set value TH1 or less is reached during bit replacement (replacement operation off) ).

The abrupt state change detector 93 detects the difference DF between the current error flag number and the previous error flag number and the set number D.
S is compared, and when DF> DS, it is determined that the radio wave condition has deteriorated drastically, and audio mute is instructed. OR gate 94
Calculates the logical sum of the audio mute signals output from the comparison unit 91 and the abrupt state change detection unit 93 to instruct the mute circuit to perform the audio mute, or to instruct the cancellation of the audio mute.

(B) When the operation radio wave condition deteriorates and the error flag number Ne becomes equal to or larger than the first set value TH1, the operation control circuit 61e "instructs the replacement timing generation circuit 61j to start bit replacement (replacement operation ON). During the replacement operation, the CN ratio is further deteriorated and the error flag number Ne becomes the second set value TH2.
When the above is reached (Ne> TH2), the operation control circuit 61e ″
Instructs the mute circuit 51g to turn off the audio (turn on the audio mute) and turn off the replacement operation.
When the radio wave condition suddenly deteriorates during the replacement operation, the operation control circuit 61e ″ causes the error flag number Ne to be the second value.
Mute circuit 51g even if it does not exceed the set value TH2 of
Direct audio mute to (audio mute on). During mute operation, the radio wave condition has improved and the number of error flags N
When e becomes the second set value TH2 or less (Ne <TH
2), the operation control circuit 61e instructs the mute circuit 51g to cancel the audio mute (audio mute off), and
The replacement timing generation circuit 61j is instructed to start bit replacement (replacement operation ON). As a result, the bit replacement operation described above is started.

During the replacement operation, when the CN ratio becomes good and the error flag number Ne becomes equal to or less than the first set value TH1 (Ne <TH1), the replacement timing generation circuit 6
1j is instructed to stop bit replacement (off switching operation). According to the third embodiment, it is possible to detect the sudden cutoff of radio waves and perform the audio mute, and it is possible to prevent the generation of noise due to the sudden cutoff of radio waves. Although the present invention has been described above with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention described in the claims, and the present invention does not exclude these.

[0041]

As described above, according to the present invention, it is possible to prevent the bit replacement operation (voice noise reduction operation) from being stopped even if the number of error flags happens to be small when the CN ratio is considerably deteriorated. It is possible to prevent the generation of annoying noise. Further, according to the present invention, by monitoring the number of times of continuous synchronization loss, it is possible to accurately determine the radio wave condition in which noise is annoying when outputting voice, and to mute the voice, and thus output the voice. Even if the sound is not offensive to the ear, the sound can be output as long as possible without applying the sound mute. Further, according to the present invention, when the error detection number of this time is a predetermined value or more than the error detection number of the previous time, the audio mute is instructed, so that the generation of noise due to the sudden interruption of the radio wave is prevented. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an audio signal processing device of a BS tuner of the present invention.

FIG. 2 is a configuration diagram of an audio noise reduction circuit according to the first embodiment.

FIG. 3 is a configuration diagram of an operation control circuit according to the first embodiment.

FIG. 4 is a configuration diagram of an audio noise reduction circuit according to a second embodiment.

FIG. 5 is a configuration diagram of an operation control circuit according to a second embodiment.

FIG. 6 is a processing flowchart of the operation control circuit according to the second embodiment.

FIG. 7 is a configuration diagram of an operation control circuit according to a third embodiment.

FIG. 8 is a frame configuration diagram of an audio signal.

FIG. 9 is an explanatory diagram of control codes.

FIG. 10 is a table for explaining specifications of a voice encoding system.

FIG. 11 is an explanatory diagram of a range bit.

FIG. 12 is an explanatory diagram of quasi-instantaneous compression.

FIG. 13 is an explanatory diagram of interleaving.

FIG. 14 is a block diagram of a transmitting side of satellite broadcasting.

FIG. 15 is a configuration diagram of a conventional satellite broadcast receiving device.

FIG. 16 is a configuration diagram of a conventional audio signal processing unit.

[Explanation of symbols]

 51..Voice signal processing unit 51e..BCH error detection / correction circuit 51g..Mute circuit 61..Voice noise reduction circuit

Claims (3)

[Claims] 1. A demodulation of a voice signal including a sync signal, a control code, a range data, and a data-compressed voice data for M channels and N samplings for each frame, and error detection and correction processing is performed on the demodulated bit stream. In the audio signal processing device of the BS tuner, which outputs the audio data in the error-corrected bit stream and decompresses the audio data in the bit stream and inputs the audio data to the DA converter, the error detection and correction process is performed within a predetermined time. An error detection number monitoring unit for monitoring the number of error detections detected by the above, a frame synchronization signal generation unit for internally generating a frame synchronization signal, a range data generation unit for internally generating predetermined range data, and Sync signal bit replacement timing and range bit replacement timing in bit stream A replacement timing generating unit that generates a range bit and a range bit in the bitstream according to a bit replacement instruction are replaced at the range bit replacement timing by the range data output from the range data generating unit, and a synchronization signal bit in the bitstream is the synchronization signal. A sync signal and range bit replacement part that replaces the sync signal at the sync signal replacement timing with the sync signal output from the generation part, and when the number of error detections exceeds the set value, instructs the bit replacement of the sync signal bit and the range bit, An audio signal processing device for a BS tuner, comprising: an operation control section for instructing to stop bit replacement of a synchronization signal bit and a range bit when the number of error detections is continuously below a predetermined value. 2. A demodulated audio signal containing a sync signal, a control code, range data and audio data for M channels and N samplings for each frame, demodulated for each frame, and subjected to error detection and correction processing on the demodulated bit stream. In the audio signal processing device of the BS tuner, which outputs the audio data in the error-corrected bit stream and decompresses the audio data in the bit stream, and inputs the audio data to the DA converter, the frame synchronization signal is detected from the bit stream. A synchronization detection unit, an error detection number monitoring unit that monitors the number of error detections detected by error detection and correction processing within a predetermined time, a frame synchronization signal generation unit that internally generates a frame synchronization signal, and a predetermined range A range data generator that internally generates data, and a sync signal signal in the bit stream. And a range timing generating unit that generates a range timing and a range bit changing timing, and a range bit in the bitstream according to the bit changing instruction, and the range data output from the range data generating unit at the range bit changing timing. A synchronization signal and range bit replacement unit that replaces the synchronization signal bit in the bit stream with the synchronization signal output from the synchronization signal generation unit at the synchronization signal replacement timing, and when the number of error detections exceeds the first set value TH1. ,
Instructing bit replacement of the synchronization signal bit and the range bit, and when the number of error detections is greater than or equal to the first setting value and less than or equal to the second setting value TH2 (> TH1), N consecutive
Operation to mute audio when once out-of-sync is detected, and to mute sound when N2 (<N1) out-of-sync is detected consecutively when the number of error detections is equal to or greater than the second set value. An audio signal processing device of a BS tuner having a control unit. 3. A demodulation of a voice signal containing a sync signal, control code, range data and voice data for M channels and N samplings for each frame for each frame, and error detection and correction processing is performed on the demodulated bit stream. In the audio signal processing device of the BS tuner, which outputs the audio data in the error-corrected bit stream and decompresses the audio data in the bit stream and inputs the audio data to the DA converter, the error detection and correction process is performed within a predetermined time. An error detection number monitoring unit for monitoring the number of error detections detected by the above, a frame synchronization signal generation unit for internally generating a frame synchronization signal, a range data generation unit for internally generating predetermined range data, and Sync signal bit replacement timing and range bit replacement timing in bit stream A replacement timing generating unit that generates a range bit and a range bit in the bitstream according to a bit replacement instruction are replaced at the range bit replacement timing by the range data output from the range data generating unit, and a synchronization signal bit in the bitstream is the synchronization signal. Synchronous signal output from the generator The synchronous signal and range bit replacement unit that replaces the synchronous signal at the timing of replacing the synchronous signal, and the instruction to replace the synchronous signal bit and the range bit when the error detection count exceeds the first set value. In addition, when the audio mute is instructed when the number of errors exceeds the second set value, and the number of error detections this time is more than a predetermined value than the number of error detections last time, the number of error detections is set to the second set value. Operation to instruct audio mute even if it is less than the value Audio signal processing apparatus BS tuner having a control unit.