JPH0831844B2 - Error recovery device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to HDLC (High Lev) which is one of communication control systems for data transmission in computers and satellite communications.
el Date Link Control Procedures) error recovery.

(2) Background of technology When communication is performed between a computer and terminals, or between terminals in a computer system, or when communication is performed between ground stations in satellite communication, the communication line has been connected. It is necessary to check the information, the addresses of the local station and the partner station, confirm that the information message was transmitted correctly, and confirm that the information message has been sent. In such communication control, HDLC (High L
evel Data Link Control Procedure).

In HDLC, information messages and control information are transmitted and received in block units called frames surrounded by specific bit patterns (flags). FIG. 1 shows the structure of this frame. The flag F indicates a frame delimiter, and is represented by a 1-byte bit pattern "01111110". Address field A is a field (about 1 byte) for displaying the addresses of the sender and receiver
The control field C is a field (1 to 1) used for control such as frame type designation and number management (described later).
2 bytes). The information message to be transmitted is written in the I field. The frame check sequence FCS is a bit sequence (about 2 bytes) used to confirm whether or not the bit pattern of each field is correctly transmitted by an error control method called a cyclic check (CRC) method.

When information messages are transmitted / received by the frame having the above configuration, the frame numbers are managed as the transmission sequence number and the reception sequence number, and the frame currently transmitted by the transmitting side is the number of the frame, and the receiving side by the receiving side. It is inserted in each frame as information indicating up to what frame the frame has been received. With such a configuration, frames can be transmitted one after another without waiting for a response from the receiving side for each transmission frame, and communication with high transmission efficiency can be performed.

In such a system, it is important to perform accurate and speedy error control in order to perform highly reliable transmission.

(3) Conventional technology and problems In order to perform error control in HDLC, the cyclic check (CRC) method using the frame check sequence FCS in Fig. 1 is used for error control of each bit pattern in the frame. However, the description of the method is omitted in this embodiment. Other errors include the error that frames are completely lost in the communication line. As a control for such an error, there is a method in which the receiving side monitors the transmission sequence number of the frame sent from the transmitting side. The method will be described with reference to FIG. Each | I (j, k) sent from the sender
| Indicates a frame including an information message whose transmission sequence number is j and whose reception sequence number is k.
Since no reception sequence number is used here, it is assumed that k = 0. If five frames of information messages are transmitted from the transmission side, the transmission sequence numbers should be sequentially received from 0 to 4 when the transmission sequence number of each frame received by the reception side is monitored. However, if the receiving side receives only the transmission sequence numbers 1 and 4 (frames indicated by a circle on the receiving side in FIG. 2), the frames having the transmission sequence numbers 0, 2, and 3 are not correctly received. You can see that (the frame indicated by × in the figure). Therefore, the receiving side can notify the transmitting side of the transmission sequence number of the frame that was not correctly received, and can request the retransmission (called retransmission) of the frame. Selective reject (hereinafter SREJ)
It is realized by sending a frame called SREJ frame from the receiving side to the transmitting side. SR
The EJ frame is configured by writing a bit pattern indicating SREJ in the control field C in the frame structure of FIG. 1 and further writing an erroneous transmission sequence number in the frame as a reception sequence number of the SREJ frame. In FIG. 2, an error in the transmission sequence number is detected on the receiving side, and first the transmission sequence number 0
SREJ frame | SREJ (0) | is sent to the sender. Here, | SREJ (l) | indicates an SREJ frame having an erroneous transmission sequence number l as a reception sequence number. The transmitting side receives | SREJ (0) | and retransmits to the receiving side a frame | I (0,0) | containing an information message having the same transmitting sequence number as the receiving sequence number 0.
If the receiving side receives | SREJ (0) | and is retransmitted within a certain time after receiving | I (0,0) |,
It is assumed that the frame with the transmission sequence number 0 is correctly received. Next, since | I (4,0) | is received, | SREJ (2) | for the transmission sequence number 2 is transmitted. Continue | SREJ
(3) | is sent, but | I (2,0) | is incorrect and | I (3,0)
| Was received correctly.

A timer that starts or restarts a timer when an I frame is transmitted and stops when all the transmitted I frames can be confirmed to monitor whether or not the transmitted I frame is correctly received by the receiving side. Is provided to transmit an RR / P frame for inquiring the receiving side of the reception status of the I frame at the time-out. The receiver is
| I (2,0) | was not received correctly, so | SREJ (2) F
Send |. The transmitting side responds to | SREJ (2) F | with | I (2,
0) | is sent to start the timer. This method
There is a problem that error recovery takes a long time in a satellite line or a high-speed line with a large propagation delay.

(4) Object of the Invention In order to eliminate the above problems, the present invention provides a means for sequentially storing the reception sequence numbers of the transmitted SREJ frames, thereby making it possible to transmit a plurality of SREJ frames while a retransmission frame is transmitted. -The purpose is to provide a recovery device.

(5) Configuration of the Invention According to the present invention, in an HDLC communication control device, a sequential storage unit that sequentially stores the sequence numbers included in a retransmission request frame in the order in which the retransmission request frame is transmitted, and a sequence included in a received retransmission frame. Comparing means for comparing the number with the oldest sequence number stored in the sequential storage means, and corresponding to the oldest stored sequence number in the sequential storage means based on the comparison result by this comparing means. Provided is an error recovery device having a transfer error detecting means for detecting a transfer error of a retransmission frame.

(6) Examples of the Invention Hereinafter, examples of the present invention will be described in detail.

FIG. 3 is a diagram for explaining the principle of the error recovery device according to the present invention. In Fig. 3 (a) | I
(0,0) |, ... and | SREJ (0) |, ... mean the second
This is similar to the case of the conventional example in the figure. First, the information message is transmitted from the transmission side to the reception side as an information I frame of 5 frames. That is, the transmission sequence number of the information I frame of 5 frames transmitted from the transmission side is from 0 to 4. Next, it is assumed that the receiving side cannot receive the information I frames having the transmission sequence numbers of 0, 2, and 3 (third part).
The state S _{0 in} FIG. As a SREJ frame having the transmission sequence numbers 0, 2, and 3 of the information I frame that could not be received as reception sequence numbers, | SREJ (0) |, | SREJ
(2) |, and | SREJ (3) | are sequentially transmitted from the receiving side to the transmitting side (states S1, S2, S3 in FIG. 3 (a)). The receiving side is provided with a storage means (hereinafter referred to as a queue) for storing the reception sequence numbers 0, 2, and 3 of the SREJ frame transmitted at this time in the order of transmission. FIG. 3B shows the operating principle therefor. Also, in FIG. 3 (a), | S
When REJ (0) | is transmitted (state S1), the reception sequence number 0 is stored in the queue (hereinafter referred to as queue-in). That is, the state becomes the state S1 in FIG. 3 (b). At this time, as shown in FIG. 3B, each reception sequence number is input to the queue from the left side. Subsequently, in FIG. 3A, when | SREJ (2) | and | SREJ (3) | are sequentially transmitted (states S2 and S3), those reception sequence numbers 2 and 3 are sequentially queued in the queue. That is, the states are S2 and S3 in FIG. As a result, the reception sequence number of the SREJ frame sent to the queue is 0, 2, 3
Are stored in the order of transmission (state S in FIG. 3 (b))
3). Next, on the transmitting side, each SRE sent from the receiving side
J frames are received, and as information I frames having the same transmission sequence number as the reception sequence numbers 0,2,3 of each SREJ frame, | I (0,0) |, | (2,0) |, and | I
(3,0) | is retransmitted to the receiving side in order (hereinafter called retransmission)
To do. That is, these retransmitted I frames are retransmitted to the receiving side again as information I frames that the receiving side could not previously receive. Then, the receiving side receives the retransmitted I frame retransmitted from the transmitting side. First, the retransmission I frame | I (0,0) | of the transmission sequence number 0 is received (state S4 in FIG. 3 (a)). The transmission sequence number 0 of this retransmission I frame should be the same as the number stored at the head of the queue. That is, the retransmitted I-frames having the transmission sequence numbers corresponding to them should be received in the order of the reception sequence numbers of the SREJ frames transmitted previously. Therefore, first, the retransmission I frame | (0,0) | of the transmission sequence number 0 is received, and if the transmission sequence number 0 matches the number stored at the head of the queue, the retransmission I frame is transmitted.
It is assumed that the frame | I (0,0) | is normally received, and the number is taken out of the queue (hereinafter referred to as queue out). That is, the state becomes S4 in FIG. 3 (b). At this time, as shown in FIG. 3B, the head number of the queue is taken out from the right side of the queue. As a result, the number stored at the head of the queue becomes 2, which is compared with the number stored in the retransmission I frame received next. However, it is assumed that the retransmitted I frame | I (2,0) | of the transmission sequence number 2 cannot be received again in the state S5 of FIG. 3 (a). (This indicates that an error occurred when sending | SREJ (2) | or sending | I (2,0) |.) In this case, | I (2,0) | Since the message was not received, the contents of the queue do not change (state S5 in FIG. 3 (b)). Then, in the state S6 of FIG. 3A, the retransmission I frame of the transmission sequence number 3 | (3,
0) | is received. This compares that number with the number stored at the beginning of the queue, but 2 is stored at the beginning of the queue. Therefore, since the numbers do not match, the receiving side knows that the retransmission I frame with the transmission sequence number 2 could not be received normally. Therefore, the number 2 at the head of the queue is first cueed out on the receiving side (state S6-1 in FIG. 3B). SREJ frame with that number as the receive sequence number | SREJ
(2) | is sent to the transmitting side again, and | I (2,0) | is retransmitted. At this time, since the SREJ frame has been sent, its number 2 is queued in the queue (state in Fig. 3 (b)).
S6-2). In this way, the error correction process for the retransmitted I frame of transmission sequence number 2 is completed. Then, the transmission sequence number 3 of the retransmission I frame | I (3,0) | received in the state S6 is compared with the reception sequence number 3 at the head of the queue. As a result, since both match, | I (3,0) | is assumed to be received normally, and the number is queued out. That is, the state S6-3 in FIG. 3 (b)
become that way. As a result, it can be seen that only the number 2 remains in the queue and the retransmitted I frame having the transmission sequence number 2 has not been normally received. Finally, in the state S7 of FIG. 3 (a), the retransmitted I frame | I
When (2,0) | is retransmitted and is received normally at the receiving side,
The transmission sequence number 2 coincides with the number stored at the head of the queue, and 2 is queued out to complete the error correction (state S7 in FIG. 3B). As described above, when the SREJ frame is transmitted on the receiving side, the reception sequence number is queued in, the retransmission I frame is received, and when the transmission sequence number matches the number at the head of the queue, it is queued out. By doing this, if the numbers do not match, it can be seen that a retransmitted I frame having the number at the head of the queue as the transmission sequence number has caused an error, and the corresponding SREJ frame is sent again, and the same processing is performed. By repeating, SREJ frames can be sent one after another. That is, the present invention utilizes the assumption that the sending order of SREJ frames and the receiving order of retransmitted I frames always match, and if the order is incorrect, it is determined that an error has occurred.

FIG. 4 is an overall configuration diagram of an error recovery device according to the present invention for realizing the above principle. The transmission information message from the channel 1 includes an inter-channel transmission / reception control circuit 2, an I frame creation circuit 3, a scheduling control circuit 4,
The signals are input in the order of the line transmission control circuit 5 and sent to the line 6. The reception information message from the line 6 is input to the line reception control circuit 7, and the line reception control circuit 7 receives the I frame sequence control circuit 8, the I frame retransmission control circuit 9, and the sequence error / retransmission I frame reception detection circuit 10. Connected to. The reception information message from the reception I-frame order control circuit 8 is sent to the channel 1 via the inter-channel transmission / reception control circuit 2, and the I-frame retransmission control circuit 9 is connected to the scheduling control circuit 9. Sequence error
The retransmission I frame reception detection circuit 10 is connected to the SREJ frame transmission control circuit 11, and the SREJ frame transmission control circuit 11 is mutually connected to the queue control circuit 12 and the scheduling control circuit 4.

The operation when the error recovery device having the above-mentioned configuration is on the transmitting side will be described first. The transmission information message input from the channel 1 is input to the I frame creation circuit 3 via the inter-channel transmission / reception control circuit 2. The I-frame creating circuit 3 creates an information I-frame of the format shown in FIG. 1 and is time-controlled by the scheduling control circuit 4 and then transmitted from the line 6 to the receiving side via the line transmission control circuit 5. Further, when the SREJ frame for the resend request is input from the receiving side to the line reception control circuit 7, the SR input in the I frame resend control circuit 9
The information I frame having the reception sequence number of the EJ frame as the transmission sequence number is retransmitted from the line 6 to the receiving side via the scheduling control circuit 4 and the line transmission control circuit 5 (see the principle of FIG. 3).

Next, the operation when the error recovery device of FIG. 4 is on the receiving side will be described with reference to the flowchart of FIG. First, when information I frames are input from the transmitting side to the line reception control circuit 7 via the line 6, if they are normally received, those information I frames are input to the reception I frame order control circuit 8. This is shown in FIG.
Corresponds to the information I frame marked with a circle in the state S0. On the other hand, when the sequence error / retransmission I-frame reception detection circuit 10 of FIG. 4 detects that the information I-frame is not normally received as indicated by the cross mark in the state S0 of FIG. 3 (a), SR is an SREJ frame that has the transmission sequence number of the information I frame in which the error occurred as the reception sequence number.
Created in the EJ frame transmission control circuit 11. Then, the reception sequence number N (R) is queued in the queue in the queue control circuit 12 (in FIG. 5 (a)). Then, the SREJ frame is transmitted from the line 6 to the transmitting side via the scheduling control circuit 4 and the line transmission control circuit 5 (in FIG. 5 (a)). The above operation (operation of FIG. 5A) is performed for all the information I frames in which an error has occurred. From the above, the state S1 of FIGS. 3 (a) and 3 (b) is obtained.
~ The operation corresponding to S3 is performed. Next, line 6 from the sender
When a retransmitted I frame is input to the line reception control circuit 7 via the, it is determined whether the transmission sequence number N (S) matches the number stored at the head of the queue in the queue control circuit 12 as a sequence error. The judgment is made by the SREJ frame transmission control circuit 11 via the retransmission I-frame reception detection circuit 10 (in FIG. 5 (b)). If they match, the number is queued out from the queue in the queue control circuit 12 (FIG. 5B), and the retransmitted I frame is input to the reception I frame order control circuit 8 as if it was normally received. From the above, the state S4 of FIGS. 3 (a) and 3 (b) is obtained.
And an operation corresponding to S7 is performed. On the other hand, if the numbers do not match, the _first number Q ₁ of the queue in the queue control circuit 12
Assuming that the retransmission I frame having the transmission sequence number N (S) is not normally received, the SREJ frame having that number as the reception sequence number N (R) is transmitted again (in FIG. 5 (b)). . Here, SREJ (Q ₁ ) indicates a SERJ frame whose reception sequence number is Q ₁ . The operation at this time follows the flowchart of FIG. After that, the head number of the queue in the queue control circuit 12 is queued out Q _OUT, Q ₁ is taken out from the queue, and then the operation of the flow in FIG. 5B is performed. From the above, the states S6 (S6-1, S6-2, S6 in FIGS. 3A and 3B) are obtained.
The operation corresponding to (3) is performed. As a result of the above operation,
When all the retransmitted I-frames are received and the error recovery is completed, the received I-frame order control circuit 8 arranges the order of the received I-frames, and the received information message is extracted from the received I-frames and the inter-channel transmission / reception control circuit 2
Is sent to channel 1 via.

The error recovery device as described above can improve the line utilization efficiency during error recovery. Further, by combining the present invention with a conventional timer, it is possible to perform more efficient error recovery control.

(7) Effects of the Invention According to the present invention, error recovery can be performed without using complicated timer control or the like by using a queue controlled according to the transmission of SREJ frames and the reception of retransmitted I frames. As a result, a plurality of SREJ frames can be transmitted without waiting for the reception of the retransmitted I frame, so that the line utilization efficiency can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the structure of an HDLC frame, FIG. 2 is an explanatory diagram of conventional error control, and FIG. 3 (a) is an explanatory diagram of error control according to the present invention. FIG. 3 (b) is a diagram for explaining the operation of the queue according to the present invention, FIG. 4 is an overall configuration diagram of the error recovery device according to the present invention, and FIG. 5 is an error recovery device according to the present invention.
It is an operation | movement flowchart of a recovery apparatus. 1 …… Channel, 2 …… Channel transmission / reception control circuit, 3 ……
I-frame creation circuit, 4 ... Scheduling control circuit, 5
...... Line transmission control circuit, 6 ...... Line, 7 ...... Line reception control circuit, 8 ...... Reception I frame sequence control circuit, 9 ...... I frame retransmission control circuit, 10 ...... Sequence error / retransmission I frame reception detection Circuit, 11 …… SREJ frame transmission control circuit, 12…
... Queue control circuit.

Claims (2)

[Claims] 1. An HDLC communication control device, wherein a sequential storage means for sequentially storing sequence numbers included in the retransmission request frame in the order of transmission of the retransmission request frame, a sequence number included in the received retransmission frame and the sequential storage Comparing means for comparing with the oldest sequence number stored in the means, and a transfer error of the retransmission frame corresponding to the oldest sequence number stored in the sequential storage means, based on the comparison result by the comparing means. And an error recovery device for detecting transfer error. 2. A control means for storing the sequence number in which the transfer error is detected by the transfer error detection means again in the sequential storage means, and for transmitting a retransmission request frame including the sequence number again. The error recovery device according to claim 1.