JPH08316470A - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JPH08316470A JPH08316470A JP7123309A JP12330995A JPH08316470A JP H08316470 A JPH08316470 A JP H08316470A JP 7123309 A JP7123309 A JP 7123309A JP 12330995 A JP12330995 A JP 12330995A JP H08316470 A JPH08316470 A JP H08316470A
- Authority
- JP
- Japan
- Prior art keywords
- region
- groove
- semiconductor substrate
- gate
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000002344 surface layer Substances 0.000 claims abstract description 12
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 11
- 230000003068 static effect Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 35
- 230000015556 catabolic process Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、炭化ケイ素等のバン
ドギャップの大きな半導体材料で製作した高耐圧、大電
流を制御する電力用半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor element for controlling a high withstand voltage and a large current, which is manufactured from a semiconductor material having a large band gap such as silicon carbide.
【０００２】[0002]
【従来の技術】電力用半導体素子は、現在半導体材料と
してシリコンが最も多く使用され、また用途に応じて様
々な構造が適用されている。その一つに、Tsengyau Sya
u et al IEEE TRANSACTION ON ERECTRON DEVICES.VOL.4
1,NO.5,MAY (1994) pp.800〜808 や特開平２−１５６７
７で開示されている構造があり、その構造について以下
に説明する。2. Description of the Related Art In power semiconductor devices, silicon is currently most often used as a semiconductor material, and various structures are applied depending on the application. One of them is Tsengyau Sya
u et al IEEE TRANSACTION ON ERECTRON DEVICES.VOL.4
1, NO.5, MAY (1994) pp.800-808 and JP-A-2-1567.
7 is disclosed, and the structure will be described below.
【０００３】図４は従来素子の断面構造図を示す。ｎ形
の半導体基板１の一方の主面（第１主面）の表面層にゲ
ート溝１３が形成され、このゲート溝１３の表面上にゲ
ート絶縁膜３を介してゲート電極２が形成される。この
ゲート溝１３に囲まれた半導体基板１の表面層にｎ+ ソ
ース領域４が形成される。半導体基板１でゲート溝１３
に囲まれた領域は第１ドリフト領域５となり、その下の
領域は第２ドリフト領域６となる。半導体基板１の他方
の主面（第２主面）の表面層にｎ+ ドレイン領域７が形
成され、ｎ+ ドレイン領域７上にドレイン電極１０が形
成される。第１ドリフト領域５の幅Ｗが極めて狭いた
め、ｎ+ ソース電極８は各セル（単位素子）に設けられ
ず、セルを構成していない半導体基板１上に設ける。そ
の場合、同図の右側にあるように、半導体基板１のｎ層
から電気的に分離するために、ｐ領域２１を形成しその
表面層にｎ+ ソース領域４を形成し、その表面にソース
電極８を形成する。FIG. 4 is a sectional view showing the structure of a conventional device. A gate groove 13 is formed in the surface layer of one main surface (first main surface) of the n-type semiconductor substrate 1, and a gate electrode 2 is formed on the surface of this gate groove 13 via a gate insulating film 3. . An n + source region 4 is formed in the surface layer of the semiconductor substrate 1 surrounded by the gate groove 13. Gate groove 13 in semiconductor substrate 1
The region surrounded by becomes the first drift region 5, and the region thereunder becomes the second drift region 6. An n + drain region 7 is formed on the surface layer of the other main surface (second main surface) of the semiconductor substrate 1, and a drain electrode 10 is formed on the n + drain region 7. Since the width W of the first drift region 5 is extremely narrow, the n + source electrode 8 is not provided in each cell (unit element) but is provided on the semiconductor substrate 1 that does not form a cell. In that case, as shown on the right side of the figure, in order to electrically isolate from the n layer of the semiconductor substrate 1, the p region 21 is formed, the n + source region 4 is formed in the surface layer thereof, and the source is formed on the surface thereof. The electrode 8 is formed.
【０００４】つぎにこの素子の動作を説明する。ゲート
電極２に正、ソース電極８に負のゲート電圧を印加する
と、第１ドリフト領域５に空乏層１１が拡がり、その空
乏層端１２が接すると、つまり空乏層１１が閉じた段階
でｎ+ ソース領域４からｎ+ドレイン領域７へ流れる電
子電流路が絶れる。従って、ソース電極８に負、ドレイ
ン電極１０に正の電圧を印加すると、空乏層１１が閉じ
るまではドレイン電流が流れ、空乏層１１が閉じた段階
でドレイン電流は遮断する。Next, the operation of this element will be described. When a positive gate voltage is applied to the gate electrode 2 and a negative gate voltage is applied to the source electrode 8, the depletion layer 11 spreads to the first drift region 5 and its depletion layer end 12 contacts, that is, when the depletion layer 11 is closed, n + The electron current path from the source region 4 to the n + drain region 7 is cut off. Therefore, when a negative voltage is applied to the source electrode 8 and a positive voltage is applied to the drain electrode 10, a drain current flows until the depletion layer 11 is closed, and the drain current is cut off when the depletion layer 11 is closed.
【０００５】[0005]
【発明が解決しようとする課題】前記の構造において
は、ソース電極８下のｐ領域２１から少数キャリアであ
る正孔が瞬時にｎ形の第一ドリフト領域５に第２ドリフ
ト領域６を介して注入されるので、ゲート電圧を印加し
た直後から空乏層端１２は、静的状態つまり反転層が正
孔によって形成された状態と、同一の伸びとなり、その
ためゲート電圧を印加した直後に空乏層端１２を、静的
状態より一時的に拡げて、静的耐圧より高い耐圧を保持
させることはできない。In the above structure, holes, which are minority carriers, are instantaneously transferred from the p region 21 under the source electrode 8 to the n-type first drift region 5 through the second drift region 6. Immediately after the gate voltage is applied, the depletion layer end 12 has the same extension as that in the static state, that is, the state in which the inversion layer is formed by holes. Therefore, the depletion layer end 12 immediately after the gate voltage is applied. 12 cannot be temporarily expanded from the static state to maintain a withstand voltage higher than the static withstand voltage.
【０００６】この発明は、前記課題を解決するために、
ｐｎ接合を含まない構造にして、さらに半導体基板にバ
ンドギャップの大きい半導体材料を使用することによっ
て、静的耐圧より高い耐圧を確保し、かつこの耐圧を保
持する時間を増大させることができる電力用半導体素子
を提供することを目的とする。[0006] The present invention, in order to solve the above problems,
By using a structure that does not include a pn junction and using a semiconductor material with a large bandgap for the semiconductor substrate, a withstand voltage higher than the static withstand voltage can be secured and the time for holding this withstand voltage can be increased. An object is to provide a semiconductor device.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
に、半導体基板の第一主面の表面層に選択的に溝を形成
し、該溝で囲まれた第一主面上にソース電極を形成し、
該溝の表面上に絶縁膜を介してゲート電極を形成し、第
二主面上にドレイン電極を形成して、トレンチ構造のＭ
ＯＳＦＥＴを構成し、前記半導体基板に１．５ｅＶ以上
のバンドギャップを有する半導体材料を使用する。この
半導体基板の材料が炭化ケイ素であるとよい。また溝で
囲まれた第一主面の表面層と、第二主面の表面層とに半
導体基板と同一導電形の高濃度のソース領域と、ドレイ
ン領域とをそれぞれ形成し、ソース領域上にソース電極
と、ドレイン領域上にドレイン電極とをそれぞれ形成す
る。To achieve the above object, a groove is selectively formed in a surface layer of a first main surface of a semiconductor substrate, and a source electrode is formed on the first main surface surrounded by the groove. To form
A gate electrode is formed on the surface of the groove via an insulating film, and a drain electrode is formed on the second main surface to form an M-shaped trench structure.
A semiconductor material having a bandgap of 1.5 eV or more is used to form the OSFET. The material of this semiconductor substrate is preferably silicon carbide. In addition, a high-concentration source region and a drain region of the same conductivity type as the semiconductor substrate are formed on the surface layer of the first main surface and the surface layer of the second main surface, which are surrounded by the groove, respectively. A source electrode and a drain electrode are formed on the drain region, respectively.
【０００８】[0008]
【作用】絶縁膜直下の半導体中の空乏層の拡がりは２種
類の条件で異なる。一つは熱平衡状態で、絶縁膜と半導
体の界面に少数キャリアである正孔が蓄積し、反転層
（ｉｎｖｅｒｓｉｏｎ）が形成される静的な状態と、も
う一つは深層空乏層（ｄｅｅｐ−ｄｅｐｌｅｔｉｏｎ：
少数キャリアである正孔による反転層が形成されない状
態での空乏層のことをいう）とよばれる現象で、急激に
ゲートに電圧を印加したとき、正孔の蓄積がそれに応答
できず空乏層が反転層より一時的に拡がる過渡的な状態
がある。しかし正孔の熱的発生やｐ領域からの注入によ
り、通常極めて短時間で空乏層は反転層の幅になる。The spread of the depletion layer in the semiconductor immediately below the insulating film differs depending on the two kinds of conditions. One is a thermal equilibrium state, a static state in which holes, which are minority carriers, are accumulated at the interface between the insulating film and the semiconductor to form an inversion layer, and the other is a deep depletion layer (depletion-depletion layer). :
This is a phenomenon called a depletion layer in which an inversion layer due to holes which are minority carriers is not formed.) When a voltage is suddenly applied to the gate, the accumulation of holes cannot respond to it and the depletion layer is There is a transient condition that extends temporarily beyond the inversion layer. However, due to thermal generation of holes and injection from the p region, the depletion layer usually has the width of the inversion layer in an extremely short time.
【０００９】図３は空乏層の拡がりを計算した図であ
る。ここではゲート絶縁膜は酸化膜（ＳｉＯ2 ）とし、
厚さは０．１μｍである。この図から深層空乏層（ｄｅ
ｅｐ−ｄｅｐｌｅｔｉｏｎ）の空乏層端１２の拡がり
は、正孔が蓄積した状態の空乏層端１２の拡がり（図で
ｉｎｖｅｒｓｉｏｎ ｌｉｍｉｔ：限界反転層）より、
数倍以上になることが分かる。このことから、ｐｎ接合
のある従来構造より、第１ドリフト領域の幅を広くして
も、耐圧を保持でき、従って各セルごとにソース電極を
形成でき、ｐｎ接合を含まない構造にすることができ
る。また同図でＷは深層空乏層（ｄｅｅｐ ｄｅｐｌｅ
ｔｉｏｎ）の幅、Ｗm は限界反転層（ｉｎｖｅｒｓｉｏ
ｎ ｌｉｍｉｔ）の幅を示し、所謂空乏層の伸びを示
す。FIG. 3 is a diagram in which the spread of the depletion layer is calculated. Here, the gate insulating film is an oxide film (SiO 2 ),
The thickness is 0.1 μm. From this figure, the deep depletion layer (de
The spread of the depletion layer end 12 of ep-depletion) is based on the spread of the depletion layer end 12 in the state where holes are accumulated (inversion limit in the figure).
You can see that it will be several times more. Therefore, compared with the conventional structure having a pn junction, even if the width of the first drift region is widened, the breakdown voltage can be maintained, so that the source electrode can be formed for each cell and a structure not including the pn junction can be obtained. it can. In the figure, W is a deep depletion layer.
width, Wm is the limit inversion layer (inversio)
n limit), which is the extension of the so-called depletion layer.
【００１０】またシリコンで製作したｐｎ接合を含まな
い構造の素子では、耐圧を保持する状態つまり前記の過
渡的状態は、数１０秒に亘って保持することができる
が、従来技術で述べたTsengyou Syau 等が開示した構
造、つまりｐｎ接合を含む構造ではこの過渡的状態がな
く、耐圧を保持できない。その理由は前記した通りで、
ソース電極を設けるｎ+ ソース領域４を半導体基板１の
ｎ層から電気的に分離するためのｐ領域２１から正孔が
第２ドリフト領域６を介して第１ドリフト領域５に注入
され、ゲート電圧の印加と同時に反転層が形成され、空
乏層が第１ドリフト領域５を閉じることができなくな
り、耐圧が保持できない。In a device made of silicon and having a structure not including a pn junction, the state of maintaining the withstand voltage, that is, the transient state can be maintained for several tens of seconds. The structure disclosed by Syau et al., That is, the structure including the pn junction, does not have this transient state and cannot maintain the breakdown voltage. The reason is as described above,
Holes are injected from the p region 21 for electrically separating the n + source region 4 provided with the source electrode from the n layer of the semiconductor substrate 1 into the first drift region 5 through the second drift region 6, and the gate voltage is increased. The inversion layer is formed at the same time when the voltage is applied, the depletion layer cannot close the first drift region 5, and the breakdown voltage cannot be maintained.
【００１１】ところで、耐圧保持時間は、空乏層中で発
生する少数キャリアである正孔で決まり、その発生率は
真性キャリア濃度ｎi とライフタイムによって決まる。
ライフタイムは結晶性などによって決まる２次的なもの
であるが、ｎi は半導体に固有の物理量であるために、
半導体材料を決めると次式で決まる。By the way, the breakdown voltage holding time is determined by holes, which are minority carriers generated in the depletion layer, and the generation rate thereof is determined by the intrinsic carrier concentration ni and the lifetime.
The lifetime is a secondary one determined by crystallinity and the like, but since ni is a physical quantity peculiar to a semiconductor,
When the semiconductor material is decided, it is decided by the following formula.
【００１２】[0012]
【数１】 ここで、Ｎc ＮV は伝導帯および価電子帯の状態密度、
Ｅｇ、ｋ、Ｔはバンドギャップ、ボルツマン定数および
絶対温度である。耐圧を長時間保持させるためには、ｎ
i を小さくする必要があり、従って、上式から大きなバ
ンドギャップの半導体材料を使用する必要がある。この
半導体材料として、ＧａＡｓ（ガリウムヒ素）やＳｉＣ
（炭化ケイ素）がある。[Equation 1] Where N c N V is the density of states of the conduction band and the valence band,
Eg, k, and T are band gaps, Boltzmann constants, and absolute temperatures. To maintain the breakdown voltage for a long time, n
It is necessary to make i small, and therefore it is necessary to use a semiconductor material having a large bandgap from the above formula. As the semiconductor material, GaAs (gallium arsenide) or SiC
(Silicon carbide).
【００１３】[0013]
【実施例】図１はこの発明の一実施例の素子の要部断面
構造を示す。ソース電極８は各セルのｎ+ ソース領域４
上に設けられているため、従来構造のようにｐ領域２１
（図４参照）の形成は不要であり全領域でｐｎ接合を含
まないトレンチ構造のＭＯＳＦＥＴである。図４とソー
ス電極８部以外は同一構造であり、また符号も同一のた
め、本構造の説明は省略する。同図において、第１ドリ
フト領域５の幅Ｗを両側からの空乏層端１２の伸びＬが
凌駕することで耐圧を確保することができる。半導体基
板１にシリコン（Ｓｉ）を使用してこの素子を製作した
場合、ｐｎ接合を含む従来構造ではデバイスシミュレー
ションの結果せいぜい２０Ｖ以下しか静的耐圧を確保で
きないものが、ｐｎ接合を含まない本発明の構造では第
１ドリフト領域５の幅Ｗを従来構造より拡げても、４０
Ｖ以上の電圧を、数１０秒間保持できた。このように、
ｐｎ接合を含まない構造にすることで、第１ドリフト領
域５の幅Ｗを従来構造より拡げることができ、そのため
各セルのｎ+ ソース領域４上にソース電極８を設けるこ
とができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a cross-sectional structure of an essential part of an element of an embodiment of the present invention. The source electrode 8 is the n + source region 4 of each cell
Since it is provided above, the p region 21 is formed like the conventional structure.
This is a MOSFET having a trench structure in which the formation of (see FIG. 4) is unnecessary and the pn junction is not included in the entire region. Since the structure is the same as that of FIG. 4 except for the source electrode 8 and the reference numerals are the same, the description of this structure is omitted. In the figure, the breakdown voltage can be ensured by the width L of the first drift region 5 being exceeded by the extension L of the depletion layer edge 12 from both sides. When this element is manufactured by using silicon (Si) for the semiconductor substrate 1, the conventional structure including the pn junction can secure a static breakdown voltage of 20 V or less at most as a result of the device simulation, but the present invention does not include the pn junction. In the structure of No. 4, even if the width W of the first drift region 5 is expanded from that of the conventional structure,
A voltage of V or higher could be maintained for several tens of seconds. in this way,
With the structure not including the pn junction, the width W of the first drift region 5 can be widened as compared with the conventional structure, and thus the source electrode 8 can be provided on the n + source region 4 of each cell.
【００１４】図２はバンドギャップと耐圧保持時間の関
係図を示す。同図において、耐圧保持時間を実用レベル
の数１０時間以上にするためには、バンドギャップは
１．５ｅＶ以上が必要であり、ガリウムヒ素（ＧａＡ
ｓ）は比較的その値に近い。また炭化ケイ素（ＳｉＣ）
はバンドギャップが３ｅＶ近くもあり、殆ど無限の保持
時間となり極めて有用な素材である。ここでバンドギャ
ップとは、電子エネルギーで表したときの価電子帯と伝
導帯の間のエネルギーギャップをいう。FIG. 2 shows the relationship between the band gap and the breakdown voltage holding time. In the figure, the bandgap needs to be 1.5 eV or more in order to keep the breakdown voltage holding time at a practical level of several tens of hours or more, and gallium arsenide (GaA
s) is relatively close to that value. Also silicon carbide (SiC)
Has a band gap of about 3 eV and has an almost infinite holding time, and is a very useful material. Here, the band gap refers to an energy gap between a valence band and a conduction band when expressed by electron energy.
【００１５】またＳｉＣはバンドギャップが大きく、化
学的にも安定な材料であるため、シリコンと比較すると
高温や放射線下でも使用可能な各種の半導体素子が期待
されて、研究されている。またＳｉＣは現在のところ、
ｐ形の不純物としてアルミニウム（Ａｌ）やホウ素
（Ｂ）があるが、その不純物準位は０．２〜０．３ｅＶ
と深く、そのために室温での活性化率（価電子帯に正孔
を与える確立）は低く、ｐｎ接合を形成したとしても、
正孔の注入は極めて低く、耐圧保持時間は長くできる。
さらに、図１の構造ではｐ領域は形成されないため、よ
り一層耐圧保持時間を長くできる。以上の点から、半導
体基板１として、ＳｉＣは最適の半導体材料である。Further, since SiC has a large band gap and is a chemically stable material, various semiconductor elements that can be used even at high temperatures and under irradiation are expected and studied as compared with silicon. Also, SiC is currently
Aluminum (Al) and boron (B) are used as p-type impurities, but the impurity level is 0.2 to 0.3 eV.
And therefore the activation rate at room temperature (the probability of giving holes to the valence band) is low, and even if a pn junction is formed,
The injection of holes is extremely low, and the breakdown voltage holding time can be lengthened.
Further, since the p region is not formed in the structure of FIG. 1, the breakdown voltage holding time can be further lengthened. From the above points, SiC is the most suitable semiconductor material for the semiconductor substrate 1.
【００１６】[0016]
【発明の効果】この発明によれば、トレンチ構造の電圧
駆動型素子で、全領域においてｐｎ接合を含まない構造
にし、半導体基板に炭化ケイ素などバンドギャップが
１．５ｅＶ以上の半導体材料を用いることで、静的耐圧
より高い耐圧をほぼ無限の時間維持することができる電
力用半導体素子を得ることができる。According to the present invention, a voltage-driven device having a trench structure is formed without a pn junction in the entire region, and a semiconductor material such as silicon carbide having a band gap of 1.5 eV or more is used. Thus, it is possible to obtain a power semiconductor element capable of maintaining a withstand voltage higher than the static withstand voltage for an almost infinite time.
【図１】この発明の一実施例の素子の要部断面構造図FIG. 1 is a cross-sectional structural view of an essential part of an element according to an embodiment of the present invention.
【図２】バンドギャップと耐圧保持時間の関係図[Fig. 2] Relationship between bandgap and withstand voltage holding time
【図３】空乏層の拡がりを計算した図FIG. 3 is a diagram in which the spread of the depletion layer is calculated.
【図４】従来素子の断面構造図FIG. 4 is a sectional structural view of a conventional element.
１ 半導体基板 ２ ゲート電極 ３ ゲート絶縁膜 ４ ｎ+ ソース領域 ５ 第１ドリフト領域 ６ 第２ドリフト領域 ７ ｎ+ ドレイン領域 ８ ソース電極 ９ ゲート電極 １０ ドレイン電極 １１ 空乏層 １２ 空乏層端 １３ ゲート溝 ２１ ｐ領域 Ｌ 空乏層端の伸び Ｗ 第１ドリフト領域の幅1 semiconductor substrate 2 gate electrode 3 gate insulating film 4 n + source region 5 first drift region 6 second drift region 7 n + drain region 8 source electrode 9 gate electrode 10 drain electrode 11 depletion layer 12 depletion layer edge 13 gate groove 21 p region L extension of depletion layer edge W width of first drift region
Claims (3)
溝が形成され、該溝で囲まれた第一主面上にソース電極
が形成され、該溝の表面上に絶縁膜を介してゲート電極
が形成され、第二主面上にドレイン電極が形成されるト
レンチ構造のＭＯＳＦＥＴを構成し、前記半導体基板が
１．５ｅＶ以上のバンドギャップを有する半導体である
ことを特徴とする電力用半導体素子。1. A groove is selectively formed in a surface layer of a first main surface of a semiconductor substrate, a source electrode is formed on the first main surface surrounded by the groove, and an insulating film is formed on the surface of the groove. And a drain electrode is formed on the second main surface of the MOSFET having a trench structure, wherein the semiconductor substrate is a semiconductor having a band gap of 1.5 eV or more. Power semiconductor device.
を特徴とする請求項１記載の電力用半導体素子。2. The power semiconductor device according to claim 1, wherein the material of the semiconductor substrate is silicon carbide.
面の表面層とに半導体基板と同一導電形の高濃度のソー
ス領域と、ドレイン領域とがそれぞれ形成され、ソース
領域上にソース電極と、ドレイン領域上にドレイン電極
とがそれぞれ形成されることを特徴とする請求項１記載
の電力用半導体素子。3. A high-concentration source region and a drain region of the same conductivity type as the semiconductor substrate are formed on the surface layer of the first main surface and the surface layer of the second main surface, which are surrounded by the groove, respectively. 2. The power semiconductor device according to claim 1, wherein a source electrode is formed on the source region and a drain electrode is formed on the drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7123309A JPH08316470A (en) | 1995-05-23 | 1995-05-23 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7123309A JPH08316470A (en) | 1995-05-23 | 1995-05-23 | Power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08316470A true JPH08316470A (en) | 1996-11-29 |
Family
ID=14857357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7123309A Pending JPH08316470A (en) | 1995-05-23 | 1995-05-23 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08316470A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003517725A (en) * | 1999-08-10 | 2003-05-27 | イノベイティブ・テクノロジー・ライセンシング・エルエルシー | Unipolar field-effect transistor |
| US6787848B2 (en) | 2001-06-29 | 2004-09-07 | Kabushiki Kaisha Toshiba | Vertical type power mosfet having trenched gate structure |
| US6855983B1 (en) | 1998-11-10 | 2005-02-15 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having reduced on resistance |
| JP2006100365A (en) * | 2004-09-28 | 2006-04-13 | Nissan Motor Co Ltd | Semiconductor device |
| WO2008153142A1 (en) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | Semiconductor device |
| JP2012182508A (en) * | 2012-06-29 | 2012-09-20 | Nissan Motor Co Ltd | Semiconductor device |
-
1995
- 1995-05-23 JP JP7123309A patent/JPH08316470A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6855983B1 (en) | 1998-11-10 | 2005-02-15 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having reduced on resistance |
| JP2003517725A (en) * | 1999-08-10 | 2003-05-27 | イノベイティブ・テクノロジー・ライセンシング・エルエルシー | Unipolar field-effect transistor |
| US6787848B2 (en) | 2001-06-29 | 2004-09-07 | Kabushiki Kaisha Toshiba | Vertical type power mosfet having trenched gate structure |
| US7045426B2 (en) | 2001-06-29 | 2006-05-16 | Kabushiki Kaisha Toshiba | Vertical type power MOSFET having trenched gate structure |
| JP2006100365A (en) * | 2004-09-28 | 2006-04-13 | Nissan Motor Co Ltd | Semiconductor device |
| WO2008153142A1 (en) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | Semiconductor device |
| US8217419B2 (en) | 2007-06-15 | 2012-07-10 | Rohm Co., Ltd. | Semiconductor device |
| US8729605B2 (en) | 2007-06-15 | 2014-05-20 | Rohm Co., Ltd. | Semiconductor switch device |
| US9419127B2 (en) | 2007-06-15 | 2016-08-16 | Rohm Co., Ltd. | Semiconductor device including switching devices in an epitaxial layer |
| JP2012182508A (en) * | 2012-06-29 | 2012-09-20 | Nissan Motor Co Ltd | Semiconductor device |
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