JPH08306708A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE: To provide a semiconductor device having low parasitic capacity, and its fabrication method, in which a self-aligned electrode can be formed while monitoring the magnitude of source-drain current. CONSTITUTION: A resist pattern having inverse trapezoidal cross-section is formed on a working layer 2 followed by formation of an insulating film on the entire surface. The insulating film is then removed from the upper surface of the working layer 2 and resist pattern thus forming a pair of inclining side wall parts 4a, 4b of insulating film. Subsequently, a first electrode layer is formed on the upper surface of the working layer 2 and resist pattern, the first electrode layer on the resist pattern is removed together with the resist pattern, and heat treatment is effected thus forming ohmic electrodes 5a, 5b. While monitoring the magnitude of current flowing between the ohmic electrodes 5a, 5b, a recess is made in the region of working layer 2 exposed between the pair of side wall parts 4a, 4b and a gate electrode, i.e., a second electrode layer 7c, is formed in the recess and on the inner face at the side wall parts 4a, 4b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a gate electrode and an ohmic electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art In manufacturing field effect transistors such as MES-FET (metal-semiconductor field effect transistor) and HEMT (high electron mobility transistor) using GaAs, ohmic electrodes to be a source electrode and a drain electrode are manufactured. Must always be kept at a constant distance from the gate electrode. Therefore, a self-aligned ohmic electrode forming method is used to form the ohmic electrode at a predetermined position with respect to the gate electrode.

9 to 14 are process sectional views showing a conventional method for manufacturing a semiconductor device using the self-alignment ohmic electrode forming method. Here, as an example, GaAs
A method of manufacturing the HEMT will be described.

First, as shown in FIG. 9, an n-AlGaAs layer 12a and n ⁺ -G are formed on a GaAs semiconductor substrate 11.
The operation layer 12 including the aAs layer 12b is formed. next,
As shown in FIG. 10, the insulating film 13 is formed on the operating layer 12 at a predetermined interval, and the resist pattern 14 is formed on the insulating film 13. Then, as shown in FIG. 11, the region of the operating layer 12 between the insulating films 13 is etched to form a recess portion (recess) 15.

Next, using the resist pattern 14 as a mask, as shown in FIG. 12, a gate electrode 16 is formed in the recess 15 and on the insulating film 13 at the periphery thereof. After that, as shown in FIG. 13, the insulating film 13 except the region of the gate electrode 16 is removed. Finally, as shown in FIG.
Ohmic electrodes 17a, 17b and 17c are formed on the operating layer 12 and the gate electrode 16. The ohmic electrodes 17a and 17b on both sides of the gate electrode 16 serve as a source electrode and a drain electrode, respectively.

As described above, when the self-alignment ohmic electrode forming method is used, the positions of the ohmic electrodes 17a and 17b with respect to the gate electrode 16 can be self-controlled, so that the gate electrode 16 and the ohmic electrode 17 can be controlled.
The distance between a and 17b can always be kept at a predetermined value. As a result, the characteristics of the semiconductor device are stabilized.

[0007]

In the conventional method of manufacturing a semiconductor device described above, in order to control the value of the current between the source electrode and the drain electrode, the region of the operating layer 12 in which the gate electrode 16 is formed is formed. The recess 15 is formed by etching.

Since the ohmic electrode is not formed when the recess 15 is formed, the etching amount cannot be controlled while monitoring the current value. for that reason,
In order to form the recess portion 15, the n-GaAs layer 12a
It is necessary to use an advanced selective etching technique that utilizes the difference in etching rate between the n ⁺ -GaAs layer 12b and the n ⁺ -GaAs layer 12b.
It is difficult to accurately etch to a predetermined depth. As a result, the characteristics of the manufactured semiconductor device are not uniform, and the yield is low.

In the conventional semiconductor device described above, the gate electrode 16 is formed in a substantially T shape, and the thick insulating film 13 exists between the cap portion of the gate electrode 16 and the operating layer 12. There is a problem that the capacitance becomes large and the high frequency characteristics cannot be improved.

An object of the present invention is to provide a semiconductor device in which electrodes can be formed in a self-aligned manner while monitoring the value of a source-drain current and which has a small parasitic capacitance, and a manufacturing method thereof.

[0011]

In a semiconductor device according to the present invention, a pair of side wall portions made of an insulating film are formed on a semiconductor layer in opposite directions so that a distance between upper ends is larger than a distance between lower ends. The first electrode layers are formed on the regions of the semiconductor layer outside the pair of side wall portions, and the recesses are formed in the region of the semiconductor layer between the pair of side wall portions. A second electrode layer is formed inside and on the inner surfaces of the pair of side wall portions.

According to the method of manufacturing a semiconductor device of the present invention, a resist film having an inverted trapezoidal cross section is formed on a semiconductor layer, an insulating film is formed on the entire surface of the semiconductor layer and the resist film, and then the upper surface of the semiconductor layer and the resist are formed. Remove the insulating film on the upper surface of the film,
A first electrode layer is formed on the upper surface of the semiconductor layer and the upper surface of the resist film, and the first electrode layer on the resist film is removed together with the resist film to form a pair of inclined side wall portions made of an insulating film. A recess is formed in the region of the semiconductor layer between the pair of sidewalls, and a second recess is formed in the recess and on the inner surface of the pair of sidewalls.
To form the electrode layer.

[0013]

In the semiconductor device and the method of manufacturing the same according to the present invention, a pair of side wall portions made of an insulating film are formed on the semiconductor layer so as to be inclined in mutually opposite directions. After a pair of first electrode layers to be ohmic electrodes are formed in a self-aligned manner on the region of the semiconductor layer, a recess is formed in the region of the semiconductor layer between the pair of side wall portions. Therefore, it becomes possible to adjust the depth of the recess while applying a current between the pair of ohmic electrodes and monitoring the current value.

In practice, a current value is measured by flowing a current between a partial region of the wafer or the ohmic electrode of the monitor chip at an appropriate point in the process of forming the recess, and a predetermined current value cannot be obtained. In some cases, the depth of the recess is further increased. This is repeated until a predetermined current value is obtained.

A second electrode layer serving as a gate electrode is formed in the recess and on the inner surfaces of the pair of side wall portions. At this time, the gate electrode and the ohmic electrode do not come into contact with each other due to the existence of the pair of sidewall portions. Moreover, since the gate electrode is formed in a substantially V shape, the parasitic capacitance between the gate electrode and the semiconductor layer is reduced.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 8 are process sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In this embodiment, a GaAs HEMT will be described as an example of a semiconductor device.

First, as shown in FIG. 1, an operating layer 2 composed of an n-AlGaAs layer 2a having a thickness of 500Å and an n ⁺ -GaAs layer 2b having a thickness of 500Å is formed on a GaAs semiconductor substrate 1. Next, as shown in FIG. 2, a resist pattern 3 having a thickness of 1.9 μm is formed on the operation layer 2 by using a positive photoresist. The cross-sectional shape of the resist pattern 3 is an inverted trapezoid. As the photoresist, for example, trade name AZ5214E manufactured by Hoechst Japan Ltd. is used. The length L1 of the upper surface of the resist pattern 3 is, for example, 1.5 μm, and the length L2 of the lower surface thereof is, for example, 0.5.
μm.

Then, as shown in FIG. 3, ECR-CV
Using the D method (electron cyclotron resonance chemical vapor deposition method), an insulating film 4 made of silicon nitride and having a thickness of 2000 Å is formed on the entire surface of the operating layer 2 and the resist pattern 3. Further, as shown in FIG. 4, carbon tetrafluoride (C
RIE method using F ₄ (reactive ion etching method)
The insulating film 4 is removed by. At this time, since the cap portion of the resist pattern 3 serves as an etching mask, the insulating films 4 on both inclined side surfaces of the resist pattern 3 and the area therebelow remain without being removed. As a result, inclined sidewall portions 4a and 4b made of an insulating film are provided on both side surfaces of the resist pattern 3, respectively.

Thereafter, as shown in FIG. 5, AuGe having a thickness of 700Å, Ni having a thickness of 70Å and A having a thickness of 1300Å are formed on the upper surface of the operation layer 2 and the upper surface of the resist pattern 3.
The first electrode layer 5 having a laminated structure of u is formed by the resistance heating vapor deposition method. Then, the GaAs semiconductor substrate 1 is immersed in a stripping agent such as acetone to dissolve the resist pattern 3, so that the resist pattern 3 is removed together with the first electrode layer 5 above it (lift-off effect), as shown in FIG. Degree). Then, heat treatment is performed at a temperature of 450 ° C. for 2 minutes to form ohmic electrodes 5a and 5b.

Next, as shown in FIG. 7, phosphoric acid GaA
The region of the operating layer 2 exposed between the pair of side wall portions 4a and 4b made of an insulating film is etched with an s etching solution to form a recess portion 6 (recess etching). At this time, in a monitoring chip that is manufactured in a partial region of the wafer or at the same time, the etching amount is controlled while flowing a current between the ohmic electrodes 5a and 5b and monitoring the current value to obtain a desired source. The depth of the recess 6 is adjusted so that the saturation current value between drains can be obtained. Actually, the etching is stopped at a point of time when the etching is performed to some extent, and a current value is measured by applying a current between the electrodes 5a and 5b of a partial region of the wafer or the chip for monitoring.
When the predetermined current value cannot be obtained, further etching is performed. This is repeated until a predetermined current value is obtained.

Finally, as shown in FIG. 8, the upper surfaces of the ohmic electrodes 5a and 5b, the inside of the recess 6 and the side walls 4a and 4 are formed.
On the inner surface of b, T of thickness 200 Å was formed by resistance heating evaporation method.
i, Pd layer with a thickness of 400Å and Au with a thickness of 3000Å
The second electrode layers 7a, 7b, 7c having a laminated structure are formed.

The ohmic electrodes 5a, 5b formed outside the pair of side wall portions 4a, 4b serve as the source electrode and the drain electrode, and are formed in the recess 6 and the pair of side wall portions 4a, 4b.
The second electrode layer 7c formed on the inner surface of 4b serves as a gate electrode. At this time, the pair of side wall portions 4a made of an insulating film,
The second electrode layer 7c serving as a gate electrode due to the presence of 4b
Does not come into contact with the ohmic electrodes 5a and 5b.

As described above, according to the semiconductor device and the method of manufacturing the same of the present embodiment, since the ohmic electrodes 5a and 5b are formed before the recess portion 6 is formed, the ohmic electrodes 5a and 5b are formed when the recess portion 6 is formed. It is possible to adjust the depth of the recess 6 so that a desired saturation current value between the source and drain can be obtained by controlling the etching amount while monitoring the current value while passing a current therethrough.
Therefore, the characteristics of the manufactured semiconductor device become uniform and the yield is improved.

In the recess portion 6 and the pair of side wall portions 4
Since the second electrode layer 7c serving as a gate electrode is formed in a substantially V shape on the inner surfaces of a and 4b, the parasitic capacitance between the gate electrode and the semiconductor substrate 1 is reduced. Therefore, the high frequency characteristics of the semiconductor device are improved.

The present invention is not limited to GaAs HEMTs, but can be applied to various semiconductor devices having a gate electrode and an ohmic electrode. For example, the invention in IE
EE ELECTRON DEVICE LETTERS, VOL. 14, NO.7, JULY 19
93, pp.354-356, TMT (Two-Mode cha
nFET (FET) may be applied.

[0026]

As described above, according to the present invention, a pair of first electrode layers, which are ohmic electrodes, are formed in a self-aligned manner on the outer sides of side wall portions made of insulating films inclined in opposite directions. After that, since the recess can be formed in the region of the semiconductor layer between the pair of side wall portions, it is possible to adjust the depth of the recess while applying a current between the pair of ohmic electrodes and monitoring the current value. It will be possible. Therefore, the desired source-drain saturation current value can be obtained while forming the ohmic electrode in a self-aligned manner with respect to the gate electrode. As a result, the characteristics of the semiconductor device are made uniform and the yield is improved.

Further, since the second electrode layer serving as the gate electrode is formed in a substantially V shape in the recess and on the inner surfaces of the pair of side wall portions, the parasitic capacitance between the gate electrode and the semiconductor layer is reduced. . Therefore, the high frequency characteristics of the semiconductor device are improved.

[Brief description of drawings]

FIG. 1 is a first process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second process sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a third process sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a fourth process sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a fifth process sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a sixth process sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a seventh process sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is an eighth process sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a first process sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 10 is a second process sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 11 is a third process sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 12 is a fourth process sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 13 is a fifth process sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 14 is a sixth process sectional view showing the method of manufacturing the conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GaAs semiconductor substrate 2 operation layer 3 resist pattern 4 insulating film 4a, 4b side wall part 5 first electrode layer 5a, 5b ohmic electrode 6 recess part 7a, 7b, 7c second electrode layer

Claims (2)

[Claims] 1. A pair of sidewalls made of an insulating film are formed on a semiconductor layer so as to be inclined in mutually opposite directions so that a distance between upper ends is larger than a distance between lower ends. First electrode layers are formed on the regions of the semiconductor layer outside the parts, and recesses are formed in the regions of the semiconductor layer between the pair of side wall parts. Inside the recesses and the pair of side walls. A semiconductor device having a second electrode layer formed on the inner surface of the portion. 2. A resist film having an inverted trapezoidal cross section is formed on a semiconductor layer, an insulating film is formed on the entire surfaces of the semiconductor layer and the resist film, and then insulation is performed on the upper surface of the semiconductor layer and the upper surface of the resist film. The film is removed, and a first electrode layer is formed on the upper surface of the semiconductor layer and the upper surface of the resist film,
The first electrode layer on the resist film is removed together with the resist film to form an inclined film made of an insulating film.
Forming a pair of sidewalls, forming a recess in a region of the semiconductor layer between the pair of sidewalls, and forming a second electrode layer in the recess and on an inner surface of the pair of sidewalls. A method for manufacturing a characteristic semiconductor device.