JPH08294077A - Video signal processing unit and composite screen projector - Google Patents

Abstract

PURPOSE: To facilitate the adjustment by calling data alternately from two memories every time correction data are revised so as to prevent flickering of the screen when soft edge is corrected by remote control while observing a composite video image. CONSTITUTION: A synchronizing separator section 31 extracts synchronizing information of a video signal and a clock generating section 32 generates a signal of a prescribed period. Then, a phase lock section 33 generates a clock signal phase-locked for each synchronizing information according to the received synchronizing information and reference clock signal. New correction data are written in one RAM not in use in two RAMs 1, 35A and 2, 35B when a horizontal frequency of the video signal is revised or correction data are adjusted. Then, data are read out of the RAM synchronously with the vertical synchronizing information of the video signal. Thus, either of the two RAMs 1, 35A and 2, 35B is selected alternately in this way to adjust the video signal, then no disturbance is caused on the screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, and more particularly to a video signal processing device useful when synthesizing two or more video signals to form a large screen, and a synthetic screen projection device. Is.

[0002]

2. Description of the Related Art As a display device for visually displaying various information, a television for displaying an image on a CRT tube surface, a liquid crystal display panel or the like, or a monitor device for a computer is usually used. However, since the size of the display screen is limited in such a display device, there is a problem that, for example, only a part of the image that the viewer actually wants to see is displayed. In addition, a projector using a projection tube or a liquid crystal plate can reproduce an image in most of the viewing angle by projecting the image on a large screen, but such a large projection device generally displays images. The larger the screen, the more difficult it is to reproduce a bright screen

Therefore, a so-called multi-vision type image projection apparatus that synthesizes a screen projected from a small projection apparatus and projects it on a large screen is a method for reproducing virtual reality, for example, a simulation apparatus or an amusement machine. It is used in various theaters. FIG. 9 shows an outline of a projection device which forms a large composite screen by arranging a plurality of small projection devices (liquid crystal projectors), and 5 shows a composite video display device as a whole. Screen portions 6a to 6 formed by dividing the transmissive screen 6 into four
Liquid crystal plates 1 to 4 are provided corresponding to d.
4 is irradiated with light to project the images LA1 to LA4 on the screen 6 as a combined screen.

The optical systems 7 to 10 have the same structure. For example, with respect to the optical system 7, the light emitted from the light source 11 is condensed on the liquid crystal plate 1 via the condenser lens 12 and the Fresnel lens 13. The transmitted light is modulated by driving the liquid crystal plate 1 with a video signal, and the transmitted light is projected on the screen through the field lens 14.

Similarly, in each of the other optical systems 8, 9 and 10, the image light transmitted through the liquid crystal plates 2, 3 and 4 is projected on each of the four divided areas of the screen 6, so that the image is displayed on the screen 6. A composite screen is formed in, and a large-sized display device can be obtained. By the way, in the case of such a projection type composite image projection device, a discontinuous line of the image is generated in the adjacent portion of each projected image, but each optical system is arranged so as to eliminate the discontinuous line. It is extremely difficult to perform the positioning of 1-4.

Therefore, in the conventional projection type projector, as shown in the screen projection image of FIG.
Each video part (LA1-LA) to be combined on the screen
The boundary of 4) is overlapped so that no gap is generated in the combined screen projection image, and the brightness level of one video signal vA projected in this overlapped area Q is shown in FIG. As shown in the figure, the signal processing is performed such that the level gradually decreases and the level of the other video signal vB gradually increases.

[0007]

However, since the above-described signal processing needs to be mutually performed for the combined video signals based on the synchronization signal included in the video signals, for example, the video signals It is conceivable to store the data for correcting the luminance level of the above in a memory or the like, and perform signal processing such that the luminance level of each video signal to be combined is changed with the data read from this memory based on the synchronization signal. There is. However, in this case, when a video signal having a different horizontal synchronizing signal of the video signal to be displayed is input, it is necessary to change the clock signal for this reading depending on the type of the video source, which complicates the correction circuit. There's a problem.

Further, as a clock for reading such correction data, a clock signal is generated from a PLL circuit controlled by a horizontal synchronizing signal, and its output is frequency-divided to read a memory in which the correction data is stored. It is conceivable to form a clock for use, but if jitter occurs in the output of the PLL circuit, the quality of the image deteriorates, and the filter for smoothing the read digital data causes the filter to change the horizontal frequency of the video source each time. , It is necessary to switch the pass characteristic.

Further, it is necessary to adjust the correction data so that the joints of the screens are not noticeable while actually seeing the projected image in the above-mentioned composite screen. However, there is a problem in that it takes time to perform the adjustment so as to eliminate the joint, and the adjustment of the overlapping portion cannot be continuously monitored, which makes the adjustment method itself difficult. Therefore, even if the same video signal is projected on the boundary portion of the projection screen, the projector for projecting the composite screen as described above is faded out so that the discontinuity of the composite video signal is eliminated at the overlapping portion. , And fade-in processing are extremely difficult to perform, and there is a problem that it is difficult to easily improve the continuity of the boundary portion due to the complicated adjustment work and circuit configuration. In particular, when the system (horizontal, vertical frequency) of the video source to be displayed is different, there is a problem that the signal processing circuit in this part becomes extremely complicated.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing apparatus suitable for a multi-scan type projector by a simple device in order to solve such a problem, and to provide the video signal processing apparatus. According to a first aspect of the present invention, there is provided a composite screen projection device, wherein the first aspect of the present invention is a sync separation means for extracting sync information of an input video signal, a reference clock signal source for generating a signal having a constant period, and the reference signal. Phase synchronization control means for inputting the clock signal output from the source and outputting the phase locked clock signal at the timing when the synchronization information is output;
Two memory means for storing the correction data for correcting the video signals for the lines at different timings, a bank switching type bank selector means for selecting the correction data read from the two memory means, and the bank An A / D converter that converts the digital signal output from the selector into an analog signal and a filter circuit that smoothes the output of the A / D converter are provided. A multiplier for converting the input video signal by the output of the filter circuit is provided so that various kinds of signal processing of the video signal are performed.

The above-mentioned correction data is data for correcting the signal in the superposition area when the above-mentioned input video signals are combined to form a composite screen, and this correction data is the start point area of each line of the video signal and / or Use the data to fade-in or fade-out with a straight line or a predetermined curve to the end point area so that the edge part of the composite screen is not noticeable

Further, the two memory means are new to the unused memory means of the memory means when the horizontal frequency of the input video signal is changed or when the correction data is adjusted. The correction data is written, and then switching is performed so that the data is read out from the memory means in synchronization with the vertical synchronization information of the video signal so that the screen is not disturbed when the video signal is adjusted.

Further, according to the second aspect of the present invention, each of the video signals synthesized by the above-mentioned video signal processing device is subjected to signal processing and then input to a plurality of projection devices capable of enlarging and projecting on a screen. Thus, the projection screen of the large screen makes it almost impossible to recognize the joint at the composite position.

[0014]

The video signal processing apparatus of the present invention controls the phase of the clock signal output from the reference clock signal source fixed at a predetermined cycle by the synchronization information of the video signal to be subjected to signal processing. Since correction data is read by the clock signal locked by phase control, accurate correction data can be output with a simple circuit configuration even when the horizontal frequency of the input video signal is different. , Signal processing compatible with multi-scan can be performed.

Further, when the edge portion of the composite screen is adjusted by the above signal processing device, the adjustment data is alternately input to the two bank memories, and new correction data is output based on the vertical synchronization information. Since it is configured, it is possible to adjust the projected composite image so as not to cover the joint area of the projected image by using the remote controller while gazing at the screen.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of a composite video projection device using a video signal processing device of the present invention will be described with reference to FIG.
In this figure, reference numeral 20 denotes a video signal source for displaying a composite image, for example, a computer 20A.
The image information output from the laser disk device 20B, the image data output from the laser disk device 20B, the video signal reproduced by the VTR 20C, and the video signal of the subject directly output from the television camera 20D are input as video sources. . It should be noted that a single video signal output from a VTR, a laser disk device or the like is once taken into the computer 20A as image data, processed into a multi-screen n-channel video signal, and output as an R, G, B component signal. However, in this case, the synchronization information may be superimposed on, for example, the G signal, or may be derived as another signal by another cable line.

The multi-video signals output from the video signal source 20 are preferably supplied as R, G and B components to the soft edge matching device 21 forming the signal processing device of the present invention. Then, in this soft edge matching device (hereinafter, referred to as SEM device), when the composite screen is projected as described above,
The signal processing is performed so that the joint portion is continuous, and the three projection devices 40A, 40B, 40C are provided for each of them.
Will be supplied to the composite image projection device 40.

The three projectors are, as a projector,
A commonly used high-intensity cathode ray tube (CRT) converts a video signal into a projected image, and a horizontally long screen 50
The image is projected as a composite image on the screen, but this projection device can also be configured by a liquid crystal projector. Further, in the case of this embodiment, three projection devices are arranged in the lateral direction, but if this number is 2 or more, the signal processing device of the present invention is targeted, and in the following embodiments, A case where the joint portion of the composite image is processed by two video screens will be described.

FIG. 2 is an explanatory view when the two images A and B are combined and displayed, and the horizontally long screen 50 shows a case where the projected images A and B are combined. Adjacent portions of the image A and the image B are a superposed area Q in which the images overlap with each other. In the superposed area Q, signals are processed on the video source side so that the images A and B are the same video. That is, as shown in the video signal V _a in one horizontal period in FIG. 2, the video signal in the diagonally downward-sloping portion of one video signal V _a and the diagonal portion of the starting point of the other video signal V _b Are image information of the same content, and signal processing is performed so that the luminance level of this portion has a fade-out characteristic that gradually decreases and a fade-in characteristic that gradually increases as shown by the curve.

Accordingly, when the image is projected on the screen 50 by the two projection devices by performing such signal processing, the brightness of the area Q of the screen 50 becomes the same as the brightness of the portions of the image A and the image B, It can be synthesized so that the joint is almost unknown. It should be noted that if the start point of one video signal V _a is processed so as to become an area OS that is slightly overscanned, and the vicinity of the end point of the other video signal V _b is also an overscan area OS, the screen is displayed. It is possible to prevent the edges of the image from appearing at both ends of 50.

When a composite image is displayed by three projectors, the left and right video signals (only one horizontal period) a and c are the same as in FIG. 2 as shown in FIG. However, the start point area b of the video signal b located on the central screen is
_S and the end point area b _E , the area a _E of the video signal a,
It is preferable to process the video signal so that the video signal has the same content as the area b _S of the video signal b. In this area, the two edge portions of the image, which are produced by the fade-out and fade-in processing and are combined, It will be corrected.

Next, the main part of the SEM device 30 shown in FIG. 1 will be described with reference to the block diagram of FIG. In this figure, OP1 to OP4 are buffer amplifiers, respectively, and the luminance level of the composite video signal (component signal) supplied from the input terminal Tin is corrected by the multiplier 38 via the line L ₁ and output from the output terminal Tout. It is supplied to the projection device 40 (A, B, C). When the synchronization information is separated as seen in the computer graphic video signal, the synchronization signal is output via the line L ₂ .

The sync information superimposed on the component G signal is separated into sync signals (horizontal sync signal and vertical sync signal) by a sync separation circuit 31. For example, the phase control circuit 3 already on sale.
3 (Product name KS6369 manufactured by CRAIAS) is input. Reference numeral 32 is a reference clock signal source composed of, for example, a crystal oscillator, and supplies a clock signal of a fixed cycle of 40 MHz to the phase control circuit 33, for example. Then, every time the horizontal synchronizing signal is input by the phase control circuit 33, the phase of the clock signal is output in synchronization with the timing.

Reference numeral 34 is an address counter for reading the data in the subsequent memory (RAM) 34 by the clock signal output from the phase control circuit 33. For example, 12-bit address data is followed by correction data for one horizontal period. Data is read from either one of the two bank memories 35A and 35B. The overlapping area Q set by the CPU 39 in one of the memories 35 (A, B), for example, 35A.
Signal processing, that is, correction data (K = 1 to 0) of the cosine curve in which the luminance signal gradually rises and gradually falls as shown in FIG. 5 (a) is written. It is output during the period of points S and E shown in FIG. Further, the other bank memory 35B, as will be described later, when making a change to this correction data,
An interrupt is issued from the CPU 39 and new data is stored. Then, this data is read at a predetermined timing in place of the data that was initially output. In this embodiment, the correction data is composed of, for example, 8-bit data and the read cycle is set to 25 nS, but this value can be changed in consideration of the capacity and price of the memory 35 (A, B). Is.

FIG. 5B shows a video signal V subjected to signal processing.
It shows the state of S for one horizontal period, and HS indicates the position of the horizontal synchronizing signal. By counting the clock signals based on the position of the horizontal synchronizing signal, S
The EM correction start address A point is set, and the SEM correction end point B is determined by the count number of the clock signal. Point C is the address of the correction rising end point of the SEM, and point D is the address of the SEM correction falling start point. The points C and D can be adjusted within a range of 46.4% of the horizontal period by a remote controller which will be described later, as indicated by a dotted line. The time required for rising and falling is, for example, 14.849% of the horizontal period at a clock of 40 MHz when the number of variable steps in this period is 64 steps. This means that when the horizontal cycle is set to the minimum of 15 KHz, the data amount becomes 400 bytes, and the cosine data output from the ROM of the CPU 39 has a memory capacity capable of outputting this data.

In the present embodiment, the correction data read cycle is also fixed at the frequency (40 MHz) of the reference clock signal, and therefore is constant regardless of the horizontal frequency of the input video signal. Therefore, the A / D converter 36 and the filter (smoothing filter with a cut-off frequency of 20 MHz) 37 that are arranged subsequently should have constant characteristics regardless of the horizontal frequency of the input video signal. Therefore, the signal processing circuit can be simplified.

When a video signal having a horizontal frequency of 15 KHz is input, one horizontal period is approximately 2 samples.
The signal processing is performed with the correction data of 667 (2667 bytes), and when the horizontal frequency is 93 KHz, the correction is performed with the data of 431 samples (431 bytes). Therefore, in the embodiment of the present invention, when the detection unit for detecting the horizontal frequency of the input video signal is provided and when the video signals of different systems are combined and projected, the memory 35 corresponds to the horizontal frequency of the video signal. The contents (storage address) of the correction data stored in (A, B) are changed, the correction data is always read out in a constant cycle, and the correction data is converted into an analog signal via the A / D converter. It is possible to form a smooth correction curve with a filter that performs smoothing and supply the curve to the multiplier 38 to perform signal processing (level adjustment) of the superimposed portion Q of the video signal.

FIG. 6 shows timing waveforms of signal processing when R, G, and B component signals are input as video signals. In the case where a synchronizing signal (horizontal synchronizing signal) is superimposed on the G signal. Is shown. The horizontal separation signal HS and the vertical synchronization signal VS are separated by the synchronization separation circuit 31, and the clock signal CLK output from the reference clock signal source 32 is phase-locked at the falling point of the horizontal synchronization signal HS and the lock clock signal (L. CLK). An address signal ADD for reading the memory 35 (A, B) by the lock clock signal KCLK
Is formed, and the correction data (RAM.D) stored in the memory is read by this address signal ADD.

The correction data RAM.D is D / A.
The converted signal is converted into an analog signal by the converter 36, smoothed by the filter 37, and supplied to the multiplier 38 shown in FIG. The multiplier 38 inputs each component R,
Correction data R output from the memory for G and B signals
Multiplying the AM and D values (k = 0 to 1), the luminance signal in the portion where the video signals of the composite screen overlap is faded out,
And the amplitude is controlled so as to fade in.

The period of the overlapping portion Q where the adjacent video screens overlap on the composite screen may be set to about 10 to 14% of the video signal, but depending on the video source, this weight part can be arbitrarily changed. Such changes can be specified by the user by the remote controller 30A shown in FIG. An all-white screen is the most suitable as a test screen that adjusts the connected parts of the composite screen by the correction data so that it is not noticeable, and a test pattern signal generator that generates all-white in part of this video signal processing circuit. May be provided.

FIG. 7 shows an electronic circuit portion of a board to be inserted into the SEM device 30. One board 10 is shown.
0 is provided with a signal processing circuit for processing one video signal forming a composite screen. That is, the board 100 surrounded by the alternate long and short dash line has terminals Rin, Gin, Bin to which a component video signal is input and a synchronization terminal Hi.
n and Vin are provided and terminals Rout, Gout, Bout and Hout, Vou for outputting these signals are provided.
t is provided.

The input R, G, B signals are clamped through the buffer amplifier 101, and the sync signal is separated by the sync signal separation circuit 102. The separated sync signal controls the phase of the fixed clock signal output from the reference clock signal source 103 described above.
To the bank memory 107A and 1 to supply the locked clock signal to the address counter 105.
The address data of 07B is output. This address data is supplied via the bank selector 106 when the data is read from the bank memory 107A or 107B at a constant cycle, and the bank memory 107A and 1
When writing the correction data to 07B, the address of the CPU 142 is selected through the SEM interface 114, and the correction data corresponding to this is written.

As described above, two systems of memories for storing the correction data for changing the level of the luminance signal are prepared. For example, the data input to the bank memory 107A is changed by the operation of the remote commander 150 or the like. At this time, the changed data is recorded in the vacant bank memory 10B, and after the changed data is recorded in this memory 107B, the operation of switching the bank memory reading is switched in synchronization with the vertical synchronizing signal. Therefore, according to this embodiment, the edge portion of the composite screen is corrected by operating the remote controller 150 while looking at the screen, and the screen is not disturbed when the edge that is the overlapping portion is corrected. .

Reference numeral 108 denotes a data buffer circuit for writing change data, which is the address data selector 1
It is driven when writing change data or saving change data based on an instruction from the CPU 142 in cooperation with 06. Switching the bank memory 107 (A, B),
The data conversion (parallel-serial conversion) is controlled by the bank memory selector 109, and the output digital data is supplied to the filter 111 via the D / A converter 110. Then, the correction signal smoothed by the filter 111 is applied to the coefficient units 112R, 112G, 112B.
Input to the component R, G, B signals so that they can have appropriate rising and falling characteristics.

FIG. 8 shows a flowchart for switching the contents of the bank memory based on a command input from the remote controller when adjusting the composite screen. The command (up, down) for changing data from the remote controller is given by the button. When input (S1), the CPU 142 calculates the correction data written in the RAM based on the correction table. Then, the calculated new data is written in the vacant bank memory 107 (A, B) (S3). This writing is performed by the interrupt processing of the CPU 142 based on the vertical synchronization, and when all the data are stored, the timing at which the vertical synchronization signal VS is input next is detected (S4). Then, the bank memory is switched at the timing when the vertical synchronizing signal is input (S5), and the screen corrected by the data adjusted from the next video frame is projected. Therefore, the video signal processing device of the present invention can prevent the screen from flickering at the stage of correcting the data.

The # 2 substrate 130 shown in FIG. 7 is a portion in which a space is provided on the substrate so that a spare electronic circuit can be inserted therein. It is possible to mount a signal processing board that corrects color shifts (changes in color of color signals) that occur at edges and corrections of hot spots.

The board 140 sequentially changes the correction data based on a command from the remote commander 150 connected by the RS232C communication protocol, and adjusts the edge portion of the composite screen so that it cannot be seen on the screen. A remote control interface 141 is provided, and a command from the remote commander 150 is analyzed by the CPU 142, and various operations on the substrate 120 described above are performed via the CPU interface 147, for example. The board 140 is also provided with a ROM 143, a RAM 144, and a backup RAM 145, which store an operation program of the CPU 142, cosine data having fade-out and fade-in characteristics, and the like.

Particularly, the backup memory 145 stores several kinds of optimum correction data of various video signals set up to now, and for example, when displaying video signals of different sources on a composite screen. When the data set for the composite screen is already detected together with the horizontal frequency of the video signal, the horizontal frequency measuring circuit 146 that detects the horizontal frequency of the newly input video signal directly interrupts the CPU 142. Then, the optimum data for projecting the composite screen is read from the backup memory 145, and the bank memories 107A and B of the board 120 are rewritten. The correction data output from the new bank memories 107A and 107B are also read according to the flowchart of FIG.

The board 100 shown in FIG. 7 is constructed so that it can be attached / detached to / from the SEM apparatus shown in FIG. 1 by the number of composite video signals.
Main C provided on the motherboard 160 via
Totally controlled by PU. The SEM remote controller 150 uses the selection buttons P1. P2. Buttons P4 and P5 for selecting the rising and falling characteristics of P3 and the overlapping portion of the screen
And a button P6 for selecting the length of the screen overlapping portion,
When these buttons are pressed, a reception signal is received from the SEM device side. The edge correction data calculated when the up and down buttons are operated are alternately input to the bank memory 107 (A, B) each time, and the edge of the screen is visible while reading the correction data. The signal is processed so as not to lose it.

In the above embodiment, the cosine curve is used as the correction data so that the video signal can be seen continuously in the superposed portion. However, this correction data may be another curve or one that changes linearly depending on the screen. You can also Further, the video signal processing device of the present invention can be appropriately changed within the scope of the gist thereof. For example, when a field memory is used as a memory for storing correction data and data is read by a horizontal synchronizing signal. ,
This makes it possible to adapt when edge correction is performed in the case where a composite screen is formed in a vertically overlapping manner.

[0041]

As described above, the video signal processing apparatus of the present invention extracts the synchronization information of the input video signal and outputs the clock signal whose phase is synchronized with this synchronization signal with high precision such as a crystal oscillator. Since the sampling cycle is formed by the clock generating means and the correction data is output regardless of the cycle of the video signal, the circuit configuration can be simplified and stable signal processing can be performed. it can.

In particular, the video signal processing device of the invention has a CPU
When the correction data calculated by is changed, it is input to the two bank memories alternately and the data is called at a predetermined timing. When performing edge correction, it is possible to prevent flicker on the screen, and it is very easy to perform adjustment work.

Further, by applying such signal processing to the superimposed portion of the combined screen to form the combined screen projection device, it is possible to easily project a large combined projection screen.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a usage mode of a combined screen projection apparatus and a video signal processing apparatus of the present invention.

FIG. 2 is an explanatory diagram of a composite screen projected on a screen.

FIG. 3 is a signal waveform diagram when synthesizing 3-channel video signals.

FIG. 4 shows a block diagram of a video signal processing device.

FIG. 5 is a graph showing an example of correction data of a superposed portion.

FIG. 6 is a waveform diagram showing a read clock signal of the memory means and a data read timing.

FIG. 7 is a block diagram showing a circuit of a board stored in the SEM device.

FIG. 8 is a flowchart showing write and call timings of the bank memory when the correction data of the video signal is changed.

FIG. 9 is an explanatory diagram showing a conventional example of a device that projects a composite screen.

FIG. 10 is an explanatory diagram showing a pattern of an edge portion of a composite screen and a correction characteristic of a video signal.

[Explanation of symbols]

 20 video source 30 soft edge matching device 32 reference clock signal source 33 phase control circuit 34 address counter 35 memory means 36 A / D converter 37 filter 38 multiplier 40 projection device 50 screen

Claims (6)

[Claims] 1. A synchronization separating means for extracting synchronization information of an input video signal, a reference clock signal source for generating a signal having a constant cycle, and a clock signal output from the reference signal source are input to perform the synchronization. Phase synchronization control means for outputting a clock signal that is phase-locked at the timing when information is output, two memory means for storing correction data for correcting at least one line of video signal at different timings, Bank selector means for selecting the correction data read from each memory means, and A / A for converting the digital signal output from the bank selector into an analog signal.
Video signal processing comprising a D converter, a filter circuit for smoothing the output of the A / D converter, and a multiplier for converting the input video signal by the output of the filter circuit. apparatus. 2. The video signal according to claim 1, wherein the correction data is data for correcting a signal in a superposition region when the input video signals are combined to form a combined screen. Processing equipment. 3. The correction data is data for performing fade-in or fade-out with a straight line or a predetermined curve with respect to a start point region and / or an end point region of each line of a video signal. The video signal processing device according to claim 1 or 2. 4. When the horizontal frequency of the input video signal is changed, the two memory means write new correction data into one of the unused memory means of the memory means, and thereafter, 4. The video signal processing device according to claim 1, wherein the switching is performed so that the data is read from the memory means in synchronization with the vertical synchronization information of the video signal. 5. When the correction data is manually changed in the two memory means, the changed correction data is written in one of the unused memory means of the memory, and then the video signal of the video signal is changed. 4. The video signal processing device according to claim 1, wherein the video signal processing device is switched so that the data is read from the memory means in synchronization with the vertical synchronization information. 6. A synchronization separating means for extracting synchronization information of an input video signal, a reference clock signal source for generating a signal of a predetermined cycle, and a clock signal output from the reference signal source are input, and the synchronization is performed. At least one phase synchronization control means for outputting a phase locked clock signal at the timing when information is output
Two lines of memory means for storing correction data for correcting video signals for lines, and correction data are read from any one of the memories based on the clock signal output from the phase synchronization control means. However, a video signal processing device is formed by the control means for performing signal processing of the edge region of the projection screen of the input video signal, and two or more video signals forming a composite projection screen are respectively sent to the signal processing device. A composite screen projection apparatus comprising two or more projection devices for inputting and performing signal processing of a superimposed area of the composite screen and projecting a video signal output from the video signal processing device on the screen. .