JPH08292739A - Driving method for direct current type plasma display panel - Google Patents

Abstract

PURPOSE: To provide a DC-PDP driving method having a less number of erroneous lighting operations. CONSTITUTION: During the period in which a writing pulse signal (Pw ) is being applied to a prescribed anode DAm in synchronization with a scanning pulse (Pk ) of a cathode, an erroneous lighting preventive pulse signal having a lower voltage than the bias voltage of the anode DAm is applied to other anode DAm+1 adjacent to the anode DAm through an auxiliary anode SAj in synchronization with the signal Pk .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a DC plasma display panel, and more particularly to a method for driving a DC plasma display panel by driving a pulse memory.

[0002]

2. Description of the Related Art A conventional DC type plasma display panel (hereinafter referred to as a DC-PDP or simply a panel).
Japanese Patent Application Laid-Open No. 6-1 of the Japanese Patent Laid-Open No. 6-1
2988.

According to the conventional pulse memory driving method, the scan pulse signal (P _K ) and the sustain pulse signal (P _sp ) are sequentially given to the cathodes on the first to mth rows on the cathode side. Apply in a cycle. The pulse width and voltage of the sustain pulse signal are determined so as to maintain the display cell discharge of the pulse memory.

On the other hand, the write pulse signal (P _w ) is applied to the anodes in the first to nth columns on the anode side at intervals of a predetermined cycle. Further, the auxiliary discharge pulse signal (P _sa ) is applied to the auxiliary anode at a constant cycle. With this configuration, when the scanning pulse signal is applied from the cathode side, each auxiliary cell is sequentially discharged by synchronizing (synchronizing) the auxiliary discharge pulse signal with the scanning pulse signal of each row. To go.

In addition, when writing to a display cell,
The scan pulse signal (P _k ) and the write pulse signal (P _W ) are synchronized with each other to discharge only predetermined display cells. After that, the sustaining pulse signal (P _sp ) is applied to the cathode at a predetermined cycle to sustain the display discharge of the display cell. By adopting such a panel configuration and driving method, even if the display panel becomes large or the sustain pulse cycle is shortened, the driving waveform of the anode and the cathode can be changed without lowering the overall efficiency of the panel. It has been reported that simplification or drive circuits can be simplified.

[0006]

However, the conventional pulse memory driving method has a problem that the drive maintenance margin becomes small. The drive sustaining margin here means the maximum sustaining voltage (the maximum value of the discharge sustaining voltage that can be applied to the cathode without causing a malfunction (erroneous discharge)).
Is the value obtained by subtracting the minimum sustaining voltage (which is the minimum value of the discharge sustaining voltage that enables normal operation).

The reason why the drive maintenance margin becomes small will be described below. When writing is performed, in the conventional driving method, the absolute value voltage of the scanning voltage V _{k of the} cathode and the writing voltage V _w is applied to a predetermined cell. At this time, since the auxiliary discharge pulse voltage V _sa is applied to the auxiliary cells in synchronization with the scan pulse signal, the auxiliary cells start discharging and the display cells are easily discharged. By applying the write pulse voltage V _w and the scan pulse voltage V _k to the display cell, the discharge of the display cell is started. Once the display cell is written, the sustain pulse signal P _sp is supplied to the cathode at a predetermined cycle.
The display discharge can be sustained by applying. A voltage _obtained by adding a bias voltage V _m of the anode and a sustain voltage V _sp, which is the same as the scan voltage V _{k of the} cathode, is applied to the display cell while maintaining the discharge. At this time, the bias voltage V _m and the sustain voltage V _sp are also applied between the anode and the cathode of another display cell that is adjacent to the auxiliary cell via the auxiliary cell.
A voltage _obtained by adding (= scanning voltage V _k ) is applied. By the way, in the conventional driving method, since the sustain voltage V _sp is the same voltage as the scanning voltage V _k , erroneous lighting (erroneous discharge) may occur due to the priming effect during auxiliary discharge. Therefore, the maximum sustain voltage cannot be increased,
Therefore, there is a limit to increase the drive maintenance margin, and there is no choice but to reduce the drive maintenance margin.

As described above, if the drive sustaining margin is made small without being made large, erroneous lighting (a phenomenon in which non-discharge cells are lit) is likely to occur, and erroneous lighting occurs as the panel becomes larger. The rate will also increase. In addition, as a method of preventing erroneous lighting, it is possible to accurately manufacture the height of the partition wall and the priming path in the printing process of manufacturing the panel, but it is necessary to cover (suppress) the variation of the discharge voltage in the manufacturing process. There was a limit.

Therefore, there has been a demand for a driving method of a DC type plasma display panel capable of increasing a driving maintenance margin.

[0010]

Therefore, according to the driving method of the DC type plasma display panel of the present invention,
A plurality of cathodes and anodes provided orthogonally to each other, a display cell provided at the intersection of the cathode and the anode, an auxiliary electrode provided in parallel with the anode between the anodes, and provided at the intersection of the auxiliary electrode and the cathode And an auxiliary cell, and a scanning pulse signal (P
_K ) and a sustain pulse signal (P _sp ), a write pulse signal (P _W ) higher than the bias voltage is applied to the anode, and an auxiliary discharge pulse (P _sa ) is applied to the auxiliary anode, and these scans are performed. In a driving method of a DC type plasma display panel for adjusting the application timing of a pulse signal, a sustain pulse signal, a write pulse signal, and an auxiliary discharge pulse signal to perform display discharge, in synchronization with a scan pulse signal (P _K ) of a cathode. While the write pulse signal (P _w ) is being applied to the predetermined anode, a voltage lower than the bias voltage of the anode is applied to the other anode adjacent to the predetermined anode via the auxiliary anode in synchronization with the scan pulse signal. The erroneous lighting prevention pulse signal is applied.

[0011]

According to the driving method of the DC type plasma display panel of the present invention, while the write pulse signal (P _w ) is applied to a predetermined anode in synchronization with the scan pulse signal (P _K ) of the cathode, , An erroneous lighting prevention pulse signal having a voltage lower than the bias voltage of the anode is applied to the other adjacent anode in synchronization with the scanning pulse signal. For this reason, when writing to a predetermined display cell, a voltage lower than the bias voltage of the conventional anode is applied to the other display cell that is adjacent to the display cell that has been written and display-discharged via the auxiliary cell. Is applied, that is, the bias voltage (V _m -α: where α is a code indicating a predetermined voltage value) is applied, the influence of the priming effect of the auxiliary discharge is reduced, Therefore, erroneous lighting (erroneous discharge) of adjacent display cells is suppressed. Therefore, the maximum sustaining voltage of the panel can be increased as compared with the conventional case. Therefore,
Since the drive maintenance margin becomes large, it is possible to realize a highly reliable DC type plasma display panel drive with less erroneous lighting.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a driving method of a DC type plasma display panel (hereinafter, also referred to as DC-PDP or simply panel) of the present invention will be described below with reference to the drawings. It should be noted that FIGS. 3 to 5 merely schematically show the components so that the configuration of the present invention can be understood. Therefore, the present invention is not limited to the embodiments described below.

[Configuration of DC-PDP] DC-of this invention
Prior to the description of the driving method of the PDP, the configuration of the DC-PDP panel and the driving circuit used in this embodiment is shown in FIG.
Will be described with reference to.

FIG. 3 shows the DC-type used in the embodiment of the present invention.
It is a principal part block diagram of PDP. The panel and drive unit of this embodiment are roughly composed of four parts.
That is, the four components are the anode driving unit 10, the cathode driving unit 20, the auxiliary anode driving unit 30, and the panel 40.

As an example, the panel 40 is provided with anodes 41 (DA ₁ , DA ₂ , DA ₃ , ..., DA _m and DA _{m + 1} ) in the column direction and a cathode 43 (in the row direction). K
_n-2 , K _n-1 , K _n , K _{n + 1} and K _{n + 2} ) are provided. In addition, between the anode DA ₁ and the anode DA ₂ and the anode D
An auxiliary anode 45 (SA ₁ , ..., SA _j ) is provided between A _m and the anode DA _{m + 1 in} parallel with the anode 41.
Also, the intersections of the anodes DA ₁ , DA ₂ , DA ₃ , ..., DA _m and DA _{m + 1} and the cathodes K _n-2 , K _n-1 , K _n , K _{n + 1} and K _{n + 2.} Each of them is provided with a display cell 42 and has cathodes K _n-2 , K _n-1 , K _n , K _{n + 1} and K _n.
An auxiliary cell 44 is provided at the intersection of _{n + 2} and the auxiliary anodes SA ₁ , ..., SA _j .

In the configuration diagram of FIG. 3, the anodes and the cathodes are shown in 5 columns and 5 rows and the auxiliary anodes are shown in 2 rows for simplification of description, but in reality, a plurality of anodes and cathodes are shown. And an auxiliary anode.

Anodes DA ₁ , DA ₂ , DA of panel 40
_The erroneous lighting prevention pulse signal and the write pulse signal (P _w ) are supplied from the anode driving unit 10 to ₃ , DA _m and DA _{m + 1} . In the anode drive unit 10, the write control information 11
The gate signal generation circuit 12 on the false lighting prevention pulse signal side
And the gate signal generation circuit 14 on the write pulse signal side. The gate signal generation circuit 12 generates a gate signal in response to the write information 11, and supplies the false lighting prevention pulse signal from the false lighting prevention pulse circuit 13 to a predetermined anode 41 in response to the gate signal (details will be described later). ). The erroneous lighting prevention pulse signal is represented here by the symbol P _mp .
On the other hand, the gate signal generation circuit 14 generates a gate signal in response to the write information 11, and in response to this gate signal, a predetermined write pulse signal (represented by the symbol P _w ) from the write pulse generation circuit 15. To the anode 41 (details will be described later).

The cathode driving section 20 includes a gate signal generating circuit 22 and a scan / sustain pulse generating circuit 23.
The scanning / sustaining control information 21 is input to the gate signal generating circuit 22 to generate a gate signal, and the scanning / sustaining pulse generating circuit 23 uses this gate signal to generate a scanning pulse signal (represented by a symbol P _k ). And a sustain pulse signal (representatively indicated by symbol P _SP ) are output. The scan pulse signal P _k and the sustain pulse signal P _sp are supplied to the cathode 43.

The auxiliary anode drive section 30 comprises a gate signal generating circuit 32 and an auxiliary discharge pulse generating circuit 33.
The auxiliary discharge control information 31 is input to the gate signal generation circuit 32 to generate a gate signal, and the auxiliary discharge pulse generation circuit 33 uses this gate signal to generate an auxiliary discharge pulse signal (represented by the symbol P _sa ). Output. This signal P _sa is supplied to the auxiliary anode 45.

FIG. 4 is an enlarged view of the electrode arrangement of the panel 40 of FIG. Here, the display cell at the intersection of the anode DA _m and the cathode K _n is indicated by DC _mn ,
The display cell at the intersection of _{m + 1} and the cathode K _n is indicated by DC _{nm + 1} ,
The auxiliary cell at the intersection of the auxiliary anode SA _j and the cathode K _n is set to DS _nj.
Indicated by

Next, the method of driving the DC-PDP panel of this embodiment will be described with reference to FIGS.

1A to 1B and 2A.
(B) is a timing chart for explaining the DC-PDP driving method of this embodiment. In this embodiment, when the display cell DC _mn is _subjected to the write discharge (ON) and the display cell DC _{mn + 1} is not _subjected to the write discharge (OFF) (the case of FIG. 1A), the display cell DC _{mn is changed} to When the display cell DC _{mn + 1} is not subjected to the address discharge (OFF) but the address discharge is performed (ON) (the case of FIG. 1B), the display cell DC
_{When mn} is not _subjected to address discharge (off) and the display cell DC _{mn + 1} is not _subjected to address discharge (off) (case of FIG. 2A)
And the case where the display cell DC _mn is address-discharged (ON) and the display cell DC _{mn + 1} is also address-discharged (ON) (the case of FIG. 2B) will be described.

First, in the case where the display cell DC _mn is _subjected to the address discharge (ON) and the display cell DC _{mn + 1} is not _subjected to the address discharge (OFF) ((A) of FIG. 1), from time t ₁ to time t ₂ . During the period, the auxiliary discharge pulse signal P _{sa is applied} to the auxiliary anode SA _j.
Is applied. At this time, the bias voltage of the auxiliary discharge pulse signal P _sa is V _m (100 V), and the auxiliary discharge pulse voltage is V _sa (90 V). Further, the scanning pulse signal P _k is applied to the cathode K _n in synchronization with the auxiliary discharge pulse P _sa . After that, the sustain pulse signal P _sp is _supplied to the cathode K at an arbitrary cycle.
_Apply to _n . At this time, the pulse voltages of the scan pulse signal P _k and the sustain pulse signal P _SP are set to the same ground voltage (GN
D: 0 V), and the scan pulse voltage V _k and the sustain pulse voltage V _sp are the same voltage (140 V).

Furthermore, the write pulse signal P _w (pulse voltage V _m : 1 to the anode DA _m is synchronized with the scan pulse signal P _k.
00V, V _w: 80V) is applied to. At this time, the voltage (absolute voltage) between the cathode K _n and the anode DA _m of the display cell DA _m becomes the added voltage (V _k + V _w = 220 V). By applying the write pulse signal P _w in synchronization with the scan pulse signal P _k in the period from time t ₁ to time t ₂ , the display cell DA _mn is discharged. Display cell DA
_{When mn} starts the display discharge, the sustain discharge pulse signal P _sp applied to the cathode K _n maintains the discharge of the display cell DC _mn .

On the other hand, the display cell DC _{mn + 1} adjacent to each other via an auxiliary cell DS _mj to the display cell DC _mn scanning pulse signal P
_The erroneous lighting prevention pulse signal P _mp is applied in synchronization with _k .
Therefore, during the period from time t ₁ to time t ₂ , the voltage (absolute voltage) applied to the display cell DC _{mn + 1} is V _k +
(V _m −α): However, in this embodiment, α is 5 V or 15 V. )become.

Next, in the case where the display cell DC _mn is not _subjected to the address discharge (OFF) and the display cell DC _{mn + 1} is _subjected to the address discharge (ON) ((B) of FIG. 1), the time t ₁ to the time t. ₂
To the auxiliary anode SA _j during the period up to
_{Apply sa} . At this time, the bias voltage of the auxiliary discharge pulse signal P _sa is V _m (100 V), and the auxiliary discharge pulse voltage is V _sa (90 V). The scanning pulse signal P _k is applied to the cathode K _n in synchronization with the auxiliary discharge pulse P _sa . After that, the sustain pulse signal P _sp is applied to the cathode K _n at an arbitrary cycle. At this time, the pulse voltages of the scan pulse signal P _k and the sustain pulse signal P _SP are set to the same ground voltage (GND: 0).
V), and the scan pulse voltage V _k and the sustain pulse voltage V _sp are the same voltage (140 V).

Furthermore, anti-lit in synchronization with the scanning pulse signal P _k erroneous anode DA _m pulse signals P _SP (bias voltage V
_m : 100 V, V _m -α: In this example, since α is set to 5 V or 15 V, V _m -α becomes 95 V or 85 V. ) Is applied. At this time, the voltage (absolute voltage) between the cathode K _n and the anode DA _m of the display cell DA _m is the added voltage (V _k + (V _m −α) = 235 V or 22).
5V).

Further, the write pulse signal P _w is applied to the anode DA _{m + 1} in synchronization with the scan pulse signal P _k . Therefore, in the period from time t ₁ to time t ₂ , the display cell D
Since the write pulse signal P _w is applied to C _{mn + 1} , the display cell DC _{mn + 1} performs display discharge. Display cell DA
_{When mn + 1} starts the display discharge, the display discharge is maintained by the sustain discharge pulse signal P _sp applied to the cathode K _n .

Next, when the display cell DC _mn is not _subjected to the address discharge (OFF) and the display cell DC _{mn + 1} is not _subjected to the address discharge (OFF) ((A) of FIG. 5), the time t ₁ to the time t ₂ are reached. Bias voltage V to the anodes DA _m and DA _{m + 1 for up} to
_{Apply m} . On the other hand, the scanning pulse signal P _K is applied to the cathode K _n.
And the auxiliary discharge pulse signal P _sp is applied. In the case of FIG. 2A, since the write pulse signal is not applied to the anodes DA _m and DA _{m + 1} , the display cells DC _mn and DC _{m
mn + 1} does not discharge.

Next, when the display cell DC _mn is _subjected to the address discharge (ON) and the display cell DC _{mn + 1} is also subjected to the address discharge (ON), the cathode K _n during the period from time t ₁ to time t _2.
Of the anodes DA _m and DA in synchronization with the scanning pulse signal P _k of
_The write pulse signal P _k is applied to _{m + 1} . The cathode K _n has the same structure as that shown in FIGS.
Similarly to the case of (A), the sustain pulse signal (P _sp ) having a predetermined cycle is applied at time t ₃ . In this way, the display cells DC _mn and DC _{mn + 1} can be simultaneously _subjected to display discharge.

In this embodiment, when the write pulse signal P _k is applied only to the predetermined display cells to discharge the predetermined display cells, the scan pulse signal P _k is supplied to the adjacent display cells via the auxiliary cells. Bias voltage V of the anode in synchronization with
_A voltage (V _m −α) lower than _m is applied to the anode. Therefore, the maximum sustaining voltage of the panel can be increased.
Therefore, the drive maintenance margin becomes large, and it becomes possible to drive the DC-PDP with high reliability. The display cell DC
_As a method of preventing erroneous lighting of _{m + 1} , there is also a method of driving the panel by lowering the 0 level (V _m ) of all the lines of the anode. The reactive power (power that does not contribute to the emission of pulses) due to the increase of the pulse amplitude is added to the active power as the power consumption, which is not a preferable method for a drive device that wants to reduce the power consumption as much as possible.

FIG. 5 is a circuit diagram for explaining the operation of the write pulse generation circuit 15 and the erroneous lighting prevention pulse generation circuit 13 of the anode drive section 10.

In this embodiment, anode DA ₁ and anode D
The operation of the anode drive unit 10 (see FIG. 3) connected to A ₂ will be described. In this embodiment, the anode driver 10
In the erroneous lighting prevention pulse generation circuit 13 for the anode DA ₁ line that constitutes the n-channel field effect transistor (F
ET) F ₃₁ and diode D ₃₁ are provided. The anode side of the diode D ₃₁ is connected to the anode DA ₁ line, and the cathode side of the diode D ₃₁ is connected to the drain side of the n-channel type transistor F ₃₁ . On the other hand, the source side of the n-channel type transistor F ₃₁ is connected to the voltage supply source 54 (V _m −α) of the bias voltage of the erroneous lighting prevention pulse signal.

The write pulse generation circuit 15 for the anode DA ₂ line is provided with a p-channel type transistor F ₁₁ and an n-channel type transistor F ₂₁ , and diodes D ₁₁ and D ₂₁ . The source side of the p-channel type transistor F ₁₁ is connected to the voltage supply source 50 of the write pulse signal P _w . Therefore, the write voltage V _w is supplied from the voltage supply source 50. The drain side of the p-channel transistor F ₁₁ is connected to the anode DA ₁ .
The anode side of the diode D ₁₁ is connected to the line of the anode DA ₁ , and the cathode side of the diode D ₁₁ is connected to the drain side of the n-channel type transistor F ₂₁ . On the other hand, the source side of the n-channel type transistor F ₂₁ is connected to the voltage supply source 52. Therefore, the bias voltage V _m is supplied from the voltage supply source 52 to the anode DA ₁ . Furthermore, the anode side of the diode D ₂₁ is connected to the source side of the n-channel type transistor F ₂₁ , while the cathode side is connected to the anode DA ₁ . The configuration of the lighting prevention pulse generation circuit 13 and a write pulse generating circuit 15 erroneously connected to the anode DA ₂ are identical to those connected to the anode DA _1, the circuit configuration that is connected to the anode DA ₂ here Will be omitted.

Next, referring to FIG. 5, the anodes DA ₁ and DA ₁
The circuit operation _{when 2} to a write pulse signal P _w and erroneous lighting prevention pulse signal P _mp supplied to the anode DA ₂ and DA ₂ will be described.

When the write pulse signal P _w is supplied to the anode DA ₁ , the F ₁ gate signal 56 from the gate signal generating circuit (not shown) is applied to the gate side of the transistor F ₁₁ . This gate signal 56 turns on the p-channel transistor F ₁₁ . Therefore, the write pulse voltage V _W is applied to the gate of the p-channel type transistor F ₁₁ from the power supply source 50 side, and
Current flows from the source side to the drain side of ₁₁ and the anode DA ₁
Reach Therefore, the write pulse voltage V is applied to the anode DA _1.
w is supplied.

On the other hand, when supplying the bias voltage V _m to the anode DA ₁ , the p-channel transistor F ₁₁ is turned off, and then the F ₂ signal from the gate signal generation circuit is applied to the gate of the n-channel transistor F ₂₁ . The voltage is applied to the side to turn on the n-channel type transistor F ₂₁ . At this time, since the write pulse voltage V _w is applied to the anode DA ₁ , current flows through the diode D ₁₁ and the n-channel transistor F ₂₁ and reaches the power supply source 52. Therefore, the anode DA ₁ has the bias voltage V _m .

Next, when supplying the false lighting prevention pulse signal P _mp to the anode DA ₂ , the n-channel transistor F _{32 is used.}
By applying the F ₃ gate signal 58 from the gate signal generation circuit to the gate side of the
_{Turn 32} on. At this time, since the bias voltage V _m is applied to the anode DA ₂ , current flows through the diode D ₃₂ and the n-channel transistor F ₃₂ and reaches the power supply source 54. The erroneous lighting prevention pulse voltage V _m -α is set in the power supply 54, so that the anode DA ₂ becomes the bias voltage V _m -α.

Next, when the line of the anode DA ₁ is the bias voltage and the line of the anode DA ₂ is the write voltage V _w , the F ₂ gate signal 60 is the n-channel transistor F.
_It is supplied to the gate of ₂₁ to turn on the n-channel transistor F ₂₁ . At this time, as described above, the anode DA ₁
Bias voltage V _m is applied to the line. Also, F
_The transistor F ₁₂ is turned on by applying the _1- gate signal 56 to the gate of the p-channel transistor F ₁₂ . In this case, it means that the write pulse voltage V _w is applied to the source side of the p-channel transistor F _12, current flows through the p-channel transistor F _12, the line anodes DA ₂ write pulse voltage V _w is supplied. The case where the bias voltage V _m is supplied to the anodes DA ₁ and DA ₂ and the case where the write pulse voltage V _w is supplied at the same time can be easily realized by a combination of the operations described above, and therefore the description thereof is omitted here. . As can be understood from the above description, in the embodiment of the present invention, during the period in which the write pulse signal is applied to the predetermined anode in synchronization with the scanning pulse signal, the write pulse signal is adjacent to the predetermined anode via the auxiliary anode. An erroneous lighting prevention pulse signal having a voltage lower than a predetermined bias voltage of the anode is applied to the other anode in synchronization with the scanning pulse signal. Therefore, the voltage (V _sp + (V _m −α)) between the bias voltage applied to the other anode and the sustain pulse voltage of the cathode is lower than in the conventional case.
Therefore, the maximum sustaining voltage of the DC type plasma display panel is increased, so that the driving sustaining margin can be increased. As the drive maintenance margin increases, erroneous lighting of the panel decreases, so that it is possible to drive the panel with high reliability even when the panel becomes large.

The above-described write pulse generation circuit and erroneous lighting prevention pulse generation circuit are not limited to this embodiment, and any other circuit can be used as long as it can generate a write pulse signal or an erroneous lighting prevention pulse signal at a certain timing. The circuit configuration of

Further, the auxiliary discharge pulse voltage V _sa , the address pulse voltage V _w , the bias voltage V _m , which are used in this embodiment,
The respective values of the scan pulse voltage V _k and the sustain pulse voltage V _sp show the optimum values in this embodiment, and therefore, it goes without saying that the respective voltage set values will change if the panel structure changes.

[0042]

As is apparent from the above description, in the driving method of the DC type plasma display panel of the present invention, the drive maintaining margin can be increased as compared with the conventional method, so that the erroneous lighting of the panel is reduced. Therefore, even if the size of the panel is increased, it is possible to drive the panel with high reliability.

[Brief description of drawings]

1A and 1B are D of an embodiment of the present invention.
It is a timing chart figure offered in order to demonstrate the drive method of C-PDP.

2A and 2B are D of an embodiment of the present invention.
It is a timing chart figure offered in order to demonstrate the drive method of C-PDP.

FIG. 3 is a block diagram of a DC-PDP used in an embodiment of the present invention.

FIG. 4 is an electrode array diagram showing a partially enlarged panel portion of a DC-PDP used in an embodiment of the present invention.

FIG. 5 is a write pulse generation circuit and erroneous lighting prevention pulse generation circuit diagram provided for explaining the operation of the anode driving unit of the present invention.

[Explanation of symbols]

10: Anode drive unit 11: Write control information 12: Gate signal generation circuit 13: False lighting prevention pulse generation circuit 14: Gate signal generation circuit 15: Write pulse generation circuit 20: Cathode drive unit 21: Scanning / maintenance control information 22: Gate signal generating circuit 23: Scanning / sustaining pulse generating circuit 30: Auxiliary anode driving unit 31: Auxiliary discharge control information 32: Gate signal generating circuit 33: Auxiliary discharge pulse generating circuit 40: Panel 41: Anode 42: Display cell 43: Cathode 44: Auxiliary cell 45: Auxiliary anode 50: Write pulse voltage supply source 52: Bias voltage V _m supply source 54: Bias voltage V _m -α supply source 56: F ₁ gate signal 58: F ₃ gate signal 60: F ₂ gate signal

Claims (1)

[Claims] 1. A plurality of cathodes and anodes provided at right angles to each other, a display cell provided at an intersection of the cathode and the anode, an auxiliary electrode provided between the anodes in parallel with the anode, and the auxiliary. An auxiliary cell is provided at an intersection of the electrode and the cathode, a scan pulse signal (P _K ) and a sustain pulse signal (P _sp ) are applied to the cathode, and a bias voltage and a write pulse signal are applied to the anode. (P _W ) and an auxiliary discharge pulse (P _sa ) are applied to the auxiliary anode, and the scan pulse signal, the sustain pulse signal, the write pulse signal, and the auxiliary discharge pulse signal are applied. a method of driving a DC plasma display panel for display discharge by adjusting the timing, the in synchronization with a predetermined anode scanning pulse signal of said cathode (P _K) writing pulse signal (P _w Is applied to the other anode adjacent to the predetermined anode through the auxiliary anode, the erroneous lighting prevention pulse signal having a voltage lower than the bias voltage of the predetermined anode in synchronization with the scanning pulse signal. A method for driving a direct-current plasma display panel, which comprises applying a voltage.