JPH08287199A - Device and method for transferring noise reduced noncontact parallel data - Google Patents

Abstract

PURPOSE: To provide an electromagnetic coupling type noncontact parallel transfer memory card which attains a fast transfer rate, has a small-sized, high-density, and lightweight structure and is high in reliability. CONSTITUTION: Write data to a memory 8 are grouped in two and after timing delay circuits 4-1 and 4-2 shift the phases and make the data into pulses, a pulse current in the same timing is not supplied to an adjacent transfer coil 1-n. Consequently, the peak value of a pulse current accompanying coil driving is reduced and the influence of crosstalk between coils becomes extremely small, so the noncontact memory card is provided which is small-sized, high in reliability, and fast in transfer rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low noise contactless parallel data transfer apparatus for transferring signals and power supplies in a contactless and parallel manner, and more particularly to a contactless contactless data transfer apparatus suitable for a portable memory device such as a memory card. A parallel data transfer apparatus and method.

[0002]

2. Description of the Related Art In recent years, a method using an electromagnetic coupling coil has been adopted as a non-contact type connecting means for supplying data to a memory card. For example, JP-A-4-23
As disclosed in Japanese Patent No. 9990, two sets of corresponding transmission coils and reception coils are provided, and necessary data is exchanged by electromagnetic coupling as a 1-bit data signal sequence.

As a type for preventing crosstalk between adjacent transfer coils, for example, Japanese Patent Laid-Open No. 3-23 is available.
As disclosed in Japanese Laid-Open Patent Publication No. 2207, a shield structure for providing a plurality of transmission / reception coils to transfer a plurality of bits at the same time and reducing the magnitude of mutual interference between bits (amount of crosstalk between bits) generated Is provided between the coils.

On the other hand, there is also known a method of shifting the drive timing between data bits in order to reduce the noise component induced in the power supply line or the ground line.
It is disclosed in Japanese Patent No. 54993.

Further, as disclosed in Japanese Patent Laid-Open No. 5-114055, a card side which receives electric power from a pair of transfer coils and a low frequency component induced from a power transfer coil located between the transfer coils. Some have a means to cancel.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The prior arts disclosed in Japanese Patent Application Laid-Open No. 990 and Japanese Patent Application Laid-Open No. 3-232207 and the like are, firstly, an extremely large peak current that is inevitably generated when information pulses of high speed and large amplitude are transmitted in parallel by electromagnetic coupling. Is not considered, and not only the scale of the power supply circuit supplied from the outside by electromagnetic coupling becomes large, but also high-energy pulse fluctuations occur as a whole, which not only causes crosstalk between transfer coils. However, there is a problem in that the probability of malfunctions inside the card increases, which causes a decrease in reliability. In particular, as the plurality of coils are mounted at a higher density, the amount of crosstalk between the coils, which is inevitably generated, increases, which is a factor that hinders the transfer coil from having a higher density.
As such measures, for example, Japanese Patent Laid-Open No. 3-232207
As disclosed in Japanese Laid-Open Patent Publication No. 2003-242242, electromagnetic shield means is provided between the coils, but there is a problem in that it is not possible to shield the entire surface of the coil and the effect of the leakage magnetic field from the peripheral coil cannot be ignored. However, it was a bottleneck in the practical application of the non-contact parallel transfer method using the electromagnetic induction coil.

Second, there is a problem of energy concentration when pulse signals transferred in parallel are transferred simultaneously at the same timing. For example, 1 coupling coil (1 channel)
Assuming that a driving current of 10 milliamps is required per unit, and if "1" is transferred simultaneously for 16 channels, a pulse current of 160 milliamps containing extremely high frequency components will be generated, and the capacity of the driving source will be increased. In addition, it becomes a noise source of the noise induced in the power supply line. In addition to such an instantaneous current, the power consumption of peripheral circuits increases in proportion to the increase in data transfer rate.
It was a bottleneck for realizing high-speed transfer.

Thirdly, in spite of the non-contact method in which the plug connector is eliminated, consideration for reverse insertion from the front and back is lacking, and restrictions on the user are added, so that the usability is not improved. There was a problem that was not done.

An object of the present invention is a non-contact parallel data transfer memory which is small in size, high in density and excellent in reliability and which can prevent malfunction caused by crosstalk between coils without providing a physical shield space. Is to provide a card.

Another object of the present invention is to provide a small size, high density and excellent reliability by limiting the magnitude of the peak current generated during data transfer even if the non-contact multi-bit parallel transfer method by electromagnetic coupling is used. Another object is to provide a contactless parallel data transfer memory card.

Still another object of the present invention is to cope with large power consumption at the time of high speed operation and to improve the reliability of starting the data transfer operation after confirming that the external device has truly supplied the power to the card side. An object is to provide an excellent contactless parallel data transfer memory card.

Still another object of the present invention is to provide a convenient non-contact parallel data transfer memory card which can be inserted into a data transmitting / receiving device (such as a personal computer) without being aware of the front and back of the memory card. .

[0013]

In order to achieve the above object, a first coil group provided for parallel transfer of access data to a portable memory device, and at least write data to the portable memory device. For supplying data to the first coil group from the data server, and a second coil group provided so as to face each coil of the first coil group for supplying data from the data server; A non-contact holding means for holding the first coil group and the second coil group close to each other in a facing state, and a pulse train of data for transferring in parallel between the first coil group and the second coil group. And a parallel pulse generating means having a delay means provided at least in the data server, the delay means comprising a first cavalry par at least a first bit number. It is divided into a pulse group and a second parallel pulse group having a second bit number, and the parallel transfer timing of the second parallel pulse group is smaller than the parallel transfer timing of the parallel pulse group of the first generation. Also comprises means for delaying a time longer than the pulse width of each bit.

Furthermore, instead of the means for delaying,
In order to cancel a crosstalk component generated in the receiving side coil adjacent to the first coil pair of the facing coil pairs of the first coil group and the second coil group, the first coil pair is canceled. And a means for supplying a part of the transfer signal to the adjacent receiving side coil with its phase reversed.

Further, the present invention relates to the above-mentioned device and its method, and to a new IC memory card which is a component thereof. That is, the IC memory card according to the present invention is
A first coil group provided to face the respective coils of the second coil group provided in the data server for parallel transfer of access data, and the first coil group.
Of the means for generating data as parallel pulses and the means for receiving data as parallel pulses when the coils of the second coil arm are closely opposed to each other and the data are transferred in parallel. Have at least one means,
The parallel pulse is divided into a first parallel pulse group having at least a first bit number and a second parallel pulse group having a second bit number, and the transfer of the second parallel pulse group. The timing is characterized by the parallel pulse delaying by a time longer than the pulse width of each bit of the first parallel pulse group.

Furthermore, in the IC memory card according to the present invention, instead of the above-mentioned delay, the first coil pair of the opposing coil pairs of the first coil group and the second coil group is replaced by the first coil pair. In order to cancel out the crosstalk component generated in the adjacent receiving side coil, a part of the transfer signal of the first coil pair is supplied to the adjacent receiving side coil with the phase reversed. .

More specifically, the transfer data of parallel bits set at the same timing is, for example, 2
To 4 groups (for example, in the case of 4 groups, 16-bit data is divided into 4 groups of 4 bits each), and a delay circuit and an edge detection differentiating circuit having different delay times are inserted in each group. did.

Further, the data lines of the different timing groups are connected to adjacent coils of the plurality of transmission coils.

Further, a gate circuit corresponding to a plurality of receiving coils sent in different timing groups and a timing generating circuit for predicting and determining the respective timings are provided.

Further, the auxiliary receiving coil is provided in the receiving coil, and the auxiliary receiving coil is connected to the adjacent receiving coil.

Further, a current having an opposite phase smaller than the drive current to the transmitting coil is applied to the adjacent transmitting coil.

Also, the transmission drive circuit and the reception amplifier circuit are connected to one end of the electromagnetic coupling coil.

In order to achieve the above-mentioned other objects, an electrode terminal composed of a spring member for power supply is provided on the external device (server) side, and an external wall is provided on the card side for receiving the external power supply. The plate-shaped electrode terminals of were closely contacted.

It is also possible to embed the electrode terminals for receiving the external power supply in the groove portions for preventing the card from being inserted in the opposite direction.

It is also possible to insert a resistor between the power supply on the external device (server) side and the power supply electrode for the external card.

In order to achieve the above-mentioned other object, the phase of the signal supplied to the coil located at one end (frontmost portion or rearmost portion) of the electromagnetic coupling transmission coil array is located at the remaining one end side of the coil array. 90 for the signal supplied to the coil
It is also applicable to insert a delay circuit.

The received signal from the coil located at the forefront of the electromagnetic coupling receiving coil array and the received signal from the coil located at the rearmost of the array, that is, the signals received by the coils located at both ends of the coil array. It is also applicable to provide a circuit for detecting the relative phase difference and a multiplexer circuit for switching the arrangement order of the signals received from the coil train.

It is also applicable to provide a means for rectifying the received signal output from the coils located at the both ends.

[0029]

A waveform obtained by passing parallel data bits through a delay circuit having a different delay time for each group and differentiating its edge can be used as a drive timing pulse for a signal transmitting coil. As a result, the peak current of the coil drive current is dispersed in the time axis direction. For example, in the case where a delay circuit having four types of delay times is provided, the value of the peak current is reduced to 1/4, Since the set capacity of the power supply is greatly eased and the energy of the pulse noise source inside the memory card is reduced, it is possible to realize a compact and highly reliable non-contact parallel data transfer memory card system. is there.

Further, by driving the adjacent coils of the signal transfer coil group (column) using pulses at different timings, magnetic lines of force (flux) between the adjacent coils.
Is not added and emphasized, the leakage magnetic field strength is small, and the amount of crosstalk to other coils is reduced. This eliminates the need for physical measures such as shielding between coils, and has the effect of realizing a compact and highly reliable non-contact parallel data transfer memory card system.

Further, in the prediction timing generation circuit, by generating a pulse having a prediction period width that will induce a signal to the corresponding receiving coil as a gate signal of the gate circuit, outside the prediction period, for example, to an adjacent coil. The crosstalk noise and the like generated at the driving timing of 1 operates so as not to pass through the gate circuit. As a result, even if a large crosstalk noise is induced from an adjacent coil or the like, it is not affected at all, so that it is possible to realize a compact and highly reliable contactless parallel data transfer memory card system. The effect is that you can do it.

The auxiliary receiving coil is set to have a number of turns capable of receiving a voltage equal to the amount of crosstalk induced voltage to the adjacent coil, and is connected in series so as to have a phase opposite to that of the adjacent coil so that the crossing in the adjacent coil is increased. The talk components operate so as to cancel each other out. As a result, it is possible to prevent a malfunction due to the occurrence of crosstalk to the adjacent coil, and it is possible to realize a highly reliable non-contact parallel data transfer memory card system.

Further, the anti-phase drive signals applied to the adjacent transmitting coils operate so as to cancel the crosstalk components to the adjacent receiving coils which are paired with the adjacent transmitting coils and face each other. As a result, it is possible to prevent a malfunction due to the occurrence of crosstalk to the adjacent coil, and it is possible to realize a highly reliable non-contact parallel data transfer memory card system.

By connecting the transmission drive circuit and the reception amplifier circuit to the same coil, the data transferred in the previous cycle can be sent back to the gap portion of the timing-shifted drive signal. As a result, the read check after writing to the memory, so-called read-after-write check, can be performed without increasing the number of transfer coils and without increasing the peak current, so it is small and highly reliable. There is an effect that a contactless parallel data transfer memory card system can be realized.

Also, since it is only necessary to prepare two pins for the power supply electrode terminals from the external device (server) side to the card side, it is possible to adopt a relatively robust structure,
In addition, the mounting space is smaller than the method of supplying a relatively large amount of power magnetically with a transformer structure. As a result, there is an effect that it is possible to realize a compact and highly reliable non-contact parallel data transfer memory card system that can cope with high power consumption during high-speed operation.

Further, according to the structure of the power supply receiving electrode terminal provided in the front and back reverse insertion preventing notch portion on the card side, it is located in the narrow concave portion of the card, which is caused by contact with fingers and dirt. Contact failure can be prevented. As a result, there is an effect that it is possible to realize a compact and highly reliable non-contact parallel data transfer memory card system that can cope with high power consumption during high-speed operation.

Also, by confirming the potential drop of the resistance inserted in the power supply line of the external device side, it is confirmed that the actual load is connected, that is, the card for data transmission / reception is the external device (server). It is possible to detect that the power supply has been started. As a result, it is possible to prevent a situation in which high-speed data transfer is started without any external power supply to the card due to some abnormality in the power connection.
There is an effect that it is possible to realize a compact and highly reliable non-contact parallel data transfer memory card system.

Further, shifting the phase difference of the signals supplied to the coils located at both ends of the electromagnetic coupling transmission coil array by 90 degrees means that the memory card insertion / reception side (for example, a personal computer) has a protrusion or the like. The left and right positions of the insertion surface are declared regardless of the physical method. As a result, it is possible to easily detect and correct the erroneous insertion of the memo value card, so that it is possible to provide a convenient non-contact parallel transfer memory card.

The circuit for detecting the phase difference between the signals induced in the coils located at both ends of the electromagnetically coupled receiving coil array is provided on the surface of the memory card (in the area of the memory card having a hexahedral thin plate structure). 2 in the order of ascending order, the longitudinal side surfaces and the 2 lateral side surfaces, and the remaining 2 surfaces are referred to as front and back sides for convenience) are inserted upward or to the right or vice versa. It operates to detect whether it has been inserted with the surface down or left. As a result, when it is recognized that the case is the reverse insertion case (the state where the surface of the memory card is inserted downward or left), the arrangement order of the receiving coil rows, that is, the data arrangement order is switched left and right. Since the multiplexer circuit operates as described above, it is not necessary to consider the front and back of the memory card when inserting the memory card, and thus it is possible to provide a convenient non-contact parallel transfer memory card.

Further, the means for rectifying the signals induced in the coils located at both ends of the electromagnetically coupled reception coil array operates so as to generate a DC voltage from the signal for detecting the front / back interchange insertion. As a result, the external power supply coil for data transfer is also used as the front / backside replacement insertion detection coil, and it is not necessary to take additional measures for the external power supply coil, and the power supply side does not require memory when the memory card is inserted. Since there is no need to consider the front and back of the card, it is possible to provide a convenient non-contact parallel transfer memory card.

[0041]

EXAMPLES Prior to the description of the concrete structure of the example, background factors that regulate the specifications of the structure, particularly crosstalk between transfer coils, will be described. Hereinafter, a transfer coil module corresponding to the present embodiment, which has been experimentally manufactured in consideration of data of an experiment conducted to examine actually occurring crosstalk and restrictions on external dimensions, will be described with reference to the drawings.

FIG. 16 (a) shows a measuring circuit for an inter-channel crosstalk experiment. Primary (transmission) side coil T0
Secondary (reception) side coils T02, T12, T22 and T23 corresponding to 1, T11, T21 and T31 are
Each of the ferrite core bobbins has 10 enamel clothing wires.
Winding for 20 to 20 turns, coils facing each other,
For example, a combination of T01 and T02, T11 and T12, etc. forms a kind of electromagnetic coupling transformer. The spacing between the ferrite cores for the coils in the primary and secondary coil blocks (coil rows) was made variable as an experimental variable, and the gap between the ferrite for the primary coil and the ferrite for the secondary coil was used as a parameter. I fixed it and investigated several ways. In the actual experiment, this parameter value was also used as a variable. As shown in FIG. 16A, the primary side drive signal is e0.
A pulse signal having a volt amplitude is applied to a resistor Rd (e0: + in the experiment)
5 V, Rd: 470 Ω) was applied to the primary side coils T01 and T31. A resistor Rd (470Ω) and a contact of the toggle switch SW are inserted in series at T31 as shown in the figure. The load resistance RL (470 Ω) is connected to the secondary coil T12, the regular reception level e1 is observed with an oscilloscope, the load resistance RL (470 Ω) is also connected to the adjacent coil T22, and the crosstalk level e2 is measured by the same means. Observed at. FIG. 16B is measurement data showing the experimental result. The abscissa is the adjacency in the coil block of the ferrite core around which the coil is wound, and the ordinate is the decibel representation of the induced voltage to the secondary side when the primary side drive voltage e0 is 0 decibel (dB). (E.g., when transmitted after being attenuated to 1/10,
It becomes dB). The regular induced voltage e1, that is, the induced voltage to the secondary side, is a constant value of -11 dB (about 1.4 dB) regardless of whether the core spacing or the switch (see FIG. 16A) is opened or closed.
Bolt). However, the induction to the adjacent coil, that is, the crosstalk voltage e2 has a larger value as the core interval becomes narrower. For example, when the adjacent distance is 1 millimeter, it is -30 dB (about 1/32), and is 156
Millivolt crosstalk occurs. Here, when the switch (see FIG. 16A) is closed and a drive current is also applied to the coil T31, the crosstalk voltage e2 to the secondary coil adjacent to both is −24 dB (about 5 V). 1
1/6; 312 millivolts).

FIG. 17 shows a PCMCIA (Personal Computer) widely used as a conventional standard for memory cards.
Memory Card International Association) Standard / Type III memory card external view and a diagram assuming a non-contact parallel transfer coil is applied to it. The type II memory card has a length of 85.6 mm, a width of 54.0 mm, a thickness of 3.3 mm in the peripheral part required for insertion and a conventional contact type plug, and a thickness of 5.0 in the central part. It is specified as millimeters. A printed circuit board 91 on which components such as a memory are mounted is housed inside a card case 90 molded in such a size, and a 68-pin contact type connector is usually provided at a plug portion (lower end portion in the drawing). Are placed. Here, in order to achieve non-contact transfer as in the present invention, it is necessary to attach an electromagnetic coupling coil instead of the contact type 68-pin connector. In this case, the above-mentioned FIG.
It is also possible to initially adopt 16-pin while avoiding the crosstalk shown in (b). Even when a non-contact parallel transfer coil is used in consideration of conformity with the above standard, the core holder 92
The longitudinal dimension of is required to be 50 mm or less. Here, when arranging coils of 16 channels, it is necessary to arrange the coils at a pitch of 3 mm or less as illustrated.

FIG. 18 is an external view of a coil array used in this embodiment and being put to practical use. Core holder 92
In addition, as shown in the drawing, a "U-shaped" single ferrite core 93 of 2 mm square is spaced by 1 mm (see FIG. 16).
16 pieces are attached according to the experimental results of (a) and (b). The core holder 92 is a plate-like body made of a non-dielectric material such as a glass member and having a length of 4 mm, a width of 48 mm and a thickness of 0.3 mm, and is surface-mounted to the printed circuit board 91 by soldering.

The case of the coil block of 16 channels has been described in detail above.
Since 68 pins and the like have been put into practical use as in the CIA standard, it is desired that the parallel transfer device of the present invention which is a non-contact type has higher density. In that case, a particular problem is crosstalk between adjacent coils as shown in FIG. 16 (b), and such electromagnetic induction noise may increase rapidly when the distance between adjacent coils becomes 1 mm. It is also clear from FIG. 16 (b). It should be noted that it is expected that such crosstalk will not only be electromagnetic induction by electromagnetic coupling but also electrostatic induction by electrostatic coupling between coils when the density is extremely increased.

The present invention provides a novel non-contact parallel data transfer device which avoids the above-mentioned crosstalk and avoids concentration of pulse energy, and a portable memory device using the same. Hereinafter, each example will be described in detail so as not to be specific.

First, a first embodiment will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data supply device (a data server such as a personal computer) and a non-contact parallel transfer memory card used in the first embodiment, in which only parts relevant to data transfer are extracted. . The data bus, the address bus and the dedicated control line included in the internal bus 11 of the data supply device 9 which uses the personal computer function are input to the data transmission control circuit 3 to read an 8-bit data string and read.
It is converted into a write control signal and output. That is, at the beginning of the data transfer, the designated address number on the memory card side (designated with 20 bits in the embodiment) is first output as 8-bit parallel data (byte unit data) in three times, and then the data string to be transferred. Are sequentially output in byte units, and at the same time a write request signal WTREQ to the memory (a read request signal RDREQ when the personal computer side reads the data)
Occurs for each data output. Here, the 8-bit output data is divided into even-numbered (bit 0, bit 2, bit 4 and bit 6) 4 bits and odd-numbered (bit 1, bit 3, bit 5 and bit 7) 4 bits, The former even-numbered bit data string is the α timing delay circuit 4
-1, and the latter data string of odd numbered bits is distributed and input to the β timing delay circuit 4-2. The α-timing delay circuit 4-1 and the β-timing delay circuit 4-2 are based on the concept of two-phase clock control (a reference phase based on one cycle of the main clock and 180 degrees from the reference phase).
In a system in which two timing references of delayed phases delayed by two degrees are provided), each is composed of a register and a pulsing circuit controlled by a reference phase timing α and a register and a pulsing circuit controlled by a delay phase timing β. (Details not shown). The output of the α timing delay circuit 4-1 is pulsed in synchronization with the α timing (1/4 time width pulse of the maximum data transfer period) RZ.
(Return zero; the signal level is always at a level indicating "0", and becomes a level indicating "1" only when the data is "1", but it always returns to "0" level after a lapse of a predetermined time) It is a signal and drives even-numbered coils 1-0, 1-2, 1-4 and 1-6 of the transmission coil array 1 via the α-phase data bus 12-1 and the coil drive circuit 5 (predetermined current And the one β-timing delay circuit 4-2 is pulsed RZ synchronized with the β-timing.
It outputs a signal and drives the odd-numbered coils 1-1, 1-3, 1-5, and 1-7 of the transmission coil array 1 via the β-phase data bus 12-2 and the coil drive circuit 5. . The individual coils 2-0 to 2-7 forming the receiving coil array 2 arranged at the positions corresponding to the transmitting coil array 1 have the same magnitude of the drive current to the transmitting coils 1-0 to 1-7. Receive a proportional electromagnetic induction signal. That is, the pulsed RZ signal synchronized with the α timing is received by the receiving coils 2-0 and 2-2 and 2-4 and 2-6, while β
The pulsed RZ signal synchronized with the timing is received by the reception coils 2-1 and 2-3 and 2-5 and 2-7, and the reception control is performed at each timing via the reception amplifier circuit 6 and the reception data bus 13. A set-reset type flip-flop (detailed configuration is not shown) forming the inside of the circuit 7 is set (only when the data is “1”). Here, the reception control circuit 7 recognizes that the first 3 bytes of the transfer data string is address information, updates the address bus data for the memory 8 (means that the write first address has been set), and then Received data is placed on the data bus of the memory 8 and a write enable signal WE (Write Enable) signal is generated (transmission coil 1-
8 and the receiving coil 2-8 to reflect the reception of the write request signal WTREQ previously received), and the W
By adding 1 to the address bus data using the trailing edge of the E signal, preparation for writing to the next memory address is made. In order to read the contents of the memory 8, a read request signal RDREQ is driven from the personal computer (data supply device) 9 side to drive the transmission coil 1-9 and give it to the reception control circuit 7 via the reception coil 2-9. However, the reading circuit system at that time is complicated, so the illustration is omitted here. FIG. 2 is a logical development view showing the signal input section of the contactless transfer memory card in more detail. Inside the contactless transfer memory card 10, only the receiving coil array 2, the receiving amplifier circuit 6, and the data input-related portion of the receiving control circuit 7 are shown, and the other constituent blocks are omitted for the sake of simplicity. The gate signal generation circuit 41 uses the system clock 2fCLK (supplied by a separate means from the data supply device side) as a base, and receives a signal transmitted at α timing (α signal
G) 45 and a gate signal (βG) 44 for receiving a signal transmitted at β timing and set /
Reset type flip-flops 43-0 to 43-
A reset signal for 7 is generated. On the other hand, the coils 2-0, 2-2, 2-4 and 2-6 belonging to the group that receives the α timing transmission signal in the receiving coil array 2
Is the α gate signal 45 via the reception amplifier circuit 6.
Gate circuits 42-0, 42-2, 4 having one input as
2-4 and 42-6, and the gated signals are input to flip-flops 43-0, 43-2, 43.
-4 Further, the coils 2-1, 2-3, 2-5 and 2-7 which are connected to the respective set terminals of 43-6 and belong to the group for receiving the β timing transmission signal in the receiving coil array 2 are also provided. , Gate circuits 42-1 and 42 which receive the β gate signal 44 as one input via the reception amplifier circuit 6
-3, 42-5 and 42-7, and the gated signals are input to flip-flops 43-1 and 43-, respectively.
3, 43-5 and 43-7 are connected to respective set terminals, and transfer data of 1 byte is transferred to the flip-flop 4
3-0 to 43-7. That is, the signal components other than the vicinity of the timing when the transfer is predicted by the operation of the gate circuits 42-0 to 42-7 are flip-flops 43.
It is forbidden to transmit to 0 to 43-7.

FIG. 3 is a time chart of the data part (address part is omitted) for explaining the first embodiment. Hereinafter, description will be made with reference to FIG. The clock applied to the transmission control circuit (3 in FIG. 1) is a rectangular wave signal 2 having a frequency twice the transfer frequency (20 MHz in the embodiment).
fCLK, which is a write command W from the host-side controller (data supply device 9 in FIG. 1) to the external memory card
Data DATA0 to DATA to be written at the same time as TCOM
ATA7 is given. Here, the DATA0 to DATA
ATA7 is hexadecimal notation "FF" (all bits of 8-bit data are "1"), "0F" (upper 4 bits are "0" and lower 4 bits are "1"), "F0" (upper bits) 4 bits are "1" and lower 4 bits are "0") Last is "FF"
It was assumed that it was. Groups (DATA0α, DATA2α, DATA4α, DAT) that operate at α timing are provided in the latch register inside the transmission control circuit.
A6α) and a group that operates at β timing (DATA
1β, DATA3β, DATA5β, DATA7β), and data is set at the falling edge of each timing. An output signal (#) which is obtained by performing a logical product of the register outputs DATA0α to DATA6α and a negative signal of the α part of the 2fCLK (a logical product of “true” when the α part of the 2fCLK is at a low level).
0-DRIVE, # 2-DRIVE, # 4-DRIVE
And # 6-DRIVE) as well as the outputs DATA1β to DATA7β of the register and β of 2fCLK.
Output signal (# 1-DR
IVE, # 3-DRIVE, # 5-DRIVE and #
7-DRIVE) is a drive current waveform to each coil (1-0 to 1-7 in FIG. 1) of the corresponding transmitting coil array (1 in FIG. 1).

4 (a) and 4 (b) are external views showing the mounting state during data transmission / reception in this embodiment.
FIG. 4A is a sectional view seen from the upper surface, and FIG. 4B is a sectional view seen from the side surface. A non-contact parallel transfer memory in which the transmission coil array 1 is arranged in parallel with the bottom surface in the deepest part of the notch of the data supply device 9 and the reception coil array 2 is arranged so as to correspond to the transmission coil array 1. By inserting the card 10 into the notch, data is transferred by the electromagnetic coupling action of the coil. At this time, since the transfer efficiency is improved by making the gap between the transmitting coil array 1 and the receiving coil array 2 as narrow as possible, the interaction using the attractive force of the permanent magnet or the mechanical repulsive force of the spring. Thus, a structure is adopted in which a force acts in the direction in which the two sets of coil rows 1 and 2 are brought into close contact with each other (not shown).

According to the first embodiment, the peak value of the current accompanying the driving of the transmitter coil is halved, especially when the data is sent back from the card side, that is, when the memory data is read. In (not shown and described), not only contributes to downsizing of the power supply circuit, but also the energy of the noise signal source is halved, so a highly reliable electromagnetic coupling type non-contact parallel transfer memory card The system can be realized. Further, since the adjacent coils are driven at different timings, and the noise signal induced at the driving timing of the adjacent coils is eliminated by the gate circuit, this is a fatal defect when a large number of induction coils are used. There is no fear of malfunction due to crosstalk noise, and it is possible to provide an extremely reliable non-contact parallel transfer memory card system.

In the above embodiment, the data is transferred by dividing it into two timings, but it is of course possible to increase the number of distribution timings to 3, 4, and 5, and the number thereof can be increased. The greater the number, the longer the time required for data transmission / reception, but on the other hand, the peak current value is also leveled and reduced, and the above effect is further enhanced.

Next, a second embodiment will be described with reference to the drawings. The second embodiment is an example in which measures are taken so that it can be dealt with even when the front and back (upper and lower) of the card are inserted in the opposite direction (see FIG. 4 of the first embodiment).

FIG. 5 shows a data supply device (personal computer) 9 and a non-contact parallel transfer memory card 10 used in the second embodiment.
It is a block diagram which extracted only the part relevant to the data transfer of. This drawing corresponds to FIG. 1 in the first embodiment, and the main difference on the data supply device 9 side from FIG. 1 is that the coils 1-0 to 1- constituting the transmitting coil array 1 are different.
7 and 1-8 and 1-9 are provided with coils for special signal transmission 1-R and 1-L and a circuit for supplying a signal to the additional coils at both ends of the memory card 10 side. The main difference is that the coils 2-0 to 2-7 and 2-8 and 2-9 forming the receiving coil array 2 are provided with special signal transmitting coils 2-R and 2-L and the additional coil. That is, a circuit and the like for processing the reception signal of is added. Therefore, the description of the part overlapping with the description of FIG. 1 is basically omitted. The rectangular wave signal generated by the transmitting circuit 21 drives one of the additional transmitting coils 1-R via the coil driving circuit 5-R, and at the same time delays the signal phase by 90 degrees by the phase delay circuit 22 and then the coil driving circuit 5-R. A signal is supplied to the remaining extension coil 1-L after passing through L. On the other hand, on the memory card 10 side, a signal received by the first additional receiving coil 2-R, amplified by the receiving amplifier circuit 6-R and shaped, and a signal received by the second additional receiving coil 2-L and received by the receiving amplifier circuit 6-R. −
By inputting the signals amplified and shaped by L to the phase comparison circuit 23, relative phase differences are compared, and a rearrangement command signal for the bit rearrangement circuit 24 is generated. Here, the state as shown in the figure, that is, the signal of the first transmission additional coil 1-R is changed to the first reception additional coil 2-R.
When it is assumed that the signal of the second transmission additional coil 1-L is received by the second reception additional coil 2-L (the phase on the B input side with respect to the A input of the phase comparison circuit) Is delayed by 90 degrees), it is determined that the memory card 10 is normally inserted into the data supply device 9 with the front side facing up, and the rearrangement command is not issued to the bit rearrangement circuit 24. (That is, the state described in FIGS. 1 and 2 in the first embodiment is maintained).
On the contrary, when the memory card 10 is inserted with its back side facing upward, only the memory card 10 side is in a state of being inverted 180 degrees from the illustrated state with respect to the data supply device 9. That is, the first transmitting additional coil 1-R is the second receiving additional coil 2-R.
Facing the L, and the transmitting coil 1-0 is the receiving coil 2-
9 and the transmitter coil 1-1 faces the receiver coil 2-8. Similarly, the upper and lower sides in the figure are interchanged to face each other, and finally the second additional transmission coil 1-L is the first. It will face the additional coil for reception 2-R. In this state (the state in which the back side is inserted upward as described above), the phase of the A input of the phase comparison circuit 23 is delayed by 90 degrees from the phase of the B input. A bit rearrangement command is issued, and at the output of the rearrangement circuit 24, the upper and lower bits are switched in order so that the same signal arrangement as that in the normal insertion is obtained. That is, the reception data line of the reception coil 2-9 is located at a symmetrical position from the center of the reception coil array 2 and the reception coil 2-0.
Replaced with the reception data line of
8 receive data lines and receive coil 2-1 receive data lines,
A reception data line of the reception coil 2-7, a reception data line of the reception coil 2-2, a reception data line of the reception coil 2-6, a reception data line of the reception coil 2-3, and a reception data line of the reception coil 2-5. The reception data lines of the reception coil 2-4 are replaced with each other.

FIG. 6 is a block diagram showing a method of supplying power to the card at the time of data transfer adopted in this embodiment. The output signal of the transmission circuit 21 is directly applied to the first transmitting coil 1-R for determining the insertion direction, which is added to one end of the transmitting coil array 1, and the other transmitting end on the other end side is used. A signal obtained by delaying the phase of the signal of the transmitting circuit 21 by 90 degrees by the phase delay circuit 22 is applied to the second expansion coil 1-L. On the side of the memory card 10, the phase comparison circuit compares the relative phase difference between the first expansion coil 2-R for reception and the second expansion coil 2-L corresponding to the expansion coil on the transmission side (see the section in FIG. 5 described above). (However, the receiving amplifier circuits 6-R and 6-L in this case function only as simple waveform shaping circuits), and the respective signals are rectified by the rectifying diodes D31 and D32 and smoothed by the resistor R33 and the capacitor C34. Electric power is used as an external power supply (actually, it is used via a three-terminal stabilized power supply IC, but not shown), and a power supply switching circuit 36 is used to switch to the internal battery 35 and supply it to the internal circuit of the memory card 10. .

According to the second embodiment, the means for supplying electric power on the card side required for high-speed data transfer from the personal computer (data supply device) side by electromagnetic coupling (transformer) and the reverse insertion of the card. Since some of the measures can be shared, it is possible to provide a non-contact parallel transfer memory card that is small, lightweight and easy to use.

Next, a third embodiment will be described with reference to the drawings.

FIG. 7 is a block diagram of a memory card system in which a transfer coil is used for both transmission and reception, and corresponds to FIG. 1 in the first embodiment, and duplicated description will be omitted in principle. In the present embodiment, the data supply device 9 side controls the writing / reading of the memory data, and the WTREQ is transmitted to the transmission coil 1-
8 and the receiving coil 2-8, and R at the time of reading
It is executed by transmitting the EREQ to the reception control circuit 7 on the memory card side via the transmission coil 1-9 and the reception coil 2-9, respectively. The write data at the time of writing data in the memory 8 passes through the transmission control circuit 3, the α timing delay circuit 4-1 and the β timing delay circuit 4-2, and the coil drive circuit 6, and is transmitted through the transmission coil array 1 (in this embodiment, in the present embodiment). Although it is a coil for both transmission and reception, the designation in the first and second embodiments is inherited for the sake of convenience.Hereinafter, the receiving coil array 2 and the individual coils 1-0 to 1 constituting them.
The same applies to -7, 2-0 to 2-7, and for the sake of convenience, the conventional name is inherited) to the receiving coil array 2, and the predetermined address of the memory 8 is passed through the receiving amplifier circuit 6 and the receiving control circuit 7. Written in. On the other hand, in order to read the data written in the predetermined address of the memory 8, the transmission control circuit 3b and α which are added to the memory card side (means that they are added in comparison with FIG. 1 above; the same applies hereinafter). Timing delay circuit 4-1b and β timing delay circuit 4-2
Data is reversely transmitted to the data supply device 9 side by diverting the receiving coils 2-0 to 2-7 of the receiving coil array 2 to the transmitting coils via b and the coil driving circuit 5b. The reversely transmitted predetermined address data of the memory 8 is added in the same manner as the reception amplifier circuit 6a added to the data supply device 9 side by receiving the transferred data by diverting the transmission coil array 1 for reception. The memory data is read out by being transmitted to the reception control circuit 7a. In this way, the data supply device 9 side and the memory card 1
This means that both sides of the 0 side have a transmission / reception function, so that the function of reading and checking the data written in the memory immediately after writing, that is, the so-called read-after-write check can be easily realized.

FIG. 8 is a time chart when the read-after-write check function is activated. This will be described with reference to FIG. The clock supplied to the transmission control circuit (3 in FIG. 7) is a rectangular wave signal 2fC having a frequency twice the transfer frequency (20 MHz in the embodiment).
LK, a write command WTC from the host-side controller (data supply device 9 in FIG. 7) to the external memory card
Data DATA0 to DAT to be written simultaneously with OM
A7 is given. Here, the DATA0 to DA
It is assumed that TA7 is a hexadecimal representation of "FF", "0F", "F0" and "FF" at the end. A group (DATA0α, DATA2α, DATA4α,
DATA6α) and β timing group (D
ATA1β, DATA3β, DATA5β, DATA7
β) are alternately assigned, and data is set at the falling edge of each timing. Register output DATA0α, DATA2α, DATA4
The logical product of α, DATA6α and the negative signal of the α part of 2fCLK (“true” when the α part of 2fCLK is low level)
Output signal (# 0-DEVIVE,
# 2-DRIVE, # 4-DRIVE and # 6-DR
IVE) as well as the output DATA1β of the above register,
DATA3β, DATA5β, DATA7β and the above 2f
Output signals (# 1-DEVIVE, # 3-DRIVE, # 5-DRI) that are ANDed with the negative signal of the β portion of CLK.
VE and # 7-DRIVE are the individual coils (1-0 to 1- 1 in FIG. 7) of the corresponding transmitter coil array (1 in FIG. 7).
The drive current waveform for 7) is obtained. The data write operation described above is exactly the same as that of the first embodiment, except that in FIG.
In the 0-DRIVE to # 7-DRIVE waveforms, the shaded area is the reverse transmission waveform of the data read from the same address immediately after writing to the memory. That is, the 0th bit (#
0-DRIVE) first write signal "1" αW0
The read reverse transmission waveform corresponding to −0 is βR0-0, and the first “1” of the first bit (# 1-DRIVE).
The read reverse transmission waveform corresponding to the write signal βW1-0 is αR1-0. Upon receiving such reverse transmission data, the data supply device 9 compares the previous transmission data, investigates whether or not an error has occurred in the transfer system, and executes predetermined error processing.

A dedicated control line (WTREQ in FIG. 7)
By also allowing bidirectional transfer for the RDREQ and RDREQ systems, an error check is performed on the memory card side (addition of a parity bit or EDC; an error detect code is possible), and as a result, when an error occurs Can also be transferred back to the WTREQ or RDREQ line.

According to the third embodiment, not only is it possible to transfer data in both directions without increasing the number of transmission / reception coils, but also a read-after-write function and a notification function when an error occurs. Since it can be easily realized, it is possible to realize a contactless parallel transfer memory card system that is compact and lightweight and has excellent reliability when transferring data.

Next, a fourth embodiment will be described with reference to the drawings.

FIG. 9 is a block diagram showing a characteristic portion of the fourth embodiment extracted. The data supply device 9 includes a transmission coil array 1 and a front / back reverse insertion prevention pin / power supply pin 50-V,
50-G, current detection resistor 52, and card insertion signal 5
4, the output comparator 53, etc., and the other parts omitted are basically the same as those in FIG. 1 showing the first embodiment. The contactless transfer compatible memory card 10 includes a receiving coil row 2 and a card-side power receiving pin 51 of an external power source and a button-type battery 3 which are arranged on the front surface inside the reverse insertion prevention groove.
5, a power supply switching circuit 36, etc., and other parts not shown have basically the same structure as FIG. 1 showing the first embodiment. Here, when the memory card 10 is inserted into a predetermined position of the data supply device 9, a positive potential (VC
C) The power receiving pin 51-V corresponding to the supply pin 50-V and the negative potential (GND) supplying pin 50-G and the power receiving pin 51-G corresponding to each contact, respectively, and a voltage is applied to the external power source side of the power source switching circuit 36. When applied, the switching circuit 36 disconnects the built-in button-type battery 35 and uses the power supplied from the power receiving pin 51-V as the power for the card. In this way, the VC on the data supply device side
C is the power supply pins 50-V, 51-V and 51-G
When a current flows by being supplied via 50 and 50-G, a potential is generated across the detection resistor 52, the voltage comparator 53 is inverted, and the card insertion signal 54 is output.
Upon receiving the card insertion signal 54, the controller (not shown and detailed description is omitted) on the data supply device side starts data transmission / reception. Sending and receiving data is done by the transmitter coil
This is performed in a non-contact manner by generating an induced voltage due to electromagnetic coupling from the receiving coils 2-0 to 2-9 by passing a pulse current of -0 to 1-9.

10 (a) and 10 (b) are external appearance image diagrams showing the fourth embodiment.

FIG. 10A is a three-dimensional external view of the IC memory card 10. If the vertical direction in the figure is defined as the front and back sides, the power receiving pins (terminals) 51-V and 51-G are fixed to the bottom of the reverse insertion prevention groove that is carved in asymmetrical positions on the front and back sides, and the receiving coil row 2 is a thin molding material. It is covered with and is placed at the tip of the card. The power receiving pin 51 and the inside of the card 10 are physically sealed with a molding material so that air and water cannot penetrate into the inside.

FIG. 10B is a sectional view showing the concept of the state where the non-contact card 10 is inserted into the data supply device 9. The transmission coil array 1 and the reception coil array 2 approach each other with a gap of about 0.5 mm, and the relative position positioning accuracy in the XY directions is plus or minus about 0.2 mm.

FIG. 11 is a principle view showing the main cause of the occurrence of crosstalk to adjacent coils. nth transmitter coil 1
-N, the transfer signal from -n is opposite to the receiving coil 2-n and two receiving coils 2- (n-1) and 2- (n adjacent to the receiving coil 2-n.
+1) shows how electromagnetically coupled to generate an induced voltage. First, when the illustrated pulse current Id is passed through the transmission coil 1-n by the coil driving circuit 5, a magnetic flux having a density proportional to the current Id and the number of turns of the receiving coil 1-n is generated, and its main magnetic flux B81 is Although it passes back only through the receiving coils 2-n facing each other, a part of the leakage magnetic flux B'82 also passes through two adjacent receiving coils 2- (n-1) and 2- (n + 1). Return to the transmitter coil 1-n. As a result, an induced voltage proportional to the passing magnetic flux density and the number of turns is generated in the receiving coil 2-n, a pulse current Ir inversely proportional to the load resistance RL is generated, and a normal signal component is transferred. Part of leakage flux B'8
Two receiving coils 2- (n-1) and 2-
The crosstalk current Ir ′ as shown in the figure is adjacent to the two receiving coils 2- (n−) because they pass through (n + 1).
1) and 2- (n + 1).

FIG. 12 is a diagram showing a first crosstalk reducing method used in this embodiment. In this figure, for the sake of simplicity, only one transmitting coil 1-n and two adjacent receiving coils 2- (n-1) and 2- (n + 1) are extracted for convenience. It should be noted that although the principle of generation of the induced voltage to the receiving coil has been described in FIG. 11 and is omitted, the difference from FIG. 11 is that the receiving coil 2-n has auxiliary coils 2a-n and 2
b-n is provided, and the auxiliary coil 2b- (n-1) is provided to the adjacent receiving coil 2- (n-1) and the other adjacent coil 2- (n-1).
The auxiliary coil 2a- (n + 1) is also provided in (n + 1) (actually, the auxiliary coil 2a- (n-1) is provided in the adjacent receiving coil 2- (n-1), and the other adjacent coil 2- (n +) is provided.
The auxiliary coil 2b- (n + 1) is also provided in 1), but the illustration is omitted). The auxiliary coil has a leakage magnetic flux B '.
The number of turns is set such that a voltage equal to the crosstalk induced voltage to the adjacent coil generated by the action of 82 is generated by the action of the magnetic flux B81 plus the leakage magnetic flux B'82.
The adjacent coils 2- (n-1) and 2- are arranged so as to cancel the crosstalk induced voltage (to have opposite phases).
Connect to (n + 1). That is, the coil drive circuit 5
When the pulse current Id (see the waveform shown in the figure) of the transmission data is sent to the transmitting coil 1-n, a regular reception signal current Ir is generated in the opposing receiving coil 2-n (see the waveform shown in the figure), and for example, adjacent The coil 2- (n-1) operates in a direction in which the crosstalk current Ir 'induced in the coil 2- (n-1) and the induced current Ic to the auxiliary coils 2a-n cancel each other, and The current IL flowing to the load resistance of the coil 2- (n-1) becomes almost zero (see the waveform shown in the figure).

FIG. 13 shows a second crosstalk reducing method used in the fourth embodiment. First, the coil drive circuit 5-
The positive side outputs of (n-1), 5-n, and 5- (n + 1) limit the current with a resistor Rd so that a predetermined drive current is obtained, and the corresponding transmission coils 1- (n-1), 1-n, 1
-(N + 1). On the other hand, the negative side outputs of the coil drive circuits 5- (n-1), 5-n, 5- (n + 1) are connected to the respective adjacent transmission coils via the resistor Rc, for example, the coil drive circuit 5-n in the center of the drawing. If so, the negative output is the adjacent transmitter coils 1- (n-1) and 1- (n +).
1) are connected to each other via individual resistors Rc. The ratio of the resistance Rc to the resistance Rd acts on the receiving coils 2- (n-1) and 2- (n + 1) adjacent to the magnetic flux (density) B81 acting only on the regular receiving coil 2-n facing each other. Magnetic flux (density) that generates a crosstalk noise component
It is almost the same as the ratio of B'82 (more accurately expressed, the ratio of B + B 'and B'is taken as a reference and the total magnetic transfer loss is taken into consideration), and it is adjacent via the resistance Rc. The transmitter coils 1- (n-1) and 1- (n
Magnetic flux Bc generated by the pulse current flowing in +1)
Since 83 is generated in the opposite direction with the same density as the leakage magnetic flux B'82, almost no magnetic flux acts on the receiving coils 2- (n-1) and 2- (n + 1) adjacent to the regular receiving coil. Since it becomes zero, the crosstalk noise component current Ir ′ is not generated either.

According to the fourth embodiment, it is possible to realize a transfer rate about twice as high as that of the crosstalk countermeasure by the phase shift method (the first to third embodiments) (in the present embodiment, the maximum transfer rate can be realized). It has the effect of confirming 20 megabytes per second).

Finally, a specific application example of the contactless parallel transfer IC memory card will be described with reference to FIGS. 14 and 15.

FIG. 14 is an external view of an IC player 10 'to which a non-contact parallel transfer IC memory card is applied. With the power switch 61 in the ON position, the acoustic information converted into compressed code information is written from the receiving coil array 2 into the internal memory at a high transfer rate (10 megabytes per second), and then <P
By operating the LAY> switch 66, the earphone 70 is placed on the ear to listen to the acoustic information recorded in the memory that is sequentially reproduced. When a plurality of pieces of music information and the like are recorded in the memory, the <+> switch 62 and the <-> switch 63 for selection are operated to operate the liquid crystal display panel 69.
After confirming the song name and song number with, play by operating the <PLAY> switch 66, and for fast listening, <FF> switch 64,
<REW> switch 67 for fast reverse, <PAU for pause
The SE operation is performed by operating the SE> switch 6565, and the reproduction operation is completed by operating the <STOP> switch 66.

FIG. 15 is a block diagram showing the internal circuit configuration of an IC player 10 'to which the non-contact parallel transfer IC memory card is applied. The compressed acoustic code information is input from the receiving coil array 2 and recorded in the IC memory 8 via the transfer control circuit 71 and the microprocessor 72. While checking on the liquid crystal display panel 69, various switches 61, 62,
When the reproduction operation is executed by the operations of 63 to 68, the compressed acoustic code information stored in the memory 8 is expanded by the microprocessor 72 and returned to an analog signal by the DA converter 73 and passed through the low pass filter which also serves as an amplifier circuit. And output. As for the power supply during normal operation, the built-in button type battery 35 is selected by the power supply switching circuit 36, but when it is set to absorb information from the data supply device (information server), the front and back of the card (up and down) Power receiving electrode pin (terminal) 51-provided in the reverse insertion prevention groove portion
Power is supplied via V, 51-G, and the power switching circuit 36 disconnects the built-in button type battery 35 to use the power of an external weapon.

According to the present embodiment, the I information having the instant dubbing function capable of recording about 70 minutes of voice information in about 3 seconds in the memory of 32 megabytes and having excellent environmental resistance such as waterproofness.
There is an effect that a C recorder can be easily realized.

[0075]

According to the present invention, in the non-contact parallel transfer system using a plurality of electromagnetic coupling coils, the size of the transfer coil and the coil gap are reduced in inverse proportion to the increase in the number of parallel transfer bits. However, since it is possible to completely prevent malfunctions due to crosstalk between coils, which was the biggest bottleneck, it is possible to provide a compact, high-density, electromagnetically coupled contactless parallel transfer card system capable of high-speed transfer with high reliability. There is an effect.

Further, since the instantaneous peak currents due to the parallel simultaneous transfer are leveled, the load on the power supply circuit system is reduced, and the noise energy due to the pulsed current is also reduced. This has the effect of realizing a highly reliable system.

Further, since the power supply coil at the time of data transfer and the inside-out insertion detecting means of the memory card can be shared,
There is an effect that a compact and easy-to-use electromagnetic coupling type contactless parallel transfer card system can be supplied with high reliability.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a data supply device and a non-contact parallel transfer memory card according to a first embodiment.

FIG. 2 is a logical expansion diagram showing an input unit of a contactless parallel transfer memory card.

FIG. 3 is a time chart diagram for explaining a part of the first embodiment.

FIG. 4 is an external view when a memory card is inserted into the data supply device.

FIG. 5 is a configuration block diagram of a data supply device and a non-contact parallel transfer memory card according to a second embodiment.

FIG. 6 is a block diagram showing an example of external power supply during data transfer.

FIG. 7 is a configuration block diagram of a data supply device and a contactless parallel transfer memory card according to a third embodiment.

FIG. 8 is a time chart diagram for explaining a part of the third embodiment.

FIG. 9 is a block diagram showing a fourth embodiment.

FIG. 10 is an external image diagram showing a fourth embodiment.

FIG. 11 is a principle block diagram showing a crosstalk noise generation mechanism.

FIG. 12 is a block diagram showing a first method for reducing crosstalk noise used in a fourth embodiment.

FIG. 13 is a block diagram showing a second method for reducing crosstalk noise used in the fourth embodiment.

FIG. 14 is an external view of an IC player which is a specific application example of a contactless parallel transfer card.

FIG. 15 is a block diagram showing a circuit configuration of an IC player which is a specific application example of a contactless parallel transfer card.

16A and 16B are a circuit diagram of a crosstalk experiment of the electromagnetic coupling transfer coil and a diagram showing experimental data thereof.

FIG. 17 is a diagram showing an appearance of a PCMCIA standard memory card and a mounting state of a non-contact coil array.

FIG. 18 is an external view of a practical coil array used in an example.

[Explanation of symbols]

1 ... Transmission coil array, 2 ... Reception coil array, 3 ... Transmission control circuit 4 ... Timing delay circuit, 5 ... Coil drive circuit, 6 ... Reception amplifier circuit 7 ... Reception control circuit, 8 ... IC memory, 9 ... Data Supply device (personal computer) 10 ... Non-contact parallel transfer memory card, 21 ... Oscillation circuit,
22 ... Phase delay circuit 23 ... Phase comparison circuit, 24 ... Bit rearrangement circuit, 35
Button battery 36 Power supply switching circuit 41 Gate timing signal generating circuit 42 Gate circuit 43 Data set reset flip-flop 44 Data set α gate signal (α timing signal acceptance period setting pulse) 45 Gate signal (Β timing signal acceptance period setting pulse)

Front page continuation (72) Inventor Kazunari Nakagawa 1-88, Torora, Ibaraki-shi, Osaka, Hitachi Maxell Co., Ltd. (72) Inventor Nobuo Hamamoto 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central (72) Inventor Takehiro Okawa 1-280, Higashi Koikeku, Kokubunji, Tokyo 1-280, Hitachi, Ltd. Central Research Laboratory (72) Inventor, Yutaka Kibuchi 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Center, Ltd.

Claims (23)

[Claims] 1. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer device having non-contact holding means for holding in proximity to each other, at least in the data server, which generates data for parallel transfer between the first coil group and the second coil group as a parallel pulse. A parallel pulse generating means having a delay means provided in the first parallel pulse group and a second parallel pulse generating means for delaying the parallel pulse by at least a first bit number; And a second parallel pulse group consisting of a number of bits, and the parallel transfer timing of the second parallel pulse group is at least smaller than the parallel transfer timing of the first parallel pulse group and is longer than the pulse width of each bit. A noise reduction contactless parallel data transfer device comprising means for delaying. 2. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. A contactless parallel data transfer device having contactless holding means for holding in proximity, wherein the portable memory device is a memory card having an IC memory built-in. 3. A portable memory device provided with a first coil group for parallel transfer provided for transmitting / receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer device having non-contact holding means for holding in close proximity to each other, at least the first and second parallel pulse groups are distributed so that adjacent coils have different timings. Noise reduction contactless parallel data transfer device. 4. A portable memory device provided with a first coil group for parallel transfer, which is provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer apparatus having non-contact holding means for holding the gates in close proximity, a gate for selecting a reception timing corresponding to each pulse group similar to the pulse group for receiving the first and second parallel pulse groups. A noise reduction contactless parallel data transfer device comprising means. 5. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer device having a non-contact holding means for holding in close proximity, at least the data server for generating data for parallel transfer between the first coil group and the second coil group as a parallel pulse. A parallel pulse generating means provided inside the first and second coil groups, and a cross generated in the receiving side coil adjacent to the first coil pair of the coil pairs facing each other. The first to counteract the over-click component
A non-contact noise reduction parallel data transfer apparatus comprising means for supplying a part of the transfer signal from at least one of the coil pairs to the adjacent receiving side coil with its phase inverted. 6. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer device having non-contact holding means for holding in proximity to each other, the means for inverting and providing the phase is adjacent to at least the receiving side coil of the first coil pair.
A noise-reducing non-contact parallel data transfer device, characterized in that it is means for supplying a canceling current of opposite phase to one receiving coil. 7. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer device having non-contact holding means for holding in proximity to each other, the means for inverting and providing the phase is adjacent to at least the transmitting side coil of the first coil pair.
A noise-reducing non-contact parallel data transfer device, characterized in that it is means for supplying a canceling current of opposite phase to two transmitting side coils. 8. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact parallel data transfer device having non-contact holding means for holding in close proximity, the portable memory device includes means for bidirectionally transferring parallel data between the first coil group and the second coil group. A noise-reducing non-contact parallel data transfer device having. 9. The noise reducing contactless parallel data transfer apparatus according to claim 2, wherein the data server and the memory card have contact terminals for supplying power and ground potential from the data server to the memory card. A noise-reduction non-contact parallel data transfer device characterized by the above. 10. The noise reducing contactless parallel data transfer device according to claim 2, wherein an electrode terminal for receiving a power source and a ground potential is provided in a recessed structure portion for preventing vertical reverse insertion provided on a side surface portion of the memory card. A noise-reducing non-contact parallel data transfer device comprising: 11. The noise reduction contactless parallel data transfer device according to claim 2, wherein it is detected whether or not a current of a power supply supplied from the data server to the memory card exceeds a predetermined constant current. A noise reducing contactless parallel data transfer device comprising means for detecting that a card has been inserted into the data server. 12. A data server provided with a second coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like.
A first coil group composed of a plurality of unit coils provided so as to face each of the plurality of unit coils forming the second coil group, and the first coil group and the second coil group are close to each other. And at least one of the means for generating the data as parallel data and the parallel data when the data are transferred in parallel in parallel.
In an IC memory card having a built-in C memory, the parallel pulse is divided into at least a first parallel pulse group having a first bit number and a second parallel pulse group having a second bit number, and the first parallel pulse group is divided into at least the first parallel pulse group. An IC memory card comprising means for delaying the parallel transfer timing of the second parallel pulse group by a time longer than the parallel transfer timing of the parallel pulse group by at least a time longer than the pulse width of each bit. 13. A data server provided with a second coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like.
A first coil group composed of a plurality of unit coils provided so as to face each of the plurality of unit coils forming the second coil group, and the first coil group and the second coil group are close to each other. And at least one of the means for generating the data as parallel data and the parallel data when the data are transferred in parallel in parallel.
In an IC memory card with a built-in C memory, a crosstalk component generated in a reception side coil adjacent to the first coil pair of the corresponding unit coil pairs of the first and second coil groups is generated. An IC memory card, comprising means for supplying a part of the transfer signal of the first unit coil pair to the adjacent unit coils of the first coil group in an opposite phase for canceling. 14. A data server provided with a second coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like.
A first coil group composed of a plurality of unit coils provided so as to face each of a plurality of unit coils forming the second coil group, and the first coil group and the second coil group are close to each other. And at least one of the means for generating the data as parallel data and the means for receiving the data as parallel data when the data are parallelly transferred in opposition to each other, and the parallel pulse has a first bit number. 1 parallel pulse group and at least a second parallel pulse group having a second number of bits, and the parallel transfer timing of the second parallel pulse group is less than the parallel transfer timing of the first parallel pulse group. And an IC memory card having a built-in IC memory having means for delaying a time longer than the pulse width of each bit, in order to make the first and second coil groups closely face each other, the data The first and second coil groups are symmetrically distributed and arranged in a direction orthogonal to the center line of the IC memory card with respect to the insertion surface of the IC memory card into which the IC memory card is inserted. The phases provided at both ends of the first and second coil groups are relatively 9
An IC memory card, which is provided with a unit coil pair for transferring with a shift of 0 degree. 15. A unit coil on the side of the memory card provided at both ends of the first coil group receives the signals 90 degrees out of phase with each other and receives the first signal based on the received signals.
15. The IC memory card according to claim 14, further comprising means for changing the arrangement order of the parallel pulses of the coil group. 16. The unit coils on the memory card side provided at both ends of the first coil group receive the signals whose phases are relatively shifted by 90 degrees, and receive the received signals from an external power source of the memory card. 15. The IC memory card according to claim 14, further comprising means used as. 17. A data server provided with a second coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like.
A first coil group composed of a plurality of unit coils provided so as to face each of the plurality of unit coils forming the second coil group, and the first coil group and the second coil group are close to each other. And at least one of the means for generating the data as parallel data and the means for receiving the data as parallel data when the data are parallelly transferred in opposition to each other;
And for canceling the crosstalk component generated in the receiving side coil adjacent to the first coil pair of the corresponding unit coil pairs of the second coil group.
And a means for supplying a part of the transfer signal of the unit coil pair to the adjacent unit coils of the first coil group in antiphase.
The first and second coil groups are arranged in the direction perpendicular to the center line of the IC memory card with respect to the insertion surface of the data server in which the IC memory card is inserted in order to make the coil groups closely face each other. An IC characterized in that unit coil pairs for symmetrical transfer are provided at both ends of the arranged first and second coil groups and the phases thereof are relatively shifted by 90 degrees. Memory card. 18. The unit coils on the side of the memory card provided at both ends of the first coil group receive the signals whose phases are relatively shifted by 90 degrees and the first coils are received based on the received signals.
18. The IC memory card according to claim 17, further comprising means for changing the arrangement order of the parallel pulses of the coil group. 19. The unit coils on the memory card side provided at both ends of the first coil group receive the signals whose phases are relatively shifted by 90 degrees, and receive the received signals from an external power supply of the memory card. 18. The IC memory card according to claim 17, further comprising means used as 20. A portable memory device provided with a first coil group for parallel transfer provided for transmitting and receiving address information, a write control signal, a data string to be written, and the like, and a portable memory device facing the first coil group. A data server having a second coil group provided so as to supply data to at least the portable memory device, and transferring data between the first coil group and the second coil group. In a non-contact data transfer method of a non-contact parallel data transfer device having a non-contact holding means for holding in proximity to each other, the first coil group and the second coil group are opposed to each other in order to transfer data in parallel. Data that is held in close proximity and is transferred in parallel between the first and second coil groups is generated as a parallel pulse, and at least a parallel pulse is generated in the data server, Even less parallel pulse generated first
Is divided into a first parallel pulse group consisting of the number of bits and a second parallel pulse group consisting of the second number of bits, and the second parallel pulse group is divided into the second parallel pulse group from the parallel transfer timing of the divided first parallel pulse group. Non-contact data of a non-contact parallel data transfer device, characterized in that the parallel transfer timing of the parallel pulse group is delayed by at least a time longer than the pulse width of each bit forming the first and second parallel pulse groups. Transfer method. 21. The portable memory device is an IC memory card having a built-in IC memory, and data is written to and read from the memory card.
The contactless data transfer method of the contactless parallel data transfer device according to 0. 22. The non-contact parallel data transfer apparatus according to claim 20, wherein the first and second parallel pulse groups are distributed so that at least mutually adjacent unit coils have different timings. Contactless data transfer method. 23. The non-contact parallel data transfer according to claim 20, wherein the receiving timing is selected for each unit receiving coil with respect to the coil group receiving the first and second parallel pulse groups. Contactless data transfer method of device.