JPH0828561B2 - Manufacturing method of printed wiring board - Google Patents

Manufacturing method of printed wiring board

Info

Publication number
JPH0828561B2
JPH0828561B2 JP3078132A JP7813291A JPH0828561B2 JP H0828561 B2 JPH0828561 B2 JP H0828561B2 JP 3078132 A JP3078132 A JP 3078132A JP 7813291 A JP7813291 A JP 7813291A JP H0828561 B2 JPH0828561 B2 JP H0828561B2
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
palladium plating
plating
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3078132A
Other languages
Japanese (ja)
Other versions
JPH04236485A (en
Inventor
正記 芳賀
衛 内田
秀美 縄舟
省三 水本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ishihara Chemical Co Ltd
Original Assignee
Ishihara Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ishihara Chemical Co Ltd filed Critical Ishihara Chemical Co Ltd
Priority to JP3078132A priority Critical patent/JPH0828561B2/en
Priority to DE19924201129 priority patent/DE4201129A1/en
Publication of JPH04236485A publication Critical patent/JPH04236485A/en
Publication of JPH0828561B2 publication Critical patent/JPH0828561B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31Coating with metals
    • C23C18/42Coating with noble metals
    • C23C18/44Coating with noble metals using reducing agents
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/50Electroplating: Baths therefor from solutions of platinum group metals
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/062Etching masks consisting of metals or alloys or metallic inorganic compounds
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/072Electroless plating, e.g. finish plating or initial plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrochemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント配線板の製造
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board.

【0002】[0002]

【従来の技術及びその課題】最近、表面実装の普及によ
って、プリント配線板両面への部品実装が可能となり、
高密度実装用のプリント配線板が広く実用化されてい
る。
2. Description of the Related Art Recently, with the spread of surface mounting, parts can be mounted on both sides of a printed wiring board.
Printed wiring boards for high-density mounting have been widely put into practical use.

【0003】このような両面表面実装方式のプリント配
線板では、種々の部品装着方法が採用されており、例え
ば、プリント配線板の表面に、チップ部品をリフローに
よりはんだ付けした後、裏面にも同じようにチップ部品
をリフローによりはんだ付けをし、その後、端子用リー
ド線をもった電子部品をリフロー法によりはんだ付けす
る方法、プリント配線板の表面にチップ部品をリフロー
によりはんだ付けし、裏面にはチップ部品を接着剤で仮
止めし、挿入部品と一緒にフローソルダリングする方法
などが採用されている。これらの方法では、プリント配
線板は、はんだ付けや接着剤の硬化のために複数回の熱
処理が行なわれており、この加熱によりプリント配線板
の導体回路を形成する銅が酸化され、はんだにより電子
部品を接続する際の接続不良の原因となっている。
In such a double-sided surface mounting type printed wiring board, various component mounting methods are adopted. For example, after soldering a chip component to the front surface of the printed wiring board by reflow, the same is applied to the back surface. As described above, solder the chip parts by reflow, then solder the electronic parts with lead wires for terminals by the reflow method, solder the chip parts on the front surface of the printed wiring board by reflow, and on the back surface A method of temporarily fixing the chip parts with an adhesive and performing flow soldering together with the insertion parts is adopted. In these methods, the printed wiring board is subjected to multiple heat treatments for soldering and curing of the adhesive, and this heating oxidizes the copper forming the conductor circuit of the printed wiring board, and the solder causes electronic It is a cause of connection failure when connecting parts.

【0004】この様な弊害を防止するために、例えば、
プリフラックス処理とよばれるプリント配線板の表面処
理が行なわれている。この方法は、プリント配線板の製
造後、ロジン材料等からなるプリフラックスを銅表面保
護膜として塗布して、銅回路部分の防錆効果を図る方法
である。しかしながら、プリフラックスは、リフローは
んだ付け等により複数回熱処理を行なう場合に、熱的履
歴を経ることによって保護膜としての機能が損なわれ、
はんだ付け性の劣化、はんだ付け後の洗浄性の劣化など
を生じるという欠点がある。
In order to prevent such an adverse effect, for example,
A surface treatment of a printed wiring board called pre-flux treatment is performed. This method is a method of applying a pre-flux made of a rosin material or the like as a copper surface protective film after the production of a printed wiring board to achieve a rust preventive effect on a copper circuit portion. However, the preflux loses its function as a protective film due to a thermal history when heat treatment is performed multiple times by reflow soldering or the like.
There is a drawback that the solderability deteriorates and the cleaning property after soldering deteriorates.

【0005】また、プリント配線板の銅回路部分に溶融
はんだにより防錆皮膜を形成するソルダーコート処理法
も採用されている。しかしながら、この方法では、はん
だ膜厚のばらつきが大きいために、表面実装部品の装着
安定性が悪く、また、パッドのピッチが狭い場合には、
はんだ過剰となり、はんだブリッジを生じ易いという欠
点がある。更に、プリント配線板の反り、ねじれが大き
く、表面実装部品の自動装着がしにくく、またはんだに
より穴づまりが起こり易く、部品挿入がしにくいという
欠点もある。
Further, a solder coat treatment method for forming an anticorrosive film on a copper circuit portion of a printed wiring board by molten solder is also adopted. However, in this method, the mounting stability of the surface mount component is poor due to the large variation in the solder film thickness, and when the pad pitch is narrow,
There is a drawback that solder becomes excessive and solder bridges are easily generated. Further, there is a drawback that the printed wiring board is largely warped and twisted, so that it is difficult to automatically mount surface mount components, or holes are apt to be clogged due to sticking, and it is difficult to insert the components.

【0006】[0006]

【課題を解決するための手段】本発明者は、上記した如
き従来技術の課題に鑑みて、特に両面実装プリント配線
板に適用するために最適な銅回路保護方法を見出すべ
く、鋭意研究を重ねてきた。その結果、はんだ付けによ
り部品を装着すべき銅金属上に、パラジウムめっき皮膜
を形成したプリント配線板は、熱的履歴を経ることによ
るはんだ付け性の低下が非常に少なく、また、保護皮膜
の膜厚の均一性が優れていることにより、表面実装部品
の装着安定性が良好であり、更にはんだブリッジが生じ
ることもなく、特に高密度実装をするためのプリント配
線板として、有用性が高いものであり、無電解めっき方
法を利用した特定の処理方法により、両面実装プリント
配線板に対しても簡単にパラジウムによる保護皮膜を形
成できることを見出し、ここに本発明を完成するに至っ
た。
In view of the problems of the prior art as described above, the present inventor has conducted earnest research to find an optimum copper circuit protection method particularly for application to a double-sided mounting printed wiring board. Came. As a result, a printed wiring board with a palladium plating film formed on a copper metal on which components should be mounted by soldering has very little deterioration in solderability due to thermal history, and a protective film Highly uniform thickness ensures good mounting stability of surface-mounted components and does not cause solder bridges. It is particularly useful as a printed wiring board for high-density mounting. Therefore, it has been found that a protective film of palladium can be easily formed even on a double-sided printed wiring board by a specific treatment method using an electroless plating method, and the present invention has been completed here.

【0007】即ち、本発明は、銅金属による導体回路及
びその上に形成したソルダーレジストパターンを有する
プリント配線板の銅金属上に、無電解パラジウムめっき
液を用いて、厚さ0.01μm〜0.2μmのパラジウ
ムめっき皮膜を形成することを特徴とするプリント配線
板の製造法に係る。
That is, the present invention uses an electroless palladium plating solution on a copper metal of a printed wiring board having a conductor circuit made of copper metal and a solder resist pattern formed on the conductor circuit, and has a thickness of 0.01 μm to 0 μm. The present invention relates to a method for producing a printed wiring board, which comprises forming a palladium plating film having a thickness of 2 μm.

【0008】本発明方法によって得られるプリント配線
板は、銅金属による導体回路を有するプリント配線板に
おいて、少なくともはんだ付けにより部品装着すべき銅
金属上に、パラジウムめっき皮膜を形成したものであ
る。本発明における、このようなプリント配線板の製造
方法は、以下の通りである。
The printed wiring board obtained by the method of the present invention is a printed wiring board having a conductor circuit made of copper metal, in which a palladium plating film is formed on at least copper metal to be mounted with components by soldering. The method for manufacturing such a printed wiring board in the present invention is as follows.

【0009】本発明方法において、適用できるプリント
配線板の種類は、銅金属を導体回路とするものであれば
特に限定はなく、基材材料としては、公知の各種材料の
基板、例えばガラスエポキシ基板、紙フェノール基板、
紙エポキシ基板等をいずれも採用できる。プリント配線
板の導体回路形成方法についても限定はなく、公知の各
種方法、例えば、パネルめっき法、パターンめっき法、
セミアディティブ法、フルアディティブ法、パートリー
アディティブ法等のいずれの方法により回路を形成した
ものも使用できる。また、プリント配線板の部品装着方
法についても、特に限定はなく、片面基板、両面基板、
多層基板等のいずれの装着方法の基板にも適用できる
が、特に、両面表面実装基板等の複数回はんだ付けを行
なう基板に最適である。
In the method of the present invention, the type of the printed wiring board that can be applied is not particularly limited as long as it is a conductor circuit made of copper metal, and the base material is a substrate of various known materials, for example, a glass epoxy substrate. , Paper phenolic board,
Any paper epoxy board or the like can be adopted. There is also no limitation on the method for forming a conductor circuit on a printed wiring board, and various known methods such as panel plating, pattern plating,
A circuit formed by any of the semi-additive method, the full-additive method, the part-additive method and the like can be used. Also, there is no particular limitation on the method of mounting the components on the printed wiring board, and a single-sided board, a double-sided board,
The present invention can be applied to boards of any mounting method such as a multilayer board, but is particularly suitable for a board such as a double-sided surface mounting board that is soldered a plurality of times.

【0010】本発明で用いる無電解パラジウムめっき液
の種類については、特に限定はなく、公知の無電解パラ
ジウムめっき液をいずれも使用できる。無電解パラジウ
ムめっき液の具体例としては、特開昭62−12428
0号公報に示された、a)パラジウム化合物、b)アン
モニア及びアミン化合物の少なくとも1種、c)二価の
硫黄を含有する有機化合物、並びにd)次亜リン酸化合
物及び水素化ホウ素化合物の少なくとも1種、を含有す
る水溶液からなる無電解パラジウムめっき液、特開平1
−268877号公報に記載されたa)パラジウム化合
物、b)アンモニア及びアミン化合物の少なくとも1
種、c)二価の硫黄を含有する有機化合物、並びにd)
亜リン酸及びその塩類の少なくとも1種、を含む水溶液
からなる無電解パラジウムめっき液、などを挙げること
ができる。
The type of electroless palladium plating solution used in the present invention is not particularly limited, and any known electroless palladium plating solution can be used. A specific example of the electroless palladium plating solution is disclosed in JP-A-62-142828.
No. 0, a) a palladium compound, b) at least one of ammonia and an amine compound, c) an organic compound containing divalent sulfur, and d) a hypophosphorous acid compound and a borohydride compound. Electroless palladium plating solution comprising an aqueous solution containing at least one kind,
At least one of a) a palladium compound, b) ammonia and an amine compound described in JP-A-268877.
Seed, c) an organic compound containing divalent sulfur, and d)
Examples thereof include an electroless palladium plating solution formed of an aqueous solution containing phosphorous acid and at least one of salts thereof.

【0011】無電解パラジウムめっきの条件は、使用す
るめっき液の種類に応じて、通常のめっき条件と同様と
すればよい。
The electroless palladium plating conditions may be the same as the usual plating conditions depending on the type of plating solution used.

【0012】銅金属上に形成するパラジウム皮膜の厚さ
は、0.01μm〜0.2μmとする。本発明では、無
電解パラジウムめっき液を用いてパラジウム皮膜を形成
することによって、この様な非常に薄い膜厚の場合に
も、銅回路を有効に保護することができる。パラジウム
皮膜の膜厚が0.01μmを下回ると、熱処理後のはん
だ付け性が低下するので、複数回はんだ付けを行う場合
には好ましくない。
The thickness of the palladium film formed on the copper metal is 0.01 μm to 0.2 μm . In the present invention,
Form a palladium film using electrolytic palladium plating solution
In case of such a very thin film thickness,
Can also effectively protect copper circuits. When the thickness of the palladium film is below 0.01 [mu] m, since solderability after heat treatment is decreased, have Na preferably when performing multiple soldering.

【0013】本発明方法において、プリント配線板にお
ける無電解パラジウムめっき皮膜を形成すべき部分は、
銅金属による導体回路のうちで、少なくともはんだ付け
すべき銅金属の部分であり、具体的には、表面実装の場
合にはパット部分、スルーホールを有する基板では、ラ
ンド部分及びスルーホール部分である。従って、本発明
では、銅金属による導体回路を形成した配線板に、ソル
ダーレジストパターンを形成し、露出した銅金属部分に
のみ無電解パラジウムめっきを行なう。この場合、通
常、常法に従ってソフトエッチングを行なって銅の酸化
物層を除去した後、無電解パラジウムめっきを行なうこ
とが好ましい。ソフトエッチングは、公知の各条件に従
えば良く、例えば、過硫酸アンモニウム150g/l程
度の水溶液に30℃程度で60秒間程度浸漬する方法、
過硫酸ソーダ150g/l程度の水溶液に30℃程度で
60秒間程度浸漬する方法、硫酸11重量%及び過酸化
水素3.8重量%を含有する水溶液に、20℃程度で6
0秒間程度浸漬する方法などを採用できる。また、後の
工程で、端子部分、ボンディングパット部分等に、金め
っき、ロジウムめっき等の貴金属めっきを行なう場合に
は、これらの部分には、めっきレジスト層を形成した
後、無電解パラジウムめっきを行なってもよい。
In the method of the present invention, the portion of the printed wiring board where the electroless palladium plating film is to be formed is
Of the conductor circuit made of copper metal, it is at least the copper metal portion to be soldered. Specifically, in the case of surface mounting, it is the pad portion, and in the case of a board having through holes, the land portion and the through hole portion. . Therefore, in the present invention, a solder resist pattern is formed on a wiring board having a conductor circuit made of copper metal, and electroless palladium plating is performed only on the exposed copper metal portion. In this case, it is usually preferable to perform soft etching according to a conventional method to remove the copper oxide layer and then perform electroless palladium plating. The soft etching may be performed according to known conditions, for example, a method of immersing in an aqueous solution of about 150 g / l of ammonium persulfate at about 30 ° C. for about 60 seconds,
A method of immersing in an aqueous solution of about 150 g / l of sodium persulfate at about 30 ° C. for about 60 seconds, and an aqueous solution containing 11% by weight of sulfuric acid and 3.8% by weight of hydrogen peroxide at about 20 ° C.
A method of soaking for about 0 seconds can be adopted. Further, in a later step, when a noble metal plating such as gold plating or rhodium plating is performed on the terminal portion, the bonding pad portion, etc., after forming a plating resist layer on these portions, electroless palladium plating is performed. You may do it.

【0014】無電解パラジウムめっきは、前記した様な
めっき液を用いて、銅金属上に、直接行なうことが可能
であるが、銅又は銅合金を選択的に活性化させる触媒液
を用いて、銅金属に触媒を付与した後、無電解パラジウ
ムめっきを行なうことが好ましく、これにより、パラジ
ウムめっきの初期析出までの時間を著るしく短縮するこ
とができる。この様な触媒液としては、公知のものをい
ずれも用いることができ、例えばICPアクセラ(商
標:奥野製薬工業(株)製)等を例示できる。
The electroless palladium plating can be carried out directly on the copper metal using the above-mentioned plating solution, but using a catalyst solution for selectively activating copper or copper alloy, After applying the catalyst to the copper metal, electroless palladium plating is preferably carried out, whereby the time until the initial deposition of palladium plating can be significantly shortened. As such a catalyst liquid, any known liquid can be used, and examples thereof include ICP Axela (trademark: manufactured by Okuno Chemical Industries Co., Ltd.).

【0015】また、本発明方法では、必要に応じて、銅
金属とパラジウムめっき皮膜の間に無電解めっき法によ
り、他のめっき皮膜、例えばNiめっき皮膜等を形成し
てもよい。
In the method of the present invention, another plating film, such as a Ni plating film, may be formed between the copper metal and the palladium plating film by an electroless plating method, if necessary.

【0016】以上示した方法によって、銅金属による導
体回路を有するプリント配線板において、少なくともは
んだ付けにより部品装着をすべき銅金属上にパラジウム
めっき皮膜を有するプリント配線板を得ることができ
る。本発明により得られるプリント配線板は、必要に応
じて、パラジウムめっき皮膜の形成前又は後の適当な時
期に、常法に従って、端子部分、ボンディングパット部
分等に、金めっき、ロジウムめっき等の貴金属めっきを
行なうことができる。この場合には、通常、ニッケルめ
っき等を下地めっきとするが、パラジウム皮膜上に直接
貴金属めっきを行なうこともできる。また、パラジウム
皮膜を剥離した後、ニッケルめっき及び貴金属めっきを
行なってもよい。また、文字印刷、外形加工等も常法に
従って行なえばよい。
By the method described above, it is possible to obtain a printed wiring board having a conductor circuit made of copper metal and having a palladium plating film on the copper metal on which components are to be mounted at least by soldering. The printed wiring board obtained by the present invention, if necessary, at an appropriate time before or after the formation of the palladium plating film, according to a conventional method, the terminal portion, the bonding pad portion, etc., gold plating, rhodium plating or other precious metal Plating can be performed. In this case, nickel plating or the like is usually used as the base plating, but the palladium coating may be directly plated with a noble metal. Further, after the palladium film is peeled off, nickel plating and noble metal plating may be performed. Further, character printing, outer shape processing, etc. may be performed according to a conventional method.

【0017】本発明により得られるプリント配線板に部
品を装着するためには、通常の部品装着法をいずれも採
用でき、例えば、ディスクリート部品の挿入実装による
片面実装、表面はディスクリート部品の挿入実装、裏面
はチップ部品の表面実装による両面実装、表面はディス
クリート部品の挿入実装とチップ部品の表面実装、裏面
はチップ部品の表面実装による両面実装、両面にチップ
部品を表面実装する両面実装、等の各種の方法を採用で
き、これらは公知の方法に従って行なえばよい。
In order to mount components on the printed wiring board obtained by the present invention, any ordinary component mounting method can be adopted. For example, single-sided mounting by discrete mounting of discrete components, insertion mounting of discrete components on the surface, Various types such as double-sided mounting by surface mounting of chip parts on the back side, surface mounting of discrete parts and surface mounting of chip parts on the front side, double-sided mounting by surface mounting of chip parts, double-sided mounting by surface mounting chip parts on both sides Method can be adopted, and these may be performed according to known methods.

【0018】[0018]

【発明の効果】本発明により得られるプリント配線板
は、パラジウムめっき皮膜による銅回路の保護皮膜を有
するものであり、部品装着時にはんだ付け等によって複
数回加熱される場合にも、銅回路を有効に保護し、はん
だ付け性の劣化、はんだ付け後の洗浄性の低下などを生
じることがない。また、パラジウムめっき皮膜の膜厚の
ばらつきが小さいために、表面実装部品の装着安定性が
良く、また、スルーホールの穴づまりの発生や回路の短
絡が生じることもない。
The printed wiring board obtained by the present invention has a protective film for a copper circuit by a palladium plating film, and the copper circuit is effective even when it is heated a plurality of times by soldering etc. when mounting components. Protects against soldering and does not cause deterioration of solderability or deterioration of cleaning performance after soldering. Further, since the variation in the film thickness of the palladium plating film is small, the mounting stability of the surface mount component is good, and there is no occurrence of clogging of through holes or short circuit of the circuit.

【0019】本発明方法により得られるプリント配線板
は上記した様な優れた特徴を有するものであり、特に部
品装着時にはんだ付け、接着剤硬化などにより複数回熱
処理を行なう高密度実装用プリント配線板において、銅
金属の酸化によるはんだ付け性の低下を有効に防止でき
る点において非常に有用性が高い。
The printed wiring board obtained by the method of the present invention has the excellent characteristics as described above, and in particular, the printed wiring board for high-density mounting, in which heat treatment is carried out a plurality of times by soldering, curing of an adhesive, etc. when mounting components. On the other hand, it is very useful in that it is possible to effectively prevent deterioration of solderability due to oxidation of copper metal.

【0020】[0020]

【実施例】以下、実施例を挙げて本発明を更に詳細に説
明する。実施例において用いたパラジウムめっき液及び
めっき条件は以下の通りである。
EXAMPLES Hereinafter, the present invention will be described in more detail with reference to examples. The palladium plating solution and plating conditions used in the examples are as follows.

【0021】 ○無電解パラジウムめっき液 塩化パラジウム 0.01モル/l エチレンジアミン 0.08モル/l チオジグリコール酸 20mg/l 次亜リン酸ソーダ 0.06モル/l pH 8 液温 60℃ ○無電解パラジウムめっき液 塩化パラジウム 0.01モル/l エチレンジアミン 0.08モル/l チオジグリコール酸 20mg/l ジメチルアミンボラン 0.06モル/l pH 8 液温 60℃ ○無電解パラジウムめっき液 塩化パラジウム 0.01モル/l エチレンジアミン 0.08モル/l チオジグリコール酸 30mg/l 亜リン酸ソーダ 0.02モル/l pH 6 液温 60℃○ Electroless palladium plating solution Palladium chloride 0.01 mol / l Ethylenediamine 0.08 mol / l Thiodiglycolic acid 20 mg / l Sodium hypophosphite 0.06 mol / l pH 8 Liquid temperature 60 ° C. ○ None Electrolytic palladium plating solution Palladium chloride 0.01 mol / l Ethylenediamine 0.08 mol / l Thiodiglycolic acid 20 mg / l Dimethylamine borane 0.06 mol / l pH 8 Solution temperature 60 ° C. Electroless palladium plating solution Palladium chloride 0 0.01 mol / l ethylenediamine 0.08 mol / l thiodiglycolic acid 30 mg / l sodium phosphite 0.02 mol / l pH 6 liquid temperature 60 ° C.

【0022】[0022]

【実施例1】以下の方法で、銅板上にパラジウムめっき
皮膜を形成した試料について、加熱処理によるはんだ付
け性の変化を調べた。
[Example 1] With respect to a sample in which a palladium plating film was formed on a copper plate, a change in solderability by heat treatment was examined by the following method.

【0023】圧延銅板(25×25×0.3mm)を電解
脱脂、酸洗した後、無電解パラジウムめっき液〜の
各めっき液を用いて、0.1μmのパラジウムめっき皮
膜を形成した後、水洗し乾燥した。これらを試料とし
て、230℃で10分、30分又は60分の加熱、25
0℃で10分又は30分の加熱を行ない、加熱前及び加
熱後のはんだ付け性を調べた。比較として、パラジウム
めっきなしの試料についても同様に試験した。測定方法
は次の通りである。結果を下記表1に示す。
A rolled copper plate (25 × 25 × 0.3 mm) is electrolytically degreased and pickled, and then a 0.1 μm palladium plating film is formed using each of the electroless palladium plating solutions, and then washed with water. And dried. Using these as samples, heat at 230 ℃ for 10 minutes, 30 minutes or 60 minutes, 25
Heating was performed at 0 ° C. for 10 minutes or 30 minutes, and the solderability before and after heating was examined. As a comparison, a sample without palladium plating was similarly tested. The measuring method is as follows. The results are shown in Table 1 below.

【0024】○はんだ付け性試験 RHESCA社製、ソルダーチェッカーを用いて、溶融
はんだの試験片に対する作用力が上向きから下向きに変
化し、上下方向の作用力が平衡して0になるまでの時間
(秒)を測定し、これをゼロクロスタイムとした。ゼロ
クロスタイムが小さいほど、はんだのぬれ性が良く、は
んだ付け性が良好であるといえる。試験条件は以下の通
りである。
○ Solderability test Using a solder checker manufactured by RHESCA, the time until the acting force of the molten solder on the test piece changes from upward to downward, and the acting force in the vertical direction is balanced and becomes zero ( Second) was measured and this was taken as the zero cross time. It can be said that the smaller the zero cross time, the better the solder wettability and the better the solderability. The test conditions are as follows.

【0025】溶融はんだ (63重量%錫/37重量%
鉛、共晶はんだ) 230±1℃ 浸漬深さ 12mm 浸漬速度 25mm/sec 浸漬時間 10秒 感度 2g フラックス タムラ化研(株)製、ソルダーライトMH
−820V
Molten solder (63 wt% tin / 37 wt%
Lead, eutectic solder) 230 ± 1 ℃ Immersion depth 12mm Immersion speed 25mm / sec Immersion time 10 seconds Sensitivity 2g Flux Tamura Kaken Co., Ltd. Solderlight MH
-820V

【0026】[0026]

【表1】 [Table 1]

【0027】以上の結果から、パラジウムめっき皮膜を
形成した場合に、熱処理によるはんだ付け性の低下が少
ないことがわかる。
From the above results, it is understood that when the palladium plating film is formed, the solderability is less likely to be deteriorated by the heat treatment.

【0028】[0028]

【実施例2】実施例1と同様にして、圧延銅板を電解脱
脂、酸洗した後、触媒液(商標ICPアクセラ200ml
/l水溶液、奥野製薬工業(株)製)を用いて、30℃
で30秒間浸漬して触媒を付与した。次いで、無電解パ
ラジウムめっき液〜の各めっき液を用いて、0.1
μmのパラジウムめっき皮膜を形成した後、水洗し乾燥
した。パラジウムめっきの析出時間は、実施例1に比べ
て短時間であった。これらを試料として、実施例1と同
様にして、熱処理前後のはんだ付け性を調べた。結果を
下記表2に示す。
Example 2 A rolled copper sheet was electrolytically degreased and pickled in the same manner as in Example 1, and then a catalyst solution (trademark ICP Accelerator 200 ml) was used.
/ L aqueous solution, manufactured by Okuno Chemical Industries Co., Ltd., at 30 ° C
The catalyst was applied by immersing in 30 seconds. Then, using each plating solution of electroless palladium plating solution
After forming a palladium plating film of μm, it was washed with water and dried. The deposition time of palladium plating was shorter than that in Example 1. Using these as samples, the solderability before and after the heat treatment was examined in the same manner as in Example 1. The results are shown in Table 2 below.

【0029】[0029]

【表2】 [Table 2]

【0030】以上の結果から、パラジウムめっき皮膜を
形成した場合に、熱処理によるはんだ付け性の低下が少
ないことがわかる。
From the above results, it is understood that when the palladium plating film is formed, the solderability is less likely to be deteriorated by the heat treatment.

【0031】[0031]

【実施例3】実施例2と同様にして、銅板に触媒を付与
した後、無電解パラジウムめっき液を用いて、0.0
05〜10μmの間の各種膜厚のパラジウムめっき皮膜
を形成した。実施例1と同様にして、熱処理前後のはん
だ付け性を調べた結果を下記表3に示す。
Example 3 In the same manner as in Example 2, after applying a catalyst to a copper plate, an electroless palladium plating solution was used for 0.0
Palladium plating films having various film thicknesses between 05 and 10 μm were formed. The results of examining the solderability before and after the heat treatment in the same manner as in Example 1 are shown in Table 3 below.

【0032】[0032]

【表3】 [Table 3]

【0033】以上の結果から、0.01μm以上のパラ
ジウムめっき皮膜を形成した場合に、熱処理によるはん
だ付け性の低下が少ないことがわかる。
From the above results, it can be seen that when a palladium plating film having a thickness of 0.01 μm or more is formed, the solderability is less deteriorated by the heat treatment.

【0034】[0034]

【実施例4】実施例1と同じ圧延銅板を電解脱脂、酸洗
した後、以下の各処理法により、無電解パラジウムめっ
き液を用いてパラジウムめっき皮膜を形成した。ソフ
トエッチングは、過硫酸アンモニウム150g/l水溶
液に30℃で60秒間浸漬することによって行なった。
触媒付与は実施例2と同様にして行なった。
Example 4 The same rolled copper plate as in Example 1 was electrolytically degreased and pickled, and then a palladium plating film was formed using an electroless palladium plating solution by the following treatment methods. The soft etching was performed by immersing in a 150 g / l ammonium persulfate aqueous solution at 30 ° C. for 60 seconds.
The catalyst was applied in the same manner as in Example 2.

【0035】○処理法1 ソフトエッチング→酸洗→触媒付与→パラジウムめっき
(0.1μm)→乾燥 ○処理法2 ソフトエッチング→触媒付与→パラジウムめっき(0.
1μm)→乾燥 ○処理法3 電気銅めっき(10μm)→触媒付与→パラジウムめっ
き(0.1μm)→乾燥 ○処理法4 電気銅めっき(10μm)→ソフトエッチング→触媒付
与→パラジウムめっき(0.1μm)→乾燥 ○処理法5 触媒付与→無電解ニッケルめっき(2μm)→酸洗→パ
ラジウムめっき(0.1μm)→乾燥上記したいずれの
処理法を用いた場合にも、実施例1と同様の条件で熱処
理を行なった後、はんだ付け性試験を行なった場合に、
ゼロクロスタイムは1.3〜1.8秒であり、はんだ付
け性は良好であった。
○ Processing method 1 Soft etching → pickling → catalyst application → palladium plating (0.1 μm) → drying ○ Processing method 2 soft etching → catalyst application → palladium plating (0.
1 μm) → drying ○ Processing method 3 electrolytic copper plating (10 μm) → catalyst application → palladium plating (0.1 μm) → drying ○ processing method 4 electrolytic copper plating (10 μm) → soft etching → catalyst application → palladium plating (0.1 μm) ) → Drying ○ Treatment method 5 catalyst application → electroless nickel plating (2 μm) → pickling → palladium plating (0.1 μm) → drying In any of the above treatment methods, the same conditions as in Example 1 were used. When a solderability test is performed after heat treatment at
The zero cross time was 1.3 to 1.8 seconds, and the solderability was good.

【0036】一方、上記処理法1〜5において、パラジ
ウムめっきを行なわない場合には、230℃、30分以
上又は250℃、10分以上の熱処理後に、全ての試料
がゼロクロスタイム10秒以上となり、はんだ付け性が
著るしく低下した。
On the other hand, in the above treatment methods 1 to 5, when the palladium plating is not performed, all the samples have a zero cross time of 10 seconds or more after heat treatment at 230 ° C. for 30 minutes or more or 250 ° C. for 10 minutes or more, Solderability was significantly reduced.

【0037】[0037]

【実施例5】ガラスエポキシ銅張積層板に穴あけをし、
無電解銅めっき、電気銅めっきを行なった後、エッチン
グレジスト層を形成し、次いで、エッチング、エッチン
グレジスト層剥離、ソルダーレジスト印刷、文字印刷、
外形加工の工程を経て得られた両面表面実装部品と片面
挿入型部品の混在実装用の100×170×16mmの銅
めっきスルーホールプリント配線板50枚について以下
の処理を行なった。
[Example 5] A glass epoxy copper-clad laminate was perforated,
After performing electroless copper plating and electrolytic copper plating, an etching resist layer is formed, and then etching, etching resist layer peeling, solder resist printing, character printing,
The following processing was performed on 50 100 × 170 × 16 mm copper-plated through-hole printed wiring boards for mixed mounting of double-sided surface mounting components and single-sided insertion type components obtained through the outer shape processing step.

【0038】プリント配線板を浸漬脱脂、酸洗した後、
ソフトエッチングを行ない、次いで酸洗後、触媒を付与
し、無電解パラジウムめっき液を用いて、膜厚0.1
μmのパラジウムめっき皮膜を形成し、水洗、乾燥し
た。ソフトエッチング、触媒付与は実施例4と同様にし
て行なった。
After the printed wiring board is immersed in degreasing and pickled,
Soft etching is performed, followed by pickling, then a catalyst is applied, and a film thickness of 0.1 is obtained using an electroless palladium plating solution.
A palladium plating film of μm was formed, washed with water and dried. Soft etching and catalyst application were performed in the same manner as in Example 4.

【0039】このプリント配線板の片面について、はん
だペーストをパット上に印刷し、表面実装部品を搭載し
た後、全面加熱リフローソルダリングにより、はんだ付
けし、次に、他方の面にも同様に、表面実装部品をリフ
ローソルダリングによりはんだ付けした後、挿入型部品
を手はんだ付けにより接合した。50枚のプリント配線
板の全箇所において、良好なはんだ付け接合が得られ、
不良率は0%であった。
On one surface of this printed wiring board, a solder paste was printed on a pad, surface-mounted components were mounted, and then soldering was carried out by full-heat reflow soldering, and then on the other surface, similarly. After soldering the surface mount components by reflow soldering, the insertion type components were joined by hand soldering. Good solder joints were obtained at all locations on the 50 printed wiring boards.
The defective rate was 0%.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】銅金属による導体回路及びその上に形成し
たソルダーレジストパターンを有するプリント配線板の
銅金属上に、無電解パラジウムめっき液を用いて、厚さ
0.01μm〜0.2μmのパラジウムめっき皮膜を形
成することを特徴とするプリント配線板の製造法。
1. A thickness of a conductor circuit made of copper metal and a copper wiring of a printed wiring board having a solder resist pattern formed thereon, which is formed by using an electroless palladium plating solution.
A method for producing a printed wiring board, which comprises forming a palladium plating film of 0.01 μm to 0.2 μm .
JP3078132A 1991-01-18 1991-01-18 Manufacturing method of printed wiring board Expired - Lifetime JPH0828561B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3078132A JPH0828561B2 (en) 1991-01-18 1991-01-18 Manufacturing method of printed wiring board
DE19924201129 DE4201129A1 (en) 1991-01-18 1992-01-17 Palladium-coated printed wiring boards - for integrated circuits, with improved solderability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3078132A JPH0828561B2 (en) 1991-01-18 1991-01-18 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH04236485A JPH04236485A (en) 1992-08-25
JPH0828561B2 true JPH0828561B2 (en) 1996-03-21

Family

ID=13653358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3078132A Expired - Lifetime JPH0828561B2 (en) 1991-01-18 1991-01-18 Manufacturing method of printed wiring board

Country Status (2)

Country Link
JP (1) JPH0828561B2 (en)
DE (1) DE4201129A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882736A (en) * 1993-05-13 1999-03-16 Atotech Deutschland Gmbh palladium layers deposition process
JPH06350227A (en) * 1993-06-08 1994-12-22 Nec Corp Surface treating method for printed wiring board
EP0697805A1 (en) * 1994-08-05 1996-02-21 LeaRonal, Inc. Printed circuit board manufacture utilizing electroless palladium
US6534192B1 (en) 1999-09-24 2003-03-18 Lucent Technologies Inc. Multi-purpose finish for printed wiring boards and method of manufacture of such boards
DE10018025A1 (en) 2000-04-04 2001-10-18 Atotech Deutschland Gmbh Production of solderable surface on circuit carriers in circuit board manufacture comprises preparing a dielectric substrate having copper structures, producing solderable surfaces, and forming functional surfaces in functional regions
JP4069181B2 (en) * 2002-03-29 2008-04-02 Dowaメタルテック株式会社 Electroless plating method
JP4598782B2 (en) * 2006-03-03 2010-12-15 日本エレクトロプレイテイング・エンジニヤース株式会社 Palladium plating solution
JP4822526B2 (en) * 2006-09-15 2011-11-24 株式会社豊田中央研究所 Zygote
EP1956114A1 (en) * 2007-01-30 2008-08-13 ATOTECH Deutschland GmbH A layer assembly, a method of forming said layer assembly and a circuit carrier comprising said layer assembly
JP5668375B2 (en) * 2009-11-12 2015-02-12 デクセリアルズ株式会社 Method for manufacturing flexible printed wiring board and method for forming terminal portion

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2113477B (en) * 1981-12-31 1985-04-17 Hara J B O Method of producing printed circuits
US4804410A (en) * 1986-03-04 1989-02-14 Ishihara Chemical Co., Ltd. Palladium-base electroless plating solution
JPH0222992U (en) * 1988-07-29 1990-02-15
EP0370133A1 (en) * 1988-11-24 1990-05-30 Siemens Aktiengesellschaft Process for producing printed-circuit boards

Also Published As

Publication number Publication date
JPH04236485A (en) 1992-08-25
DE4201129A1 (en) 1992-07-23

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