JPH08274816A - Data transmission method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a method and system for routing data transmission with a broad band width efficiently at a low cost. SOLUTION: The system employs a high performance standard IO interconnection bridge hardware for a parallel machine provided with a packet exchange network and connects a parallel processor to an external network by combining a new hardware and a new software. The hardware is a bridge to connect an internal interprocessor exchange 11 to an external asynchronous transfer node network. The software is a mirror forming the connection.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to parallel processing machines and, more particularly, to internet connections in such machines.

[0002]

2. Description of the Related Art A parallel machine (for example, IBM's 9076 model SP1 and SP2) is connected to an external local machine.
The conventional method for connecting to area networks (LANs) and wide area networks (WANs) is to use a general-purpose computer as an internet protocol (IP).
-Used as a router. However, this method has a narrow bandwidth, a long waiting time, and is expensive.

Another method uses a general purpose LAN hub as a router instead of a general purpose computer. However, there are many different types of hubs, and each of them uses different methods for data transmission between many LAN and WAN adapter boards. Building a unique parallel machine adapter for each of these hubs is extremely costly.

In the third method, a gateway router
Use a computer. However, the gateway router computer cannot guarantee the identifiable (i.e. low variability) latency required by applications such as video servers. here,
The latency is defined as the time it takes for a data packet to pass through a device, in this case a gateway. Future applications are expected to require high performance Asynchronous Transfer Mode (ATM) networks, such as for transmission of video information, but such applications require data to be delivered at identifiable time intervals.
Packet delivery needs to be guaranteed. Therefore, the waiting time must be known in advance. If not, a large amount of buffering is required at the receiver to facilitate the delivery of non-constant data packets.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and system for efficiently and inexpensively routing wide bandwidth data transmissions.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides data transmitted from one processor in a multiprocessor system to a plurality of data in the system or in an external network linked to the system. To one of the destinations of the. The method comprises the steps of generating an internet protocol destination address that represents the desired destination of the data, generating an internal source address that represents the internal address of the source of the data to be transmitted, and Generating an internal destination address representative of the internal destination of the data when the device in the multiprocessor system is constructed to send the data to its desired destination; and an internet protocol destination address. , Attaching to the internal destination address of each processor in the system having different input / output (IO) ports, and sending data from the internal source to the Internet protocol destination via the internal destination. .

The present invention includes a bridge or apparatus for connecting two different media and associated software. On one end of the bridge is a parallel processor interconnect switch, which is internal to the processor to which it is connected. On the other end of the bridge, the industry standard A
There is a TM network. For more information on ATM networks, see Understanding Asynchronous Transfer Mo
de (ATM) "(W. Clark, Cabletron Systems, 1993). The ATM network is not part of the bridge. IP traffic from the interconnection switch
Received by the switch interface integrated circuit (IC),
Sent to dual port RAM. When a sufficient amount of data has been received, transmission to the ATM will begin. ATM
The chip retrieves the data from the dual port RAM and sends it out to the network.

The present invention provides identifiable latency and very small variations in parallel machine IO interconnects. This is because it is designed to minimize competing traffic on any data path within the parallel machine. That is, the bandwidth of the parallel machine interconnect is much higher than the bandwidth required for the internet connection. Another factor is the nature of the control software. The control software runs only in specific cases. It is at the beginning and end of each IP packet (ie the header processing and cleaning stage of each packet).
Moreover, this software runs within a certain time. Random events that induce fluctuations in the communication path do not occur.

The software implemented method of the present invention allows this efficient bridging hardware to act as a router or hub, routing packets in and out of parallel machines. A technique called "mirroring" routes these IP packets to the correct IO bridge path, or "reflect".
It is used to Mirroring is scalable and is used both at the output and the input of packets. That is, the mirroring process is scaled up in the system so that its capacity and function correspond approximately linearly to increased performance. Thus, the present invention allows for increased bandwidth without introducing additional latency or fluctuations.

In the preferred embodiment, the mirroring functionality is contained in microcode residing at any of several locations within the processing node (element 106 in FIG. 2). By executing the microcode in the communication adapter 104 in FIG. 2, the mirror processing can be utilized to the maximum extent, which will be described later. Another implementation location is the processing node itself and the telecommunication switch interface IC 102 of FIG.

System Hardware As shown in FIG. 1, the present invention provides a means for connecting a parallel processor switch 11 to a standard WAN such as an ATM network. The exchange interface IC 10 is an ASIC having a data transfer function, and is used as a buffer for data input to and output from the parallel processor exchange 11. The data transfer IC 12 is also an ASIC having a data transfer function and is used to connect the switch interface IC 10 to the dual port RAM 14 and the microprocessor bus 16. Most of the data traffic in this configuration is due to the switch interface IC 10 and dual port RAM1.
Exists between 4 and 4. Slightly microprocessor 1
8 may only communicate with the switch interface IC 10 or the dual port RAM 14 (eg, under header or trailer processing and non-standard conditions). Accordingly, the data transfer chip 12 serves to isolate the traffic on the microprocessor bus 16 from the traffic between the switch interface IC 10 and the dual port RAM 14.

According to the flow of the main data traffic, the data entering / exiting the parallel processor switch 11 is passed through the data transfer IC 12 to be dualized.
It is stored in the port RAM 14. Therefore, the dual port RAM 14 is provided between the two transmission media, namely the parallel processor switch 11 and the ATM network 2 of FIG.
Used to collect and buffer traffic to and from 4A.

A sufficient amount of data in the dual port RAM 14 (a sufficient amount here depending on the expected rate of data transmission in and out of the RAM 14 and being set dynamically) is, for example, exchanged. Once it arrives from device 11, data can be sent towards the ATM side of this bridge. The entire IP packet may have a length of 65000 bytes or more, but it is not necessary to wait for the start of transmission to the ATM side until the entire IP packet completely arrives from the parallel processor switch 11.

Since the bandwidth of ATM is much less than that of a parallel processor switch, dual port RAM 14 can support several ATM links at the same time. On the ATM side, various segmentation and reassembly (SA)
R) IC chips can be used. In the preferred example, any of these ICs can be used. ATMSARAA
The L chip 22 is a dual port RAM bus (DPR).
The bus 20) is connected to the dual port RAM 14.

There are many types of ATM physical layer chips 24. All of these work equally well.

The properties of ATM elements are described in the Clark reference cited above.

On the microprocessor bus 16, a microprocessor 18, a static RAM 26,
There is an ATM control interface 28 connected to the ATM SARAAL chip 22. Microprocessor 18
Executes control microcode that handles the IP header and various interface-specific control functions. In particular, the microprocessor 18 examines the packet header to determine the desired destination. A further function of the microprocessor 18 is that ATMSARAA when a sufficient amount of data is received in the dual port RAM 14.
Instruct the L chip 22 to start reading data from the dual port RAM 14. In addition, the microprocessor 18 initiates the appropriate cleaning function by processing the trailer byte at the end of the packet. Static RAM 26 stores programs and any temporary data structures used by microprocessor 18 to perform its functions. AT
The M control interface 28 is the microprocessor 18
Buffer and latch functions that allow communication between the ATMSARAAL chip 22 and the ATMSARAAL chip 22. This allows the microprocessor 18 to control initialization of the ATMSARAAL chip 22 and its functions.

In the preferred embodiment of the present invention, the microprocessor 18 used to control the function of the IP bridge according to the present invention does not execute general purpose operating system software. It is best to leave the system maintenance function performed by such software to a general-purpose host computer. this is,
Most preferably, the microprocessor bus 16 is implemented by connecting to a host computer via an industry standard host interface such as a PCI bus or a Micro Channel bus. In this way, the host
The computer can collectively support these multiple IP bridges.

Software-Direct Routing FIG. 2 illustrates a processor-IO port mapping from a group of processors to various external IO ports according to the present invention. The bridge interconnect hardware 102 in FIG. 2 is preferably implemented using the hardware configuration of FIG. The high performance interconnect switch 100, adapter card 104 and processor 106 are located in a parallel processing machine. In the preferred example, the adapter
The card 104 is physically installed within the associated processor 106. Bridge interconnect hardware 102
May be located external to the parallel processing machine with inputs from the processor via a cable.

The mapping between the processor and the IO port is
This is done based on the source address of the transmitted packet (ie, the address of the device initiating the transmission). This address is defined by hardware or programmable logic. In this arrangement, all packets leaving the system are
It is sent to the IO port associated with the originating processor. The bridge interconnect hardware protocol segments the IP packet and encloses each resulting segment in a parallel processor switch network routing header and a trailer. The Parallel Network Header (PNH) contains a field for the destination address and a field for the source address within the parallel machine.

FIG. 3 is a diagram showing a route that a packet takes when moving directly from a processor to a switch. This is the I sent internally from eg a given processor.
The destination of the P packet is the IO related to the processor.
Occurs only if it is a port. As an example, when processor A attempts to communicate with external machine W, source A
From the destination to the destination W is created. PNH
Contains the source address of A and the destination address of R, where R is the link between the high performance interconnect switch 100 and the bridge interconnect hardware 102 for IO port W. . There may be one or more links similar to R, depending on the number of external ports and internal processors. These links are configured so that transmissions between external ports and a given processor are always transports on the same link.

Upon receipt of the packet, the microprocessor 18 operating in microcode (FIG. 1) causes the PN
After inspecting the source field of the H header, it is discarded. This source field is used to route the IP packet to the IO / A external port in this case (because this source is a processor inside the system). After that, IP routing is performed by the device W.
Used for the rest of the transmission to.

In the opposite situation, that is, when receiving a packet from the interface IO / A port, the bridge interconnect hardware 102 (specifically the microprocessor 18 in FIG. 1) causes the R and A source fields and the transmit field, respectively. The PNH header with the first field automatically surrounds the IP packet. This instructs the parallel switching network to route the IP packet to processing node A. The communication adapter card associated with processor A sends this packet to IP
Identify it as a packet and verify that its source is the routing interface R. Destination of PNH and I
Since both P's destinations are this node, this packet is received and further processed.

Software-Mirror Processing Routing The communication adapter card 104 microcode is PN
The source field and the destination field of H are compared to determine whether or not mirror processing should be performed. The mirroring process is necessary, for example, when the destination of an IP packet created by a given processor is an IO port not related to that processor. In the mirror process,
All packets leaving the system are sent (via the local routing table of the TCP / IP protocol stored in the processor) to the processor associated with the desired IO network. The processor that receives this packet is the processor associated with that desired IO port. This processor detects that mirror processing is requested and sends the packet to its IO.
"Reflection transfer" to the network interface port. This detection is done by examining the IP destination (ie, global destination address) and the source and destination fields (local address) of the PNH.

FIG. 4 is a diagram showing how a packet is sent from processor group D to a IO / A port via a mirror processing path. When attempting to transmit a packet from parallel machine D to external machine W, an internet packet is created from PNH source D to IP destination W. This causes problems in standard systems. This is because only processor A is configured to communicate with external machine W. According to the present invention, the D from the PNH source field and the A from the PNH destination field are used to determine the IP from the processor D.
The new network software is configured to route the packet to Node A, which "reflects and forwards" it. In any case, the node that performs the "reflection transfer" is the node associated with the desired IO port.
When the packet is received, the communication adapter of processor A
The card checks the IP destination address and PNH source. IP originating from another processor (ie D, not IO interface) and desired
Since the destination is not A, the packet is "reflected and forwarded"
To be done. In order to "reflect and forward" packets, the PNH
It is necessary to change the source and destination fields. In this example, they are changed to A and R, respectively. The packet is then successfully routed to the IO / A port.

In the opposite situation, ie, when a packet is received from the external device W on the interface IO / A port, the bridge interconnection hardware will be
And automatically enclose the packet with a PNH header with source and destination fields of A. This allows the parallel switching network to route the IP packet to processing node A. The communication adapter card associated with processor A identifies this packet as an IP packet and verifies that its source is routing interface R. Since the IP destination is not processor A (which is determined from the packet's IP destination field), the packet is "reflective forwarded" to the appropriate processor using a lookup table of IP addresses with parallel switching node routing. Will be done. This table is stored in the processor. That is, the IP destination address is translated into a PNH destination field that identifies the destination processor.

In the preferred embodiment, tables mapping the links between external IO ports and internal processors are used for mirroring, but these tables are only needed for routing within parallel machines. And their size is constant and limited by the number of processors in the parallel machine. The external device routing table is created and maintained by TCP / IP software within the compute node. This is desirable because this list of external devices can be large and dynamic. Furthermore, the time to mirror a packet that it receives is constrained by the time to search a list of n entries plus the time to "reflect and forward" this packet to the network.

Further, the processor can reside in a parallel machine that does not have a logical IO port mapping. These processors exclusively communicate with the IO port via the mirror processing transfer to the designated port. Therefore, all traffic on these processors will be mirrored.

In summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) 1 in the multiprocessor system
A processor for transmitting data to one of a plurality of destinations in the multiprocessor system or in an external network linked to the multiprocessor system, each processor in the multiprocessor system comprising: Associating with different IO ports of a multiprocessor system, generating an internet protocol destination address representing the desired destination of the data, and an internal source representing the internal address of the source of the transmitted data. Generating an address and one in the multiprocessor system configured to send the data to the desired destination.
Generating an internal destination address representing the internal destination of the data when the device is an internal destination,
A data transmission method comprising: attaching the Internet protocol destination address to the internal destination address; and transmitting the data from the internal source to the Internet protocol destination via the internal destination. (2) The step of transmitting the data from the internal transmission source to the Internet protocol transmission destination via the internal transmission destination, wherein the internal transmission destination is the multiprocessor.
In the case of one processor in the system, transmitting the data and the Internet protocol destination address to the internal destination, and via the IO port associated with the processor that is the internal destination, Transmitting the data to the Internet protocol destination, the data transmission method according to (1). (3) including transmitting said data from said internal destination through a bridge interconnect to its associated IO port, said bridge interconnect establishing a data buffer means and a threshold for data reception. Has and
The data transmission method according to (2) above, wherein the data buffer means starts transferring the data to the Internet protocol destination. (4) In a method of transmitting data from one processor in a multiprocessor system having a plurality of processors to one of a plurality of destinations in the multiprocessor or in an external network linked to the multiprocessor, A bridge coupled to receive data transmission signals from a plurality of processors and each external port configured to directly receive and transmit data directly to only one of the plurality of processors, said bridge A data transmission system having a plurality of external ports coupled to receive a data signal from the plurality of external ports and means for transmitting data from any of the plurality of processors to any of the plurality of external ports. (5) The data transmission system according to (4), further comprising means for dynamically setting a data threshold value for transmitting data from the bridge to one of the plurality of external ports. (6) One or more processors of the plurality of processors are not mapped to any of the plurality of external ports, and the multiprocessor system is configured from the unmapped one or more processors. 6. The data transmission system according to (5) above, including means for routing a data transmission signal to one of the plurality of external ports via the data transmission means.

[Brief description of drawings]

FIG. 1 is a block diagram of a system according to the present invention.

FIG. 2 is a diagram showing mapping of processors to IO ports according to the present invention.

FIG. 3 is a diagram showing packet transmission by direct routing in the system of the present invention.

FIG. 4 is a diagram showing packet transmission by mirror processing routing in the system of the present invention.

[Explanation of symbols]

 10 Switching Interface IC 11 Parallel Processor Switch 12 Data Transfer Device 14 Dual Port RAM 16 Microprocessor Bus 18 Microprocessor 20 DPR Bus 22 ATMSARAL Chip

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michael Mim Zao, Delano Road, Yorktown Heights, NY 10598, NY 746

Claims (6)

[Claims] 1. A method of transmitting data from a processor in a multiprocessor system to one of a plurality of destinations in the multiprocessor system or in an external network linked to the multiprocessor system. Associating each processor in the multiprocessor system with a different IO port of the multiprocessor system; generating an internet protocol destination address representative of a desired destination of the data; Generating an internal source address representative of the internal address of the source of the data; one device in the multiprocessor system configured to send the data to the desired destination is the internal destination. Internal destination indicating the internal destination of the data, if Generating an address; attaching the Internet protocol destination address to the internal destination address; transmitting the data from the internal source to the Internet protocol destination via the internal destination. A data transmission method including and. 2. The step of transmitting the data from the internal source to the Internet protocol destination via the internal destination, wherein the internal destination is one processor in the multiprocessor system. Transmitting the data and the Internet protocol destination address to the internal destination, the data to the Internet protocol destination via the IO port associated with the processor that is the internal destination. The data transmission method according to claim 1, further comprising a step of transmitting. 3. Transmitting said data from said internal destination through a bridge interconnect to its associated IO port, said bridge interconnect setting a data buffer means and a threshold for data reception. And the data buffer means initiates the transfer of the data to the Internet protocol destination.
The data transmission method described in. 4. A method of transmitting data from a processor in a multiprocessor system having multiple processors to one of a plurality of destinations in the multiprocessor or in an external network linked to the multiprocessor. A bridge coupled to receive data transmission signals from the plurality of processors, and each external port configured to directly receive and transmit data directly to only one of the plurality of processors, A data transmission system comprising: a plurality of external ports coupled to receive a data signal from the bridge; and means for transmitting data from any of the plurality of processors to any of the plurality of external ports. 5. The data transmission system according to claim 4, further comprising means for dynamically setting a data threshold for transmitting data from the bridge to one of the plurality of external ports. 6. One or more of the plurality of processors are not mapped to any of the plurality of external ports and the multiprocessor system is the one or more unmapped. 6. A data transmission system according to claim 5, comprising means for routing a data transmission signal from a processor via said data transmission means to one of said plurality of external ports.