JPH08274277A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a semiconductor memory device (DRAM) more enhanced in degree of integration exceeding a prior art. CONSTITUTION: A stereoscopic SOI(Silicon-On-Insulator) structure is formed on a part of a silicon substrate, and a capacitor and an insulated gate field effect transistor channel forming region are formed in one piece inside the SOI structure. The channel forming region (130a, b) of an insulated-gate field effect transistor is formed on the side wall of the stereoscopic SOI structure, the drain (or source) region of the insulated-gate field effect transistor is formed as continuously connected to the channel forming region, and a capacitor is formed overlapping with the drain (or source) region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to DRAM.

[0002]

2. Description of the Related Art A general memory cell of a DRAM is shown in FIG.
As shown in FIG. 3, it is composed of an nMOS transistor (Q) and a capacitor (C).

FIG. 12 is a sectional view of a memory cell having a conventional structure using a trench capacitor as the above-mentioned capacitor (C).

In this memory cell, an nMOS transistor (polysilicon gate 710, gate insulating film 740, source / drain regions (drain, source region) 720a, 720b is formed on the surface of a silicon (Si) substrate 700.
And a trench capacitor (an inner electrode 760 made of polysilicon) is formed in the vicinity thereof.
And the outer electrode 7 composed of the SiO ₂ film 750 and the n ⁺ diffusion layer.
And 30) are formed.

Outer electrode (n ⁺ ) 7 of trench capacitor
30 is an n-type region (drain or source region) to be connected to the trench capacitor of the MOS transistor
It is formed by connecting to 720b.

Also, the inner electrode 76 of the trench capacitor
Since 0 needs to be at the ground potential, it is connected to the aluminum (Al) electrode 770 (ground wiring) through the contact hole.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
D using a conventional trench capacitor as a memory capacitor
In the RAM, the outer electrode of the trench capacitor is composed of an n ⁺ diffusion layer (730) provided so as to surround the outer side of the trench (groove).

Therefore, the memory cells must be arranged at a distance T so that the n ⁺ diffusion layers (730) are not in contact with each other (FIG. 12), and a margin is required to prevent high integration. It has become.

As a matter of course, since the MOS transistors forming the memory cells of the DRAM are formed on the surface of the wafer, it is necessary to secure a region for forming the transistors. For the above reasons, the conventional memory cell structure has a certain limit in high integration.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a semiconductor memory device and a method of manufacturing the same which further attains higher integration beyond the limit of the prior art. To do.

[0011]

The present invention which achieves the above object has the following constitution.

(1) The present invention according to claim 1 is a semiconductor memory device in which a memory cell is composed of an insulated gate field effect transistor and a capacitor, wherein a three-dimensional SOI ( Silicon On In
a three-dimensional SOI is formed.
In the structure, the capacitor and the channel forming region of the insulated gate field effect transistor are integrally formed, and the channel forming region of the insulated gate field effect transistor is formed into a sidewall portion in the three-dimensional SOI structure. It is characterized in that it is formed.

(2) The present invention according to claim 2 provides the invention according to claim 1, wherein the drain (or source) region of the insulated gate field effect transistor is formed so as to be connected to the channel forming region. It is characterized in that the capacitor is formed so as to overlap the source region.

(3) The present invention according to claim 3 is a semiconductor memory device in which a memory cell is composed of an insulated gate field effect transistor and a capacitor, and a three-dimensional SOI (Silicon) is formed on a part of a silicon substrate. On Insu
Lateral structure is formed, and this three-dimensional SOI structure has a groove portion having a side wall perpendicular to the surface of the silicon substrate in a part of the silicon substrate, and an insulating layer is provided on the inner surface of the groove portion. The groove is formed by connecting the first region provided along the side wall perpendicular to the surface of the silicon substrate and the first region provided at the bottom of the groove. A second area,
A gate insulating film provided to cover the surface of the first region and a gate electrode layer formed in contact with the gate insulating film are formed, and the first region is the insulated gate field effect. Constitutes the channel formation region of the transistor,
A portion of the second region, which is connected to the first region, constitutes a drain (or a source) of the insulated gate field effect transistor, and the silicon substrate is connected to a predetermined potential. The silicon substrate is used as a first node, the bottom of the second region in the groove is used as a second node, and the insulating layer interposed between the silicon substrate and the second region is used as a dielectric layer. It is characterized in that a trench capacitor is configured.

(4) The present invention according to claim 4 is a method of manufacturing a semiconductor memory device in which a memory cell is composed of an insulated gate field effect transistor and a capacitor, the surface of which is covered with an insulating film. A step of forming a groove having a side wall substantially perpendicular to the surface of the silicon substrate in a part of the silicon substrate and forming an insulating layer on the inner surface of the groove, and impurities at the bottom of the groove. First doped
A step of forming an amorphous silicon layer, a step of forming an opening in a part of the insulating film covering the surface of the silicon substrate to form a seed region in which a part of the surface of the silicon substrate is exposed, Forming a second amorphous silicon layer that covers the seed region and extends along a sidewall of the groove portion that is perpendicular to the surface of the silicon substrate, and that connects to the first amorphous silicon layer; By performing the heat treatment, solid phase epitaxial growth (Solid Phase) starting from the seed region in the second and first amorphous silicon layers is performed.
Epitaxy; SPE) to obtain a single crystal silicon layer, a gate insulating film is formed on the surface of the single crystal silicon layer, and a gate electrode layer is formed on the gate insulating film. A step of obtaining an insulated gate field effect transistor in which a portion of the single crystal silicon layer along a side wall perpendicular to the surface of the silicon substrate is used as a channel formation region; and the silicon substrate is connected to a predetermined potential and the silicon And a step of forming a capacitor having the substrate as a first node and the bottom portion of the single crystal silicon layer of the groove portion as a second node.

(5) A fifth aspect of the present invention is a semiconductor memory device in which a memory cell is composed of an insulated gate field effect transistor and a capacitor, wherein the insulated gate is formed on an insulating film covering a surface of a silicon substrate. Type field effect transistor is formed, and the capacitor having a trench structure is formed under the drain (source) of the insulated gate field effect transistor so as to overlap the drain (or source) of the insulated gate field effect transistor. The capacitor having the structure has the silicon substrate connected to a predetermined potential as a first node, the insulating layer formed on the inner surface of the groove provided in the silicon substrate as a dielectric, and is formed on the inner surface of the groove. Filling the inside of the groove in contact with the formed insulating layer and connected to the drain (or source) of the insulated gate field effect transistor. Characterized in that the conductor layer is configured as a second node.

(6) The present invention according to claim 6 is a method of manufacturing a semiconductor memory device in which a memory cell is composed of an insulated gate field effect transistor and a capacitor, the surface of which is covered with an insulating film. Forming a groove having a side wall substantially perpendicular to the surface of the silicon substrate on a part of the substrate, forming an insulating layer on the inner surface of the groove, and the insulating film covering the surface of the silicon substrate. A step of forming an opening in a part of the substrate to form a seed region in which a part of the surface of the silicon substrate is exposed, and a step of forming an amorphous silicon layer covering the seed region and filling the groove. By performing heat treatment, solid phase epitaxial growth (Solid Phase) starting from the seed region in the amorphous silicon layer is performed.
Epitaxy; SPE) to obtain a crystalline silicon layer, and impurities are selectively introduced into the crystalline silicon layer formed on the surface of the silicon substrate to fill the groove. Forming a drain (or source) region in a form having an overlap with the crystalline silicon layer, connecting the silicon substrate to a predetermined potential, and using the silicon substrate as a first node, filling the groove portion And a step of forming a capacitor using the crystallized silicon layer as a second node.

[0018]

[Action]

(1) According to the first aspect of the present invention, a MOS transistor and a capacitor forming a memory cell of a DRAM are integrally formed in, for example, a U groove to form an SOI three-dimensional structure using the U groove. A transistor is formed on the sidewall of the groove.

By adopting such a three-dimensional SOI structure, the conventional inconvenience is solved.

That is, according to the SOI structure, no element is formed on the underlying silicon substrate, so that a potential can be freely applied to this silicon substrate.

Taking advantage of this feature, the grounded (or other DC potential) silicon substrate itself is used as the node of the capacitor, so that it is not necessary to consider the layout margin of the n ⁺ diffusion layer as in the conventional case.

Further, since the channel forming region itself of the MOS transistor is formed on the side wall portion in the groove, most of the planar transistor region is reduced.

Due to such an effect, a very high degree of integration is realized.

(2) According to the present invention of claim 2, a drain (source) region is formed in contact with the channel forming region,
Further, the capacitor is formed in a self-aligned manner by overlapping the drain (source).

Therefore, unlike the conventional case, the contact between the drain of the MOS transistor and the ground wiring is unnecessary, and since the silicon substrate itself serves as the ground wiring, it is not necessary to separately provide the ground wiring.

Due to such effects, an extremely high degree of integration is realized.

(3) According to the present invention of claim 3, an SOI structure using a trench is utilized to form the structure of claims 1 and 2. Therefore, as described above, a very high degree of integration is achieved.

That is, in the present invention, the integration between the trench capacitors is shortened as much as possible, and the area of the contact, wiring, or the like that does not directly affect the operation of the device is eliminated to improve the degree of integration and the area of the transistor itself. Can also be reduced.

(4) In the present invention according to claim 4, solid phase epitaxial growth (SPE) of silicon is used.
~ 3 (especially claim 3) to realize the SOI structure.

Solid phase epitaxial growth of silicon (SP
Regarding E), the method previously proposed by the applicant of the present application (the technique disclosed in Japanese Patent Application No. 6-193604) can be used. Here, FIG. 14A to FIG.
The outline will be described using (d).

As shown in FIG. 14A, a SiO ₂ film 1100 is formed on a silicon single crystal substrate 1000, and then, as shown in FIG. 14B, a part of the SiO ₂ film is opened to form a silicon film. A part of the single crystal is exposed to form seed (seed crystal) parts 1200a and 1200b.

Subsequently, as in (C), amorphous silicon (α-Si) 1210 is deposited and heat treatment is performed at a predetermined temperature (for example, 600 ° C.).

Then, solid phase epitaxial growth proceeds in the vertical and horizontal directions, amorphous silicon is single-crystallized from the seed crystal portion, and finally a silicon single crystal 1300 is obtained.

In this case, the crystal finally obtained by SPE is known to be affected by the underlying insulating film, and is not necessarily a single crystal. For example, when the base insulating film is Si ₃ N ₄ , the crystal obtained by SPE is polycrystalline silicon. In the present invention, such SP
The E technique is used to form a trench SOI structure.

That is, after forming an insulating layer on the inner surface of the groove formed in the silicon substrate, an amorphous layer is deposited on the insulating layer, and the seed portion provided in a part of the silicon substrate by heat treatment is used as a starting point. Cause SPE,
The amorphous layer is changed to a single crystal layer, and an active layer is formed on the insulating film. This active layer is used as a formation region for MOS transistors and capacitors.

According to this method, the MOS transistor and the capacitor can be formed by self-alignment, and a highly integrated IC can be formed with high reliability without considering the margin of the mutual positional relationship.

(5) According to the present invention of claim 5, claims 1 to
As a structure conforming to the structure of No. 3, a MOS transistor forming a memory cell of a DRAM is formed with a planar SOI structure, while a trench capacitor is formed in a region (drain or source) to be connected to the trench capacitor of the MOS transistor. The structure will be placed at the bottom with an overlap.

As a result, there is no region which the trench capacitor occupies alone, and since the silicon substrate itself is used as one pole (node) of the capacitor, the degree of integration can be improved.

That is, the distance between the trench capacitors can be reduced to the minimum rule, the ground wiring is not necessary, and the contact of the inner electrode of the capacitor is not necessary in this structure, so that the process is simple.
A DRAM with dramatically improved integration can be manufactured at a low price.

(6) In the present invention of claim 6, the structure of claim 5 is formed by using the SPE technique as in the method of claim 4. Therefore, the MOS transistor and the capacitor can be formed by self-alignment, and a highly integrated IC can be formed with high reliability without considering the margin of the mutual positional relationship.

[0041]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the semiconductor memory device of the present invention.

In this embodiment, the groove portion 50 is formed in the silicon single crystal substrate 100 connected to the ground potential, the inside of the groove portion is covered with the SiO ₂ film 110 (a), and the main surface of the silicon substrate is the SiO ₂ film. It is covered by 110 (A).

An n ⁺ layer 120, channel forming regions 130a and 130b, and an n ⁺ layer 150 are formed on these insulating films to form a three-dimensional SOI structure. Then, the gate insulating film 140 is formed on the channel regions 130a and 130b, and the inside of the trench is filled with the polysilicon gate electrode 160.

An interlayer insulating film 17 is formed on the surface of the silicon substrate.
0 is formed, and the Al electrode 180 is arranged thereon. The Al electrode 180 is n through the contact hole.
⁺ Connected to layer 150.

According to the present structure as described above, as shown by a thick line in FIG. 2, a MOS transistor Q having a channel forming region provided along the sidewall of the trench and a MOS transistor Q provided at the bottom of the trench, one end of which is provided. Grounded trench capacitance C
And are being built. That is, the MOS transistor and the capacitor that form the memory cell of the DRAM are integrated in the U-shaped three-dimensional SOI structure.

In the present embodiment, the capacitor (C) forming the memory cell of the DRAM is arranged below the n ⁺ region 120 to be connected to the capacitor of the MOS transistor, so that the area for arranging the capacitor is large. Is not required separately.

Further, one pole of the capacitor (first node)
Is connected to the n ⁺ region 120 which should be connected to the capacitor of the MOS transistor, while the Si substrate 100 itself serves as the other pole (second node) of the capacitor, the distance between the capacitors can be reduced to the minimum rule. In addition, the ground wiring and the electrode contact of the capacitor are unnecessary.

Further, M which constitutes the memory cell of the DRAM
Since the OS transistor is formed on the sidewall of the U-shaped three-dimensional SOI structure, the area of the transistor can be very small.

Further, since the U-shaped three-dimensional SOI structure can be produced by the SOI structure forming technique based on the epitaxial technique such as SPE technique (described later), the degree of integration can be dramatically improved by a simple process.

Next, an example of the manufacturing method of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, the SiO ₂ film 110 is formed on the Si single crystal substrate 100 by a process such as thermal oxidation.
(A) is deposited, and then a trench (groove) 50 is formed in the silicon substrate 100 by using RIE (reactive ion etching) or the like.

Next, as shown in FIG. 4, the SiO ₂ film 110 is formed inside the trench 50 by a process such as thermal oxidation.
(A) is deposited.

Next, doped amorphous Si (α-S
i) A film of 300 is formed, followed by RIE or the like to leave the amorphous doped Si only at the bottom of the trench.

Subsequently, a part of the SiO ₂ film is removed by photolithography, RIE, etc., and the opening (seed) part 3 is formed.
Form 10.

Next, as shown in FIG. 5, amorphous S
After i (α-Si) 400 is formed and flattened by etching on the entire surface, solid phase epitaxial growth is caused from the opening (seed) portion 310 as a starting point by SPE (Si solid phase crystal growth) technique to form a groove bottom portion. n ⁺ single crystal layer 120
Then, a single crystal layer 130 is formed along the side wall. As a result, a U-shaped three-dimensional SOI structure is formed. As a result, the MOS transistor and the electrode of the capacitor arranged below the MOS transistor are formed in a self-aligned manner, and it is not necessary to separately connect them.

The amorphous silicon layer formed in FIG. 5 can be either undoped or doped. When a non-doped one is used, it is necessary to introduce impurities in a later step in order to adjust the impurity concentration in the channel region.

After that, unnecessary portions of the single crystal grown Si film for element isolation are removed by RIE or the like, and Si is removed.
By forming an O ₂ film and removing an unnecessary SiO ₂ film portion by RIE or the like, the Si substrate exposed portion (seed) portion 310 and the element isolation region formed in the step of FIG.
Embed with an O ₂ film. Subsequently, in order to form a groove for forming the word wiring, the SiO ₂ film corresponding to the wiring portion is removed by RIE or the like to form a groove in the SiO ₂ film. This state is the state shown in the bottom diagram of FIG.

Next, as shown in FIG. 6, the gate oxide film 1
40 is formed by a process such as thermal oxidation, then a Poly-Si film to be a gate electrode is formed by a process such as CVD, and is processed by photolithography and RIE to form a gate Poly-Si electrode 160 (and this). Wiring that connects the two).

After that, a gate electrode, a wiring connecting the gate electrode, and a high concentration region 150 to be a source region are formed by ion implantation. Finally, an interlayer insulating film (for example, BPSG)
Etc.) 170 and the Al electrode 180 are formed to complete the device (FIG. 6).

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment is an example similar to the embodiment of FIG. 1, in which the MOS transistors forming the memory cell of the DRAM are constructed with a planar SOI structure, while the DRAM is
The trench capacitor (C) that constitutes the memory cell of
N of the MOS transistor to be connected to the capacitor
It is arranged immediately below the ⁺ region (drain (source) region) 420.

The trench capacitor is formed on the silicon substrate 10.
The insulating film 110 (a) is formed on the inner surface of the groove portion 50 formed in 0.
Is formed, and the groove portion 50 is filled with the polysilicon layer 430.

In this embodiment, the planar area occupied by the MOS transistor cannot be reduced, but the capacitor is n ^+.
Since it is arranged immediately below the region (drain (source) region) 420 so as to overlap therewith, the capacitor does not occupy a single area and the degree of integration can be increased.

Further, as in the above-mentioned embodiment, the Si substrate 10
Since 0 itself is connected to the common potential (ground potential) as the outer electrode of the capacitor, it is not necessary to provide a margin to prevent the outer electrodes from contacting each other unlike the conventional case.
Therefore, the minimum rule between capacitors can still be reduced.

Further, since the ground wiring and the contact between the inner electrode of the capacitor are not required, the degree of integration can be dramatically improved.

Next, an example of the manufacturing method of this embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 8, the SiO ₂ film 110 is formed on the Si single crystal substrate 100 by a process such as thermal oxidation.
(A) is deposited, and subsequently, a trench (groove portion) 50 is formed by RIE or the like.

Next, as shown in FIG. 9, a Si ₃ N ₄ film 110 (a) is formed on the inner surface of the groove 50, and a part of this Si ₃ N ₄ film is removed by photolithography and RIE. .

Then, a part of the SiO ₂ film 110 (a) is removed by photolithography, RIE or the like to form an opening (seed) portion 500 (lower side of FIG. 9).

Next, as shown in FIG. 10, SPE (Si
Solid phase crystal growth) technology, etc. on the SiO ₂ film and Si ₃ N
_A Si film is simultaneously grown as a single crystal on the _four films.

At this time, a polycrystalline Si film 430 grows on the Si ₃ N ₄ film (inside the trench capacitor) under the influence of the underlying insulating film. Further, a silicon single crystal layer 440 grows on the SiO ₂ film.

After that, the Si film, which has been polycrystal-grown for element isolation, is removed by RIE or the like, and an element isolation opening 510 is formed.
Then, a SiO ₂ film is formed, and unnecessary portions of the SiO ₂ film are removed by RIE or the like to form the exposed portion (seed portion) 500 of the Si substrate formed in the process of FIG. Embed with ₂ membranes.

Next, as shown in FIG. 11, a gate insulating film (SiO ₂ film) 140 is formed by a process such as thermal oxidation, and then a Poly-Si film to be a gate electrode is formed by CV.
Photolithography and R are formed by a process such as D
Gate Poly-Si electrode 160 processed by IE or the like
To form.

After that, a high concentration region 420 to be a source / drain region is formed by ion implantation, an interlayer insulating film (eg BPSG etc.) 170 and an Al electrode 180 are formed, and the device is completed.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to this, and various applications and modifications are possible.

For example, in the first embodiment, the MOS transistor is formed on the side wall of the groove, but the idea is changed to 3
A MOS transistor may be formed in the wall portion of the three-dimensional device. That is, the idea of the present invention of claims 1 and 2 is
This means that MOS transistors and capacitors are integrated and integrated in a three-dimensional SOI structure.

Further, in order to form the three-dimensional SOI structure described above, SPE (solid phase epitaxial growth) was used in the above-mentioned embodiment, but laser irradiation, X-ray irradiation, etc. may be used as a method for crystallizing the amorphous. Can also be used.

That is, the process technology regarding SOI is applied to construct a three-dimensional DRAM cell.

[0078]

As described above, according to the present invention, the following effects can be obtained.

(1) According to the present invention of claim 1, the three-dimensional S
By adopting the OI structure, the grounded (or other DC potential) silicon substrate itself is used as the node of the capacitor, so that it is not necessary to consider the layout margin of the n ⁺ diffusion layer as in the conventional case. Further, since the channel forming region itself of the MOS transistor is formed on the side wall portion in the groove, most of the planar transistor region is reduced. Due to such an effect, a very high degree of integration is realized.

(2) According to the present invention of claim 2, a drain (source) region is formed in contact with the channel forming region,
Further, the capacitor is formed in a self-aligned manner by overlapping the drain (source). Therefore, it is not necessary to provide a contact between the drain of the MOS transistor and the ground wiring as in the conventional case, and since the silicon substrate itself serves as the ground wiring, it is not necessary to separately provide the ground wiring. Due to such an effect, a very high degree of integration is realized.

(3) According to the present invention of claim 3, an SOI structure using a trench is utilized to form the structure of claims 1 and 2. Therefore, as described above, a very high degree of integration is achieved. That is, in the present invention, the distance between the trench capacitors is shortened as much as possible, and the area of a portion such as a contact or a wiring that does not directly affect the operation of the device is eliminated to improve the degree of integration and also reduce the area of the transistor itself. It is possible to

(4) In the present invention of claim 4, solid phase epitaxial growth (SPE) of silicon is used.
~ 3 (especially claim 3) to realize the SOI structure. According to this method, the MOS transistor and the capacitor can be formed by self-alignment, and a highly integrated IC can be formed with high reliability without considering the margin of the mutual positional relationship.

(5) According to the present invention of claim 5, claims 1 to
As a structure conforming to the structure of No. 3, a MOS transistor forming a memory cell of a DRAM is formed with a planar SOI structure, while a trench capacitor is formed in a region (drain or source) to be connected to the trench capacitor of the MOS transistor. The structure will be placed at the bottom with an overlap. As a result, there is no area occupied by the trench capacitor alone, and since the silicon substrate itself is used as one pole (node) of the capacitor, the degree of integration can be improved.

(6) In the present invention of claim 6, the structure of claim 5 is formed by using the SPE technique similarly to the method of claim 4. Therefore, the MOS transistor and the capacitor can be formed by self-alignment, and a highly integrated IC can be formed with high reliability without considering the margin of the mutual positional relationship.

[0085]

[Brief description of drawings]

FIG. 1 shows an embodiment of a semiconductor memory device of the present invention (DRA
It is sectional drawing which shows the structure of M).

FIG. 2 is an enlarged sectional view of a main part of the embodiment of FIG.

FIG. 3 is a diagram showing a first step for manufacturing the structure of the embodiment of FIG. 1 (the upper side is a cross-sectional view, and the lower side is a plan view).

FIG. 4 is a diagram showing a second step for manufacturing the structure of the embodiment of FIG. 1 (the upper side is a sectional view, the lower side is a plan view).

5 is a third embodiment for manufacturing the structure of the embodiment of FIG.
Diagram showing steps 4 and 5 (right side is a sectional view, left side is a plan view)
Is.

FIG. 6 is a view showing a sixth step for manufacturing the structure of the example of FIG. 1 (the upper side is a sectional view, and the lower side is a plan view).

FIG. 7 is a cross-sectional view showing the configuration of another embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a diagram showing a first step for manufacturing the structure of the embodiment of FIG. 7 (the upper side is a cross-sectional view, and the lower side is a plan view).

FIG. 9 is a diagram showing a second step for manufacturing the structure of the example of FIG. 7 (the upper side is a cross-sectional view, and the lower side is a plan view).

FIG. 10 is a diagram showing a third step for manufacturing the structure of the example of FIG. 7 (the upper side is a cross-sectional view, and the lower side is a plan view).

FIG. 11 is a diagram showing a fourth step for manufacturing the structure of the example of FIG. 7 (the upper side is a cross-sectional view, and the lower side is a plan view).

FIG. 12 is a cross-sectional view showing a configuration of a conventional example.

FIG. 13 is a diagram showing a general cell configuration of a DRAM.

14A to 14D are cross-sectional views in each step for explaining the outline of solid phase epitaxial growth (SPE).

[Explanation of symbols]

100 Silicon Single Crystal Substrate 110 (a) Oxide film on main surface of silicon substrate 110 (b) Oxide film in groove of silicon substrate 120 n ⁺ layer at bottom of trench forming one pole of capacitor and drain (source) of MOS transistor 130a, 130b Channel formation region 140 Gate oxide film 150 n ⁺ layer that constitutes the source (drain) of a MOS transistor 160 Polysilicon gate 170 Interlayer insulating film 180 Al electrode 190 Insulating layer for embedding seed portion 200 SOI substrate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirofumi Funabashi, Nagakute-cho, Aichi-gun, Aichi Prefecture, Nagachoji 1 41, Yokochi, Toyota Central Research Institute Co., Ltd. (72) Susumu Sugiyama, Nagakute-cho, Aichi-gun, Aichi Prefecture 41, Yokoshiro Road Inside Toyota Central Research Institute Co., Ltd.

Claims (6)

[Claims] 1. A semiconductor memory device comprising a memory cell including an insulated gate field effect transistor and a capacitor, wherein a three-dimensional SOI (Silico) is formed on a part of a silicon substrate.
n On Insulator) structure is formed, and the capacitor and the channel forming region of the insulated gate field effect transistor are integrally formed in this three-dimensional SOI structure. A semiconductor memory device, wherein a channel formation region is formed on a side wall portion in the three-dimensional SOI structure. 2. A drain (or source) region of an insulated gate field effect transistor is formed in contact with the channel forming region, and a capacitor is formed so as to overlap with the drain (or source) region. The semiconductor memory device according to claim 1, wherein: 3. A semiconductor memory device comprising a memory cell composed of an insulated gate field effect transistor and a capacitor, wherein a three-dimensional SOI (Silico) is formed on a part of a silicon substrate.
n On Insulator) structure is formed, and this three-dimensional SOI structure has a groove portion having a side wall perpendicular to the surface of the silicon substrate in a part of the silicon substrate, and an insulating layer is formed on the inner surface of the groove portion. Is formed by providing a first region provided along the sidewall perpendicular to the surface of the silicon substrate and the first region provided at the bottom of the groove in the groove. A second region connected to the first region, a gate insulating film provided so as to cover the surface of the first region, and a gate electrode layer formed in contact with the gate insulating film are formed. A region constitutes a channel forming region of the insulated gate field effect transistor, and a portion of the second region connected to the first region is a drain of the insulated gate field effect transistor ( Or a source), and the silicon substrate is connected to a predetermined potential, whereby the silicon substrate serves as a first node and the second region in the groove serves as a second node. A semiconductor memory device comprising a trench capacitor having the insulating layer as a dielectric layer interposed between the trench capacitor and the second region. 4. A method for manufacturing a semiconductor memory device, wherein a memory cell is composed of an insulated gate field effect transistor and a capacitor, wherein a surface of the silicon substrate is covered with an insulating film.
Forming a groove having sidewalls substantially perpendicular to the surface of the silicon substrate, and forming an insulating layer on the inner surface of the groove; and a first amorphous material in which the bottom of the groove is doped with impurities. Forming a silicon layer; forming an opening in a part of the insulating film covering the surface of the silicon substrate to form a seed region in which a part of the surface of the silicon substrate is exposed; Forming a second amorphous silicon layer covering the groove and extending along a sidewall perpendicular to the surface of the silicon substrate of the groove and connecting to the first amorphous silicon layer; The solid phase epitaxial growth starting from the seed region in the second and first amorphous silicon layers (Solid Phase E
Pitaxy; SPE) to obtain a single crystal silicon layer, and a gate insulating film is formed on the surface of the single crystal silicon layer,
A gate electrode layer is formed on the gate insulating film, whereby an insulated gate field effect transistor in which a portion of the single crystal silicon layer along a side wall perpendicular to the surface of the silicon substrate serves as a channel forming region. And a step of connecting the silicon substrate to a predetermined potential, using the silicon substrate as a first node, and forming a capacitor having a bottom portion of the single crystal silicon layer of the groove portion as a second node, A method of manufacturing a semiconductor memory device, comprising: 5. A semiconductor memory device comprising a memory cell composed of an insulated gate field effect transistor and a capacitor, wherein the insulated gate field effect transistor is formed on an insulating film covering a surface of a silicon substrate, , The drain (or source) of the insulated gate field effect transistor
The trench-structured capacitor is formed under the drain (source) of the silicon substrate connected to a predetermined potential as a first node, and The insulating layer formed on the inner surface of the groove provided on the substrate is used as a dielectric, and the inside of the groove is filled with the insulating layer formed on the inner surface of the groove in contact with the insulating layer. A semiconductor memory device comprising a conductor layer connected to (or a source) as a second node. 6. A method of manufacturing a semiconductor memory device, wherein a memory cell is composed of an insulated gate field effect transistor and a capacitor, wherein a surface of the silicon substrate is covered with an insulating film.
Forming a groove having a sidewall substantially perpendicular to the surface of the silicon substrate and forming an insulating layer on the inner surface of the groove; and opening a part of the insulating film covering the surface of the silicon substrate. A portion to form a seed region in which a part of the surface of the silicon substrate is exposed, a step of forming an amorphous silicon layer that covers the seed region and fills the groove portion, and a heat treatment is performed. , Solid phase epitaxial growth starting from the seed region in the amorphous silicon layer (Solid Phase Epitaxy;
SPE) to obtain a crystalline silicon layer, and by selectively introducing impurities into the crystalline silicon layer formed on the surface of the silicon substrate to fill the groove. Forming a drain (or source) region in a form having an overlap with a crystalline silicon layer, connecting the silicon substrate to a predetermined potential, and using the silicon substrate as a first node, and filling the groove portion And a step of forming a capacitor having a crystalline silicon layer as a second node.