JPH08274187A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a manufacturing method of a semiconductor device whereby a silicide process and an SAC process can be compatible with each other. CONSTITUTION: In a first process of Fig. (a), a gate 6 comprising a Poly-Si layer 4 and an insulation protective film 5 is formed on the surface of an Si substrate 1. In a second process of Fig. (b), a sidewall 9 with a different etching rate from the insulation protective film 5 is formed on the sidewall portion of the gate 6, and in a third process of Fig. (c), the insulation protetive film 5 is removed. In a fourth process of Fig. (d), high-melting-point metallic layers 11 are formed on the Si substrate 1, and these are reacted to form high-melting- point metallic silicide layers 11a (Fig. (e)). In a fifth process of Fig. (f), the unreacted high-melting-point metallic layers 11 are removed. and in a sixth process of Fig. (g), after an interlayer insulation layer 12 with an etching rate different from that of the sidewall 9 is formed on the Si substrate 1, a contact hole 13 is formed in the interlayer insulation layer 12, close to the outer side surface of the sidewall 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method applied to the manufacture of a semiconductor device such as a CMOS.

[0002]

2. Description of the Related Art One of the important techniques for achieving miniaturization of semiconductor devices is a self-alignment technique. That is, as in the case of forming a source / drain (S / D) diffusion layer by ion implantation using a gate made of, for example, polysilicon (Poly-Si) as a mask, the self-alignment technique defines the previous process. The mask shape is automatically changed to a mask so that no mask shift occurs. Therefore, this technique is advantageous in achieving miniaturization.

The above self-alignment technique can be applied to other steps of the step of forming the S / D diffusion layer. As a typical example, a so-called salicide process in which the gate and the S / D diffusion layer are simultaneously silicidized in a self-aligning manner in a silicidation process, or a so-called SAC (Self Aligned Contac
t) Process etc. In the salicide process, the resistance of the gate and the S / D diffusion layer can be lowered by silicidation, and in the SAC process, fine contacts can be formed, and misalignment of lithography at the time of contact formation can be formed in the previous step. Since these can be absorbed by a sidewall or the like, these processes are particularly effective for obtaining a high-performance and fine semiconductor device. Conventional salicide process and SAC process are
For example, it is performed as follows.

In the salicide process, as shown in FIG. 3A, a gate 53 is formed by sequentially stacking a gate oxide film 51 and a Poly-Si layer 52 on a silicon (Si) substrate 50, and then described later. LDD (Lightly-Doped dr
ain) Ion implantation for forming the diffusion layer 56 is performed on the Si substrate 50. Then, the gate 53 is formed by the CVD method.
On the Si substrate 50 so as to cover the silicon oxide (Si
O ₂ ) (not shown) is deposited, followed by RIE etchback to the sidewalls of gate 53, typically LDD.
A sidewall 54 made of SiO ₂ , which is called a spacer, is formed.

Then, the Si substrate 5 is formed by the ion implantation method.
The S / D diffusion layers 55 are formed on both sides of the sidewall 54 at 0. At this time, since ions are not implanted into the portion of the Si substrate 50 immediately below the sidewall 54, the portion finally becomes the LDD diffusion layer 56.

Next, as shown in FIG. 3B, the Si substrate 5 is covered by the CVD method or the sputtering method so as to cover the surface of the Poly-Si layer 52 and the side wall 54.
A titanium (Ti) layer 57 is formed on the surface of the aluminum oxide film 0, and then a first rapid thermal treatment (RTA) (up to 600 ° C.) is performed. As a result, the poly-Si layer 52 and the Ti layer 57, and the Si substrate 1 and the Ti layer 57 at the position of the S / D diffusion layer 55 respectively undergo a silicidation reaction, and the poly-Si layer 52, that is, the gate 53.
A C49-phase titanium silicide (TiSi ₂ ) layer 58 a is formed on the S / D diffusion layer 55. At this time, the Ti layer 57 on the surface of the sidewall 54 is not silicidated because the sidewall 54 is made of SiO ₂ .

Then, as shown in FIG. 3C, the Ti layer 57 on the surface of the sidewall 54 is selectively etched and removed by ammonia hydrogen peroxide or the like, and the second RTA (.about.
800 ° C). As a result, the TiSi ₂ layer 58a becomes
Phase change from C49 phase to C54 phase with lower resistance and lower resistance T
It becomes the iSi ₂ layer 58b.

On the other hand, in the SAC process, a gate oxide film and a Poly-Si layer are first formed on a Si substrate and then C
An SiO ₂ layer is formed on the Poly-Si layer by the VD method. Next, after forming a resist pattern on the SiO ₂ layer, by RIE using the resist pattern as a mask, as shown in FIG. 4A, the gate oxide film 61, the Poly-Si layer 62 and the SiO 2 on the Si substrate 60 are formed. _A laminated body composed of _two layers 63 is formed in the pattern of the gate 65. After forming the gate oxide film 61 in the pattern of the gate 65 by RIE using the resist pattern as a mask,
The resist pattern is removed, and then the resulting pattern of the gate oxide film 61 is used as a mask for etching.
The ly-Si layer 62 and the SiO ₂ layer 63 may be processed into the pattern of the gate 65.

Next, as shown in FIG. 4B, after removing the resist pattern 64, ion implantation for forming an LDD diffusion layer 68 and sidewalls 66 are performed in the same manner as in the step shown in FIG. 3A. Then, CVD for forming the film, etchback, and ion implantation for forming the S / D diffusion layer 67 are sequentially performed. As a result, the sidewall 66 is formed on the sidewall of the gate 65 and the Si substrate 6 is formed.
0, the S / D diffusion layers 67 are formed on both sides of the sidewall 66, and the LDD diffusion layer 68 is formed on the Si substrate 50 immediately below the sidewall 55.

Next, as shown in FIG. 4C, a silicon nitride (SiN) layer 69 is formed on the Si substrate 60 in a state of covering the gate 65 by the CVD method, and then SiO ₂ is formed on the SiN layer 69. The interlayer insulating film 70 is formed. Then, by RIE, a contact hole 71 is formed in the interlayer insulating film 70 in the vicinity of the outer surface of the sidewall 66.
During this RIE, the SiN layer 69 serves as an etching stopper. Although not shown, the SiN layer 69 immediately below the contact hole 71 is removed by RIE, and a metal wiring layer is formed on the interlayer insulating film 70 in a state of filling the contact hole 71 to form a contact. Note that Si
A SiO ₂ film may be formed before forming the N layer 69.

[0011]

However, conventionally, it has been difficult to make both the salicide process and the SAC process compatible in the manufacture of a series of semiconductor devices for the following reasons.

That is, in the SAC process, since the contact hole is formed close to the outer surface of the sidewall, in order to prevent conduction between the gate and the metal wiring layer embedded in the contact hole, the width of the sidewall is required. It is necessary to make the thickness thicker to secure the withstand voltage. Further, the width of the sidewall defines the size of the LDD diffusion layer formed immediately below the sidewall, and therefore the sidewall needs to have a predetermined thickness. On the other hand, since the side wall is formed by etching back by anisotropic etching such as RIE, the width of the side wall cannot be increased unless the gate is raised. Therefore, the conventional S
In the AC process, it is necessary to form a SiO ₂ layer on the Poly-Si layer as described above in order to raise the gate.

On the other hand, in the salicide process, the surface of the poly-Si layer of the gate needs to be exposed for silicidation. For the above reasons, it has been difficult to make both the salicide process and the SAC process compatible in the manufacture of a series of semiconductor devices.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of achieving both a salicide process and a SAC process in the manufacture of a series of semiconductor devices. .

[0015]

In the method of manufacturing a semiconductor device according to the present invention, first, in a first step, a silicon-based material layer and an insulating protective film are sequentially laminated on a surface of a substrate made of a silicon-based material, and then, The stack is patterned into gates.
Next, in a second step, a layer of an insulating material having a different etching rate from that of the insulating protective film is formed on the substrate in a state of covering the gate, and then a sidewall made of the insulating material is formed on the side wall of the gate by etching. Is formed, and the insulating protective film is removed by etching in the third step. Then, in a fourth step, a refractory metal layer or a refractory metal compound layer is formed on the base so as to cover the side wall surface and the silicon-based material layer, and then the base and the silicon-based material layer are respectively removed. A silicidation reaction is performed with the melting point metal layer or the high melting point metal compound layer. Next, in a fifth step, the refractory metal layer or refractory metal compound layer that has not been silicidated is removed. Next, in a sixth step, an interlayer insulating film is formed on the substrate by using a material having an etching rate different from that of the sidewall. At this time, the interlayer insulating film is formed so as to cover the sidewall surface and the silicon-based material layer. Then, a contact hole is formed in the interlayer insulating film in the vicinity of the outer surface of the sidewall.

In this semiconductor device manufacturing method, it is desirable to form an insulating film on the side wall of the silicon material layer between the first step and the second step.

[0017]

In the present invention, since the gate is raised by forming the insulating protective film on the silicon-based material layer, the metal wiring embedded in the gate and the contact hole is used in the etching for forming the sidewall. A sidewall having a thickness width capable of ensuring a sufficient withstand voltage is formed between the sidewall and the layer. Further, since the interlayer insulating film is formed of a material having a different etching rate from the sidewall, that is, a material having different etching resistance, the sidewall is not etched by the etching for forming the contact hole.
Therefore, in this etching, the etching is restricted on the outer surface of the sidewall, and the contact hole is formed in a self-aligned manner. Further, when the sidewall is formed of an insulating material having an etching rate different from that of the insulating protective film and the insulating protective film on the silicon-based material layer is removed by etching, the upper surface of the silicon-based material layer is exposed. In the silicidation reaction step after forming the layer or the refractory metal compound layer, the gate and the substrate are silicidized in a self-aligned manner and at the same time.

Further, if an insulating film is formed on the side wall of the silicon material layer and then a side wall is formed on the side wall of the gate, the insulating film serves as a buffer layer and stress generated between the silicon material layer and the side wall. Is alleviated.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. 1A to 1G are explanatory views showing a first embodiment of the present invention in process order. Here, a silicon (Si) substrate is used as a substrate in the present invention. First, in the first step shown in FIG. 1A, a gate oxide film 2 having a thickness of 6 nm is formed on the surface of the silicon substrate 1 by a thermal oxidation method. To do.

Then, by a CVD method, a polysilicon (Poly-Si) layer 4 serving as a silicon-based material layer of the present invention and a silicon oxide (SiO ₂ ) are formed on the Si substrate 1 via the gate oxide film 2. The insulating protection film 5 is sequentially laminated.
At this time, the film thickness of the Poly-Si layer 4 is 150 nm, and the film thickness of the insulating protective film 5 is 150 nm, for example. Next, after forming a resist pattern (not shown) on the insulating protective film 5, a laminated body including the Poly-Si layer 4 and the insulating protective film 5 is formed in the pattern of the gate 6 by etching using the resist pattern as a mask. To do. The insulating protective film 5 is formed into the pattern of the gate 6 by etching using the resist pattern as a mask, the resist pattern is removed, and then the resulting pattern of the insulating protective film 5 is used as a mask to perform poly-etching. Si layer 4 gate 6
It may be processed into a pattern. Then, the LDD diffusion layer 7 is formed on the Si substrate 1 by the ion implantation method.

After the first step, the insulating film 8 made of SiO ₂ is formed on the side wall of the Poly-Si layer 4 by, for example, the thermal oxidation method. By this thermal oxidation method, SiO ₂ is also formed on the interface between the gate oxide film 2 and the Si substrate 1 other than directly below the gate 6, and the gate oxide film 2 in that portion becomes thick.

Next, in the second step, the Si substrate 1 is formed on the Si substrate 1 through the gate oxide film 2 by the CVD method in a state of covering the gate 6, that is, in a state of covering the surfaces of the insulating film 8 and the insulating protective film 5. Form a layer of insulating material (not shown). Here, as this layer, a silicon nitride (SiN) layer having a different etching rate from the insulating protective film 5, that is, a different etching resistance is formed to have a film thickness of, for example, 300 nm. Then, by etching back by RIE, as shown in FIG. 1B, a sidewall 9 made of SiN is formed on the sidewall of the gate 6.

Next, in the third step shown in FIG. 1C, the sidewall 9 on the Si substrate 1 is formed by ion implantation.
S / D diffusion layers 10 are formed on both sides of the S / D diffusion layer 10. At this time, since ions are not implanted into the portion of the Si substrate 1 immediately below the sidewalls 9, the portion is finally LDed.
It becomes the D diffusion layer 7. Then, the insulating protective film 5 is selectively removed by wet etching using diluted hydrofluoric acid or the like. In this step, the S / D diffusion layer 1 is simultaneously formed.
The gate oxide film 2 on 0 is also removed.

Then, in the fourth step shown in FIG.
The Si substrate 1 is covered with the surface of the sidewall 9 and the top of the Poly-Si layer 4 by the CVD method or the sputtering method.
A refractory metal layer 11 made of, for example, titanium (Ti)
To form. Subsequently, as shown in FIG. 1E, a first rapid thermal treatment (RTA) (up to 600 ° C.) is performed, and S /
Each of the Si substrate 1 and the Poly-Si layer 4 at the position of the D diffusion layer 7 and the refractory metal layer 11 are silicidized. As a result, on the Poly-Si layer, that is, on the gate 6, S /
A refractory metal silicide layer 11a made of, for example, titanium silicide (TiSi ₂ ) having a C49 phase is formed on the D diffusion layer 10.
Is formed.

Then, in a fifth step shown in FIG. 1 (f), by wet etching using ammonia-hydrogen peroxide or the like,
The refractory metal layer 11 on the surface of the sidewall 9 which has not undergone the silicidation reaction is selectively removed, and then the second RTA (up to 800 ° C.) is performed. As a result, the refractory metal silicide layer 11a undergoes a phase transition from the C49 phase to a C54 phase having a lower resistance, and becomes a refractory metal silicide layer 11b having a lower resistance.

Next, in the sixth step shown in FIG. 1G, the surface of the sidewall 9 and Poly-S are formed by, for example, the CVD method.
An interlayer insulating film 12 is formed on the Si substrate 1 in a state of covering the refractory metal silicide layer 11b on the i layer 4. As a material for forming the interlayer insulating film 12, a material having an etching rate different from that of the sidewall 9 is used, and the interlayer insulating film 12 is made of SiO ₂ here.

Next, after forming a resist pattern (not shown) on the interlayer insulating film 12, the contact hole 13 is formed in the interlayer insulating film 12 in proximity to the outer surface of the sidewall 9 by etching using the resist pattern as a mask. To form. At that time, the contact hole 13 is S
It is formed so as to reach the refractory metal silicide layer 11b on the / D diffusion layer 10. Although not shown, a metal wiring layer is formed on the interlayer insulating film 12 in a state of filling the contact hole 13 to form a contact.

In the method of manufacturing a semiconductor device described above, the Poly
-Since the gate 6 is raised by forming the insulating protective film 5 on the Si layer 4, in the etching back for forming the sidewall 9, the gate 6 and the contact hole 13 are formed to be buried later. Side wall 9 having a thickness width capable of ensuring a sufficient withstand voltage with the metal wiring layer to be formed.
Can be formed.

Further, the interlayer insulating film 12 is formed on the sidewall 9
Are formed of materials having different etching rates, that is, different etching resistance,
The sidewall 9 is not etched by the etching for forming. Therefore, this etching can prevent the LDD diffusion layer 7 immediately below the sidewall 9 from being etched, and at the same time, the etching is restricted on the outer surface of the sidewall 9 to form the contact hole 13 in a self-aligned manner. can do. That is, since the SAC process can be performed, a fine semiconductor element can be formed.

Since the side wall 9 is formed of an insulating material having an etching rate different from that of the insulating protective film 5, the insulating protective film 5 on the Poly-Si layer 4 can be selectively removed by etching. And by this process,
Since the upper surface of the Poly-Si layer 4 and the surface of the Si substrate 1 on the S / D diffusion layer 10 can be exposed, the gate 6 and the S / D diffusion layer 10 are silicided in a self-aligned manner and at the same time. can do. By this silicidation, the resistance of the gate 6 and the S / D diffusion layer 10 can be lowered. Further, the sidewall 9 made of an insulating material
Thus, the gate 6 and the S / D diffusion layer 10 can be insulated from each other.

Therefore, according to the first embodiment, both the salicide process and the SAC process can be made compatible in the manufacture of a series of semiconductor devices, so that the resistance of the gate 6 and the S / D diffusion layer 10 can be reduced. A transistor (cell) can be miniaturized at the same time, and a high-performance and fine semiconductor device can be manufactured.

In the first embodiment, the Poly-S of the gate 6 is used.
Since the insulating film 8 made of SiO ₂ is formed on the side wall of the i layer 4 and the side wall 9 made of SiN is formed on the side wall of the gate 6, the insulating film 8 serves as a buffer layer.
The stress generated between the Poly-Si layer 4 and the sidewall 9 can be relaxed. Therefore, a semiconductor device having improved electrical and physical reliability can be obtained.

In the first embodiment, the case where the insulating film 8 is formed by the thermal oxidation method has been described, but the insulating film in the present invention can also be formed by another method, for example, the CVD method. When it is formed by the CVD method, an insulating film is formed on the Si substrate 1 while covering the surface of the gate 6 and via the gate insulating film 2.
When removing the insulating protective film 5 in the third step, the insulating film on the Si substrate 1 can be removed together with the gate oxide film 2.

In this embodiment, the case where the refractory metal layer of the present invention is the Ti layer has been described, but it goes without saying that another refractory metal layer such as tungsten (W) or molybdenum (Mo) may be used. is there.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (f). In this embodiment, the first
The difference from the embodiment is that the Poly-Si layer 4 is formed after the first step.
That the second step is performed without forming an insulating film on the side wall of the metal, and that the refractory metal compound layer 21 is formed in place of the refractory metal layer in the fourth step, and after the silicidation, S / D
That is, the diffusion layer 10 is formed.

That is, after performing the first step in the same manner as in the first embodiment, in the second step, the SiN layer (not shown) is formed on the Si substrate 1 by the CVD method so as to cover the surface of the gate 6. ) For example, it is formed to a film thickness of 300 nm. Further RIE
2A, sidewalls 9 made of SiN are formed on the sidewalls of the gate 6 by etching back. Next, in a third step shown in FIG. 2B, by wet etching using diluted hydrofluoric acid or the like,
The insulating protective film 5 is selectively removed.

Then, in a fourth step shown in FIG. 2C, C
By the VD method or the like, the surface of the sidewall 9 and Poly-Si
A refractory metal compound layer 21 made of, for example, titanium nitride (Ti _x N _y ) is formed on the Si substrate 1 so as to cover the layer 4 and above. And the first RTA (~ 600
℃) is performed, and the Si substrate 1 at the position of the S / D diffusion layer 7, Poly
Each of the -Si layers 4 and the refractory metal compound layer 21 are silicidized. Thereby, on the Poly-Si layer,
That is, the refractory metal silicide layer 2 made of, for example, TiSi ₂ having a C49 phase is formed on the gate 6 and the S / D diffusion layer 10.
1a (see FIG. 2D) is formed.

Next, as shown in FIG. 2E, S / D diffusion layers 10 are formed on the Si substrate 1 at both sides of the sidewalls 9 by ion implantation. At this time, since ions are not implanted into the portion of the Si substrate 1 immediately below the sidewall 9, the portion finally becomes the LDD diffusion layer 7. Then, in the same manner as the fifth step shown in FIG. 1F of the first embodiment, in the fifth step, the sidewalls 9 which have not been subjected to the silicidation reaction by wet etching are used.
The refractory metal compound layer 21a on the surface is selectively removed. Subsequently, the second RTA (up to 1000 ° C.) is performed.
As a result, the refractory metal silicide layer 21a undergoes a phase transition from the C49 phase to the C54 phase having a lower resistance, and becomes the refractory metal silicide layer 21b having a lower resistance (see FIG. 2F).

Next, the sixth embodiment shown in FIG. 1 (g) of the first embodiment is shown.
Similar to the step, after forming the interlayer insulating film 12 in the sixth step shown in FIG. 2F, the contact hole 13 is formed in the interlayer insulating film 12 in the vicinity of the outer surface of the sidewall 9. Although not shown, a metal wiring layer is formed on the interlayer insulating film 12 in a state of filling the contact hole 13 to form a contact.

Also in this semiconductor device manufacturing method, since the gate 6 is raised by forming the insulating protective film 5 on the Poly-Si layer 4, it is buried in the gate 6 and the contact hole 13. It is possible to form the sidewall 9 having a thickness width capable of ensuring a sufficient dielectric strength with the metal wiring layer. Further, since the interlayer insulating film 12 is formed of a material having an etching rate different from that of the sidewall 9,
The contact hole 13 can be formed in a self-aligned manner. Further, the sidewall 9 is formed of an insulating material having an etching rate different from that of the insulating protective film 5, and the Poly-Si layer 4 is formed.
Since the upper insulating protection film 5 is selectively removed to expose the upper surface of the Poly-Si layer 4 and the surface of the Si substrate 1 on the S / D diffusion layer 10, the self-alignment and the S and D diffusion layers 10 and the S and D diffusion layers 10 are simultaneously performed. / D
The diffusion layer 10 and the above can be silicidized.

Therefore, like the first embodiment described above,
Both the salicide process and the SAC process can be compatible in the manufacture of a series of semiconductor devices, and the resistance of the gate 6 and the S / D diffusion layer 10 can be reduced and the transistor can be miniaturized at the same time. A high-performance and fine semiconductor device can be manufactured.

In the second embodiment, the case where the insulating film is not formed on the sidewall of the Poly-Si layer 4 has been described. However, as in the above-described embodiments, it is between the first step and the second step. Of course, the step of forming the insulating film may be performed. In this embodiment, the case where the refractory metal compound layer of the present invention is the Ti _x N _y layer has been described, but it goes without saying that a refractory metal compound layer such as another W compound or Mo compound may be used.

Further, in each of the first and second embodiments, the case where each of the insulating protective film and the interlayer insulating film in the present invention is made of SiO _{2 in} which no impurity is introduced has been described. If the etching rate is different, an insulating material containing impurities, such as P
An insulating protective film and an interlayer insulating film can be formed with SG or BPSG.

In each of the first and second embodiments, the case where the interlayer insulating film 12 is formed on the Si substrate 1 has been described, but prior to the formation of the interlayer insulating film 12, the interlayer insulating film 12 is formed. It is also possible to form an insulating film, such as a SiN film, having a sufficient etching selection ratio on the Si substrate 1. In this case, since the insulating film serves as an etching stopper during the etching for forming the contact hole 13, it is necessary to perform overetching sufficiently in consideration of the variation in the film thickness. Refractory metal silicide layer 11 on 10
b or the refractory metal silicide layer 21b can be protected more reliably. Also, S for making contact
The insulating film such as the iN film is removed after the interlayer insulating film 12 is etched.

[0045]

As described above, according to the method of manufacturing a semiconductor device of the present invention, since the insulating protective film is formed on the silicon-based material layer to raise the gate, the gate for etching to form the sidewall is not formed. It is possible to form a sidewall having a thickness width capable of ensuring a sufficient withstand voltage between the metal wiring layer and the metal wiring layer embedded in the contact hole. Further, since the interlayer insulating film is formed of a material having an etching rate different from that of the sidewall, etching is restricted by the sidewall and the contact hole can be formed in a self-aligned manner. Further, since the side wall is formed of an insulating material having an etching rate different from that of the insulating protective film, and the insulating protective film on the silicon-based material layer is removed by etching to expose the upper surface of the silicon-based material layer, a refractory metal is used. In the silicidation reaction step after the formation of the layer or the refractory metal compound layer, the gate and the substrate can be silicidated in a self-aligned manner and at the same time. Therefore, according to the present invention, both the salicide process and the SAC process can be compatible in manufacturing a series of semiconductor devices. By this, the resistance of the S / D diffusion layer formed on the gate and the base and the miniaturization of the transistor can be achieved at the same time, so that a high-performance and fine semiconductor device can be manufactured.

If an insulating film is formed on the side wall of the silicon material layer and then a side wall is formed on the side wall of the gate, the insulating film serves as a buffer layer and stress generated between the silicon material layer and the side wall. Is alleviated,
A semiconductor device with improved electrical, electrical, and physical reliability can be manufactured.

[Brief description of drawings]

1A to 1G are explanatory views showing a first embodiment of the present invention in process order.

2A to 2F are explanatory views showing a second embodiment of the present invention in process order.

3A to 3C are explanatory views showing a conventional salicide process in the order of steps.

4A to 4C are explanatory views showing a conventional SAC process in the order of steps.

[Explanation of symbols]

1 Si Substrate (Base) 4 Poly-Si Layer (Silicon Material Layer) 5 Insulation Protective Film 6 Gate 8 Insulation Film 9 Sidewall 10 Refractory Metal Layer 10a, 10b, 21a, 21b Refractory Metal Silicide Layer 12 Interlayer Insulation Film 13 Contact hole 21 Refractory metal compound layer

Claims (2)

[Claims] 1. A first step of sequentially stacking a silicon-based material layer and an insulating protective film on a surface of a base material made of a silicon-based material, and then patterning the stacked body into a gate, and the step of covering the gate with the first step. After forming a layer of an insulating material having a different etching rate from the insulating protective film on the substrate,
A second step of forming a side wall made of the insulating material on the side wall of the gate by etching, a third step of removing the insulating protective film by etching, and covering the side wall surface and the silicon-based material layer. A refractory metal layer or a refractory metal compound layer is formed on the base body in the state, and then the refractory metal layer or the refractory metal compound layer and the refractory metal layer or the refractory metal compound layer are silicified. A fourth step, a fifth step of removing the refractory metal layer or the refractory metal compound layer that has not been subjected to the silicidation reaction in the fourth step, and the step of covering the sidewall surface and the silicon-based material layer. After forming an interlayer insulating film on the substrate by using a material having an etching rate different from that of the sidewall, the sidewall is formed on the interlayer insulating film. And a sixth step of forming a contact hole in the vicinity of the outer surface of the roll. 2. Between the first step and the second step,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an insulating film on the side wall of the silicon-based material layer.