JPH08273361A - Multivalue static random access memory cell circuit - Google Patents

Abstract

PURPOSE: To provide a static random access memory(SRAM) comprising a semiconductor integrated circuit in which high integration, low cost and low power consumption are realized by configuring a memory cell circuit storing multivalue signal of four values or more thereby decreasing the number of circuit elements and signal lines per bit. CONSTITUTION: The multivalue static random access memory comprises a latch circuit 13 including multivalue (four values or more) inverter circuits 11, 12 combining a multipower supply and MOSFETs having different threshold voltage, and a transmission gate 16 including an N type MOSFET 14 and a P type MOSFET 15 connected in parallel, wherein the transmission gate 16 has one end connected with the multivalue latch circuit 13 and the other end connected with a bit line 17. The transmission gate is controlled through a first word line 18 and a second word line 19 delivering a inverted signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (hereinafter referred to as SRAM) using a semiconductor integrated circuit.
Abbreviated), the present invention relates to a circuit configuration of a memory cell in which a multilevel signal having four or more values is stored in the memory cell to increase the integration degree per bit.

[0002]

2. Description of the Related Art A conventional SRAM memory cell circuit outputs 1, 0 as shown in FIG. 4 which is the most commonly used example or as a rare example as shown in FIG. 5 in Japanese Patent Laid-Open No. 4-298893. A latch circuit composed of two inverter circuits stores a binary signal of 1 or 0.

[0003]

In the above-mentioned conventional memory cell configuration, 6 transistors and 3 signal lines are required for each bit, which is a bit compared with a dynamic random access memory (DRAM). There was a problem that the degree of accumulation per hit was low.

Further, since the number of circuit elements and the number of wirings per bit including the peripheral circuit are large, there is a problem that the power consumption per bit is large.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide an SRAM memory cell having a high degree of integration per bit, that is, a low cost per bit, and an SRAM. The purpose is to

Another object of the present invention is to provide an SRAM with low power consumption by reducing the number of circuit elements and the number of wirings per bit.

[0007]

A multilevel static random access memory cell circuit according to the present invention comprises: a) a static random access memory; and b) a plurality of power sources of 2M different potential levels, where M is a positive integer of 2 or more. And C) a group of P-type insulated gate field effect transistors having different threshold voltages of M kinds, and d) a group of N-type insulated gate field effect transistors of different threshold voltages of M kinds, and e) the 2M pieces. From a first inverter circuit of 2M value and a second inverter circuit of 2M value composed of a plurality of power supplies, M types of P-type insulated gate field effect transistors, and M types of N-type insulated gate field effect transistors Becomes
The output terminal of the first 2M value inverter circuit is connected to the input terminal of the second 2M value inverter circuit, and the output terminal of the second 2M value inverter circuit is connected to the input terminal of the first 2M value inverter circuit. And a f-type insulated gate field-effect transistor and a P-type insulated gate field-effect transistor.
Type insulated gate field effect transistor comprising a transmission gate formed by connecting source electrodes or drain electrodes to each other, g) an input terminal of the first 2M-valued inverter circuit is connected to a second terminal of the transmission gate. Connected, a first terminal of the transmission gate is connected to a bit line as a memory, a gate electrode of the N-type insulated gate field effect transistor is connected to a first word line as a memory, and the P-type insulated gate is connected. The gate electrode of the field effect transistor is connected to a second word line having an inverted signal relationship with the first word line.

[0008]

According to the above-mentioned structure of the present invention, a 2M-value latch circuit is used, whereas the same number as the conventional circuit in the case where the transmission gate, the word line and the bit line are binary is used. The number of elements and the number of signal lines are reduced, and the degree of integration is increased.

Further, since the number of circuit elements per bit and the number of signal lines are reduced, the power consumption per bit is reduced.

[0010]

The details of the present invention will be described below with reference to Examples. FIG. 1 is a memory cell circuit diagram showing an embodiment of the present invention in the case of four values. In FIG. 1, 11 and 12 are four-valued inverter circuits, the output terminal of the four-valued inverter circuit 11 is connected to the input terminal of the four-valued inverter circuit 12, and the output terminal of the four-valued inverter circuit 12 is the four-valued inverter circuit 11. A four-valued latch circuit, which is connected to the input terminal and surrounded by a broken line 13 by the four-valued inverter circuits 11 and 12, is configured. 14 is an N-type MOSFET and 15 is a P-type MOS
It is a FET. N-type MOSFET 14 and P-type MOSFE
T15 is connected in parallel and constitutes a transmission gate surrounded by a broken line 16. The first terminal of the transmission gate 16 is connected to the input terminal of the four-valued inverter circuit 11 in the four-valued latch circuit 13, and the second terminal of the transmission gate 16 is connected to the bit line 17. Reference numeral 18 is a first word line, and 19 is a second word line having an inverted signal relationship with the signal of the first word line. The gate electrode of the N-type MOSFET 14 is connected to the word line 18, and the gate electrode of the P-type MOSFET is connected to the word line 19. The circuit surrounded by the broken line 10 constitutes a memory cell circuit.

FIG. 2 is a circuit diagram showing an embodiment of a four-valued inverter circuit used in the present invention and a diagram showing a truth table. Figure 2
(A) Positive first power source + VDD1 and positive second power source
+ VDD2 and first negative power supply-VSS1 and second negative power supply-VSS2
There are four types of power supplies. 21 is the threshold voltage VTP
It is a P-type MOSFET having 1. Reference numeral 23 is a P-type MOSFET having a threshold voltage VTP2 higher than VTP1. 22 is the threshold voltage VTN1
It is an N-type MOSFET having. 24 is an N-type MOSFET having a threshold voltage VTN2 higher than VTN1. 25 and 26 are diodes.
The source electrode of the P-type MOSFET 21 is connected to + VDD1, the drain electrode is connected to the positive electrode of the diode 25,
The negative electrode of the diode 25 is connected to the output terminal 28. The source electrode of the N-type MOSFET 22 is connected to -VSS1, the drain electrode is connected to the negative electrode of the diode 26, and the positive electrode of the diode 26 is connected to the output terminal 28. The source electrode of the P-type MOSFET 23 is connected to + VDD2, and the drain electrode is connected to the output terminal 28. The source electrode of the N-type MOSFET 24 is connected to -VSS2, and the drain electrode is connected to the output terminal 28.
The gate electrodes of the MOSFETs 21, 22, 23, 24 are connected to each other and to the input terminal 27. Now, in the threshold voltage VTP1 of the P-type MOSFET 21, there is a relation of VDD1 + VSS1>VTP1> 0 as + VDD2> + VDD1>0>-VSS1> -VSS2, and the gate potential of the P-type MOSFET 21 is-.
Both VSS2 and -VSS1 turn on (ON), + VDD2, + V
Both are turned off by DD1. P-type MOSFET 23
Threshold voltage VTP2 is set to a high value, and there is a relation of VDD2 + VSS2>VTP2> VDD2 + VSS1. That is, the P-type MOSFET 23 turns on when the gate potential is −VSS2, but does not turn on at −VSS1, and remains off. As a matter of course, it is off at + VDD2 and + VDD1. In the threshold voltage VTN1 of the N-type MOSFET 22, there is a relation of VDD1 + VSS1>VTN1> 0, and the gate potential of the N-type MOSFET 22 is +.
Both are turned on at VDD2 and + VDD1, and turned off at -VSS2 and -VSS1. In the threshold voltage VTN2 of the N-type MOSFET 24, there is a relation of VDD2 + VSS2>VTN2> VDD1 + VSS2. Therefore, the N-type MOSFET 24 turns on when the gate potential is + VDD2, but does not turn on at + VDD1 and remains off. And of course -VSS2, -VS
It is off in S1. From the above, when the potential of + VDD2 is applied to the input terminal 27, the N-type MOSFET 22 and the N-type MOSFE
T24 turns on, and -VSS1 from N-type MOSFET 22
Further, -VSS2 is supplied from the N-type MOSFET 24 to the output terminal 28, respectively, but since the diode 26 is provided, the output terminal 28 has the potential of -VSS2. Also, input terminal 27 + VD
The N-type MOSFET 22 turns on when the potential of D1 is applied.
Therefore, the output terminal 28 has a potential of -VSS1. Further, when the potential of −VSS1 is applied to the input terminal 27, only the P-type MOSFET 21 is turned on, so that the output terminal 28 is +
It becomes the potential of VDD1. When the potential of -VSS2 is applied to the input terminal 27, the P-type MOSFET 21 and the P-type MOSFET 2 are
3 is turned on, and + VDD1 is output from the P-type MOSFET 21 and + VDD2 is output from the P-type MOSFET 23, respectively.
8 is supplied, but there is a diode 25, so output terminal 2
8 becomes the potential of + VDD2. FIG. 2B shows a truth table in which the above is organized. In general, there are no restrictions as follows, but if VDD1 = VSS1 = E1 VDD2 = VSS2 = E2 for the sake of clarity, + VDD1 = + E1 -VSS1 = -E1 + VDD2 = + E2 -VSS2 = -E2 Therefore, if FIG. 2B is rewritten based on this condition, FIG. 2C is obtained. Looking at the truth table of FIG.
It can be seen that the circuit of (a) is a four-valued inverter circuit.

From the above, the four-value latch circuit 13 in which the four-value inverter circuits 11 and 12 are combined in FIG. 1 stabilizes + VDD2, + VDD1, -VSS1, -VSS2 or + E2, + E1, -E1, -E2. You can see that it is a circuit to store.

Now, the threshold voltage of the N-type MOSFET 14 in the transmission gate 16 is VTN1.
If the threshold voltage of the P-type MOSFET 15 is VTP1, the word line 18 has -VSS2 (-E2),
When the word line 19 is + VDD2 (+ E2), the transmission gate 16 is off (OFF) and the 4-value latch circuit 13 has one of four values (+ E2, + E1, -E1, -E2). Signal is held. Word line 18 is + VDD2 (+ E
2) When the word line 19 is -VSS2 (-E2), the transmission gate 16 is turned on (ON) and the four values (+ E2, + E1, -E1, -E) stored in the four-value latch circuit 13 are stored.
In any case of 2), the signal can be accurately read to the bit line 17, and any four-valued signal can be written from the bit line 17 to the four-valued latch circuit 13.

From the above, in the circuit configuration of FIG. 1 and FIG.
It can be seen that a value static random access memory circuit can be constructed. At this time, according to the configuration of FIG. 1, a 2M-value latch circuit is used, whereas the same number as the conventional circuit in the case where the transmission gate, the word line, and the bit line are binary is used. Therefore, the number of circuit elements per bit and The number of signal lines is reduced and the degree of integration is increased. Moreover, since the number of circuit elements per bit and the number of signal lines are reduced, the power consumption per bit is reduced.

In the above, the case of four values has been described, but the present invention is not limited to four values. Next, FIG. 3 shows an embodiment of a 6-valued inverter circuit.

In FIG. 3A, the positive first power source + VDD1
And a positive second power supply + VDD2, a positive third power supply + VDD3, a negative first power supply -VSS1, a negative second power supply -VSS2 and a negative third
Power Supply-There are 6 types of power supply, VSS3. Reference numeral 31 is a P-type MOSFET having a threshold voltage VTP1. 33
Is a P-type MOSFET having a threshold voltage VTP2 higher than VTP1. 35 has a higher threshold voltage VTP3 than VTP1 and VTP2 P
Type MOSFET. 32 is the threshold voltage VTN
It is an N-type MOSFET having 1. 34 is an N-type MOSFET having a threshold voltage VTN2 higher than VTN1. 36 is an N-type MOS having a threshold voltage VTN3 higher than those of VTN1 and VTN2.
It is a FET. The source electrode of the 2P type MOSFET 31 is
It is connected to + VDD1, the source electrode of the N-type MOSFET 32 is connected to -VSS1, the source electrode of the P-type MOSFET 33 is connected to + VDD2, the source electrode of the N-type MOSFET 34 is connected to -VSS2, and the source of the P-type MOSFET 35. The electrode is connected to + VDD3, and the source electrode of the N-type MOSFET 36 is connected to -VSS3. MOSFET3
The gate electrodes of 1, 32, 33, 34, 35 and 36 are connected to each other and to the input terminal 37. Further, the drain electrodes of the MOSFETs 31, 32, 33, 34, 35, 36 are connected to each other via a diode and are also connected to the output terminal 38. + VDD2, + VDD1, -VS
S1, -VSS2 and threshold voltage VTP1 of P-type MOSFET 31, threshold voltage VTP2 of P-type MOSFET 33, threshold voltage VT of N-type MOSFET 32.
Threshold voltage VTN2 of N1 and N-type MOSFET 34
The relationship of MO is in the four-valued inverter circuit of FIG.
This is the same as the relationship between the SFETs 21, 23, 22 and 24.
Now, in the newly added threshold voltage VTP3 of the P-type MOSFET 35, there is a relation of VDD3 + VSS3>VTP3> VDD3 + VSS2 as + VDD3> + VDD2> + VDD1>0>-VSS1>-VSS2> -VSS3. The gate potential of the MOSFET 35 is −
It turns on at VSS3, but does not turn on at -VSS2 and -VSS1 and remains off. Also naturally + VDD3, + VD
It is off at D2 and + VDD1. In the threshold voltage VTN3 of the N-type MOSFET 36, there is a relation of VDD3 + VSS3>VTN3> VDD2 + VSS3, and the gate potential of the N-type MOSFET 36 is +.
It turns on at VDD3, but does not turn on at + VDD2 and + VDD1 and remains off. And of course -VSS3, -VS
It is off at S2 and -VSS1. With the above configuration, the relationship between the potential of the input terminal and the potential of the output terminal is as shown in the truth table of FIG. 3 (b) for the same reason as in the four-valued inverter circuit of FIG. = (VSS1 = E1 VDD2 = VSS2 = E2 VDD3 = VSS3 = E3) FIG. 3 (b) becomes like FIG. 3 (c). FIG.
It can be seen from the truth table of FIG. 3C that the circuit of FIG. 3A is a six-valued inverter circuit.

As described above, a 6-valued inverter circuit can also be formed, and by using this 6-valued inverter circuit, a 6-valued latch circuit can be formed and a 6-valued static random access memory circuit can be formed. Further, if expanded in the same manner, eight or more values can be similarly configured. Generally, the larger the multi-valued value, the higher the degree of integration per bit.

In FIG. 1, a 4-valued (multi-valued) signal is output to the bit line 17, but there is also a method of treating the circuit following the bit line as 4-valued (multi-valued), or soon. 1,
There is also a method of converting into a binary value of 0 and processing. Further, the peripheral circuit can be configured with multiple values or with two values.

Since the present invention uses two word lines and four power supply lines in FIGS. 1 and 2, it is more effective in a manufacturing process using metal multi-layer wiring.

[0020]

As described above, according to the present invention, although a multi-value (2M value) signal is stored in a memory cell, the transmission gate, the word line and the bit line have a binary value. Since the number of circuits is the same, the number of circuit elements per bit and the number of signal lines are reduced, which has the effect of increasing the degree of integration.

Therefore, it is possible to construct a larger memory capacity in the same process dimension and reduce the cost per bit.

Further, since the number of circuit elements per bit and the number of signal lines are reduced, the power consumption per bit can be reduced.

When used in combination with a multi-valued circuit for a function other than the memory, the entire integrated circuit can be configured with the multi-valued circuit as it is, and the conversion circuit between the binary and the multi-valued can be saved, thus eliminating waste and functioning. A synergistic effect of up can be expected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory cell showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a four-valued inverter circuit used in a four-valued latch circuit used in the memory cell of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a 6-valued inverter circuit used in a 6-valued latch circuit used in the memory cell of the present invention.

FIG. 4 is a circuit diagram showing a typical configuration example of a conventional static random access memory cell.

FIG. 5 is a circuit diagram showing another configuration example of a conventional static random access memory cell.

[Explanation of symbols]

10 ... Memory cell circuit 11, 12 ... 4-valued inverter circuit 13 ... 4-valued latch circuit 14, 22, 24, 32, 34, 36 ... N-type MOS
FETs 15, 21, 23, 31, 33, 35 ... P-type MOS
FET 16 ... Transmission gate 17 ... Bit line 18 ... Word line 19 ... Inverted signal word line + VDD3, + VDD2, + VDD1 ... Positive power supply potential -VSS1, -VSS2,- VSS3 ・ ・ ・ Negative power supply potential

Claims (3)

[Claims] 1. A) In a static random access memory, b) a plurality of power supplies of 2M different potential levels, where M is a positive integer of 2 or more, and C) P-type insulated gate electric field of M different threshold voltages. An effective transistor group, and d) an N-type insulated gate field effect transistor group having M different threshold voltages, and e) a plurality of 2M power sources and M types of P-type insulated gate field effect transistors. And a 2M-valued first inverter circuit and a 2M-valued second inverter circuit configured by M kinds of N-type insulated gate field effect transistors,
The output terminal of the first 2M value inverter circuit is connected to the input terminal of the second 2M value inverter circuit, and the output terminal of the second 2M value inverter circuit is connected to the input terminal of the first 2M value inverter circuit. And a f-type insulated gate field-effect transistor and a P-type insulated gate field-effect transistor.
Type insulated gate field effect transistor comprising a transmission gate formed by connecting source electrodes or drain electrodes to each other, g) an input terminal of the first 2M-valued inverter circuit is connected to a second terminal of the transmission gate. Connected, a first terminal of the transmission gate is connected to a bit line as a memory, a gate electrode of the N-type insulated gate field effect transistor is connected to a first word line as a memory, and the P-type insulated gate is connected. A multi-valued static random access memory cell circuit, wherein a gate electrode of the field effect transistor is connected to a second word line having an inverted signal relationship with the first word line. 2. The first and second M-valued inverter circuits according to claim 1, wherein the 2M power supplies are the Kth (1 ≦ K ≦ M) power supplies counted from the higher potential side, The threshold voltage is connected to the source electrode of the P-type insulated gate field-effect transistor of the Kth from the highest absolute value of M different threshold voltages, and the 2M power sources are counted from the lowest potential to K.
The th power source is connected to the source electrodes of the Kth N-type insulated gate field effect transistors from the highest absolute value of the M different threshold voltages, and the Pth and N type insulated gate field effect transistors are connected. A multi-valued structure in which gate electrodes are connected to each other as input terminals, and drain electrodes of the P-type and N-type insulated gate field effect transistors are connected to each other as output terminals via diodes. Static random access memory cell circuit. 3. The first and second word lines according to claim 1 are 2
A multi-level static random access memory cell circuit, characterized in that in a semiconductor integrated circuit device using more than one layer of metal wiring, the metal wirings are of different layers.