JPH08273305A - Digital video signal recording device and reproducing device - Google Patents

Abstract

PURPOSE: To deal with the case in which a digital compressed video signal is transmitted at arbitrary intervals by providing a recorded and reproduced signal processing circuit and the like as a recording means for adding and recording discriminating information. CONSTITUTION: At the time of recording, an input-output circuit 107 detects recorded packet data and outputs it to a recorded and reproduced signal processing circuit 102. The recorded and reproduced signal processing circuit 102 determines the number of a packet to be recorded in one track in accordance with a recording mode determined in a control circuit 104 to produce an error correction code, ID information, a subcode and the like and those are recorded into a tape 111 through a rotary head 100 by producing a recording signal. At the time of reproduction, reproducing operation is performed in an arbitrary reproducing mode at first, and the ID information is detected by the recorded and reproduced signal processing circuit 102 and the detection of a synchronous signal, the correction of error detection and the like are performed by a reproducing signal from the rotary head 100 to reproduce data, subcode and the like and output them to the input-output circuit 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording / reproducing apparatus for recording / reproducing a digital video signal,
In particular, the present invention relates to a recording device and a reproducing device for recording / reproducing a digital compressed video signal.

[0002]

2. Description of the Related Art A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape using a rotary head is disclosed in Japanese Patent Laid-Open No. 174496/1993.

[0003]

However, no consideration is given to recording of signals transmitted in packet format at arbitrary intervals rather than at a constant rate.

An object of the present invention is to provide a digital signal recording apparatus and a digital signal reproducing apparatus which can cope with transmission even at arbitrary intervals.

[0005]

The above object is to divide a digital signal in a packet format of n bytes into a predetermined number of bytes, add a synchronization signal, a control signal and an error detection / correction code into a block format, and set a predetermined number. In a digital signal recording device for forming a digital signal recording area by the individual blocks and recording on a magnetic recording medium, identification information for identifying the type of the signal recorded in the block is added as a control signal in block units. This can be achieved by identifying the identification information at the time of reproduction and outputting the packet format digital signal recorded in the block.

[0006]

According to the identification information, a block in which a packet-type digital signal is recorded and a block in which other signals are recorded or a block in which a valid signal is not recorded are identified and recorded. Since the end of the existing area can be identified, even if the amount and arrangement of the signals recorded during recording are changed, it is possible to respond to the reproduction.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a digital signal recording / reproducing apparatus. Although FIG. 1 shows a device for both recording and reproduction, it goes without saying that recording and reproduction are independent. Reference numeral 100 is a rotary head, 101 is a capstan, 102 is a recording / reproducing signal processing circuit for generating a recording signal for recording and demodulating a reproducing signal for reproducing, and 104 is for controlling a recording / reproducing mode, for example, a microprocessor. Control circuit, such as
Reference numeral 105 denotes a timing generation circuit that generates a timing signal that serves as a reference for the rotation of the rotary head 100, and 106 denotes a servo circuit that controls the feed speed of the rotary head and the tape.
Reference numeral 07 is an input / output circuit that inputs a recording signal or outputs a reproduction signal, 109 is a timing control circuit that controls the timing at the time of recording, 110 is an oscillation circuit that generates a reference clock, 111 is a tape, and 112 is an analog video signal. It is a recording / reproducing circuit.

At the time of recording, packet-type recording data is input from the input / output terminal 108 at arbitrary time intervals. A part of the packet data input from the input / output terminal 108 is input to the control circuit 104 via the input / output circuit 107. The control circuit 104 detects the type of packet data, the maximum transmission rate, etc. from the information added to the packet data or the information sent separately from the packet data, determines the recording mode based on the detection result, and outputs the recording / reproducing signal. The operation modes of the processing circuit 102 and the servo circuit 106 are set. The input / output circuit 107 detects the packet data to be recorded and outputs it to the recording / reproducing signal processing circuit 102. In the recording / reproducing signal processing circuit 102, the control circuit 1
The number of packets to be recorded on one track is determined according to the recording mode determined in 04, and the error correction code, ID information,
A subcode or the like is generated, and a recording signal is generated and recorded on the tape 111 by the rotary head 100.

At the time of reproduction, first, reproduction operation is performed in an arbitrary reproduction mode, and the recording / reproduction signal processing circuit 102 detects ID information. Then, the control circuit 104 determines in which mode the recording is performed, and the operation modes of the recording / reproducing signal processing circuit 104 and the servo circuit 106 are reset and reproduction is performed.
In the recording / reproducing signal processing circuit 104, the synchronizing signal is detected, the error is detected and corrected from the reproducing signal reproduced by the rotary head 100, and the data, subcode, etc. are reproduced and output to the input / output circuit 107. The input / output circuit 107 outputs reproduction data from the input / output terminal 108 with reference to the timing generated by the timing generation circuit 105.

At the time of recording, the timing control circuit 109 controls the operation timing of the recording / reproducing apparatus with the rate of the recording data input from the input / output terminal 108 as a reference, and at the time of reproduction, the clock oscillated by the oscillation circuit 110 is used as an operation reference. To work as.

When recording / reproducing an analog video signal, the analog video signal input from the input terminal 113 is recorded in the tape 111 by the rotary head 100 by a predetermined process in the analog recording / reproducing circuit 112 during recording. At the time of reproduction, the video signal reproduced by the rotary head 111 is output from the output terminal 114 after the analog recording / reproducing circuit 112 performs a predetermined process. In this case, although not shown, the servo circuit 106 is controlled based on the frame period of the analog video signal. The analog recording head may be used also as the digital recording head, or may be provided independently.

FIG. 2 shows a recording pattern for one track. Reference numeral 3 is an additional information recording area such as an audio signal, 7 is a data recording area for recording a digital compressed video signal, 12 is a subcode recording area for recording subcodes such as time information and program information, and 2, 6 and 11 are respectively Of the recording areas, 4, 8 and 13 are postambles of the respective recording areas, 5 and 9 are gaps between the respective recording areas, and 1 and 14 are margins of track ends.
In this way, by providing the postamble, the preamble, and the gap in each recording area, it is possible to perform postrecording in each area independently. Of course, digital signals other than the digital compressed video signal and audio signal may be recorded in the recording areas 3 and 7. Also, area 7
A digital compressed audio signal may be recorded together with the digital compressed video signal.

FIG. 3 shows a block configuration of each area. Figure 2
(A) is a block configuration of the additional information recording area 3 and the data recording area 7. Reference numeral 20 is a synchronization signal, 21 is ID information, 22 is data, and 23 is a parity (C1 parity) for the first error detection and correction. For example, sync signal 2
0 is 2 bytes, ID information 21 is 3 bytes, data 22 is 99 bytes, parity 23 is 8 bytes, and 1 block is 112 bytes. Figure 2
(B) is a block configuration of the subcode recording area 12. In the block of the subcode recording area, the synchronization signal 20
And the ID information 21 are the same as those in FIG.
Is composed of 19 bytes and the parity 23 is composed of 4 bytes, and one block is 28 which is 1/4 of the block in FIG.
It consists of bytes. In this way, the number of bytes in one block is set to be an integer ratio, and the sync signal 11 and the ID information 12 are configured to be the same in all areas, so that a block for recording and a sync signal for recording are generated. ,
Processing such as detection of ID information can be processed by the same circuit.

FIG. 4 shows the structure of the ID information 21. 31
Is a sequence number, 32 is a track address, and 33 is 1
Block address in track, 35 is sequence number 31, track address 32 and block address 33
It is the parity for detecting the error. The block address 33 is an address for identifying a block in each recording area. For example, in the data recording area 7, 0 to
335, 0 to 13 in the additional information recording area 3, and 0 to 15 in the subcode recording area 12. Track address 3
Reference numeral 2 is an address for identifying a track. For example, 6 tracks can be identified by changing the address in units of 1 track or 2 tracks and setting the address to 0-5 or 0-2. Sequence number 31 is
For example, 72 tracks can be identified by changing them in units of 6 tracks identified by the track address 32 and setting 0 to 11. If the track address is synchronized with the cycle of the second error correction code described later and the sequence number is synchronized with the recording cycle of the variable speed reproduction data described later, the processing at the time of recording and the identification at the time of reproduction can be facilitated. You can

FIG. 5 shows the structure of one track of data in the data recording area 7. The sync signal 20 and the ID information 21 are omitted. The data recording area 7 is composed of, for example, 336 blocks, and the first 306
The data 41 is recorded in the block, and the second error correction code (C2 parity) 43 is recorded in the next 30 blocks.

The C2 parity 43 divides data of 306 blocks × 6 tracks into 18 in units of 6 tracks, and 10 blocks of C2 in each 102 blocks.
Add parity. As the error correction code, for example, a Reed Solomon code may be used.

Each block of 99-byte data is composed of a 3-byte header 44 and 96-byte data 41. FIG. 6 shows the structure of the header 44 of the data recording area 7. The header 44 is composed of format information 31, additional information 32, and block information 33.

FIG. 7 shows the structure of the format information 31. The format information 31 is information about the recording format, and for example, 6 bytes of 6 blocks make up one piece of information. Then, this information is recorded multiple times to improve the detection capability during reproduction.
The 6 blocks of data are composed of, for example, 8 types of data of ID-1 to ID-8.

ID-1 defines the recording format of the data recording area 7. That is, it is possible to support a plurality of types of formats by changing the value of ID-1. For example, when recording a packet-format digital compressed video signal, ID-1 is set to "1".

ID-2 defines the recording mode, that is, the maximum recording capacity. In this embodiment, when two-channel recording is performed at a rotation speed of 1800 rpm using a four-head rotary head, data of approximately 25 Mbps can be recorded. Here, if recording is performed once every two times, the recording capacity becomes about 12.5 Mbps. If the recording is performed once every four times, the recording capacity is about 6.25 Mbps.
Becomes In this case, tape feed speed is 1/2 or 1
When set to / 4, the track patterns on the tape are almost the same. Similarly, the maximum recording capacity is 1 at 25 Mbps.
/ N is possible. At the time of recording, the transmission rate of the recording data is identified, the optimum recording mode is set, and recording is performed. Then, the recording mode is recorded in ID-2. For example, at 25 Mbps, "1",
When it is 12.5 Mbps, it is "2", and when it is 6.25 Mbps, it is "3".

ID-3 defines the time axis compression mode, that is, the time axis compression rate at the time of recording. This corresponds to a system in which a digital signal is compressed on the time axis and transmitted in a short time, and the digital signal is recorded and then expanded on the time axis for reproduction. For example, it is set to "1" when there is no time axis compression, "2" when the time axis compression rate is double, and "3" when the time axis compression rate is four times.

ID-4 defines the number of channels of data to be recorded simultaneously. For example, in recording mode 1,
Data of 12.5 Mbps can be recorded on two channels.

ID-5 defines the number of packets to be recorded on one track, and ID-6 defines the packet length of the packets to be recorded. By controlling the amount of data recorded on one track in units of packets and recording the number of recorded data,
It can support any transmission rate. It should be noted that the control may be performed for each track or a plurality of tracks.
In addition, by recording the packet length, it is possible to handle a packet having an arbitrary length.

As described above, by controlling the recording mode and the amount of data to be recorded in one track according to the transmission rate of the data to be recorded, it is possible to perform efficient recording with a simple recording / reproducing process. At the time of reproduction, first, the ID data 34 may be detected to identify the recording mode and the like, and the reproduction processing circuit may be set to that mode for reproduction.

If the address of the last block is recorded in ID-5 and the position of the last data is recorded in ID-6 without associating the packet with the block, the amount of data to be recorded is controlled in byte units. It is also possible.

ID-7 is record information of variable speed reproduction data. As shown in FIG. 8, by recording the data 50 dedicated to variable speed reproduction at a predetermined position corresponding to the miracle of the head during variable speed reproduction, it is possible to reproduce a good reproduced image even during variable speed reproduction. it can. Therefore, whether or not this data is recorded, or what kind of data is recorded, is recorded in ID-7, and by identifying it at the time of reproduction, it is easy to support variable speed reproduction. Can be

FIG. 9 shows the structure of the additional information 32. As the additional information 32, for example, 6 bytes of 6 blocks form one piece of information, the first 1 byte is an item code indicating the type of information, and the remaining 5 bytes are data, so that various types of data can be stored. Can be recorded.
For example, information such as recording time and the type of recording signal are recorded. Detailed information relating to the variable speed reproduction data may be recorded here in association with ID-7.

FIG. 10 shows a data recording area 4 for a digital compressed video signal transmitted in a packet format of 188 bytes.
3 is an example of the configuration of a block when recording in No. 1. In this case, 4-byte time information 25 is added to make 192 bytes, and one packet is recorded in two blocks. Data of one packet is recorded in two blocks, that is, in correspondence with one code sequence of C1, so that when a block error cannot be corrected due to a burst error due to a dropout on the tape, the error is a unit of transmission. Does not span multiple packets.

FIG. 11 shows the block configuration when the length of the packet 71 is 140 bytes. At this time, 2
Each packet 71 is recorded in 3 blocks.

FIG. 12 shows another configuration example of the packet shown in FIG. 10 or 11. The packet is composed of, for example, time information 25 of 3 bytes and control information 72 related to the packet of 1 byte by packet data 71 of 188 bytes or 140 bytes. Packet data 7
When the number of 1's is smaller than this, for example, in the case of 130 bytes, dummy data may be added and recorded, or the area of control information may be increased.

The time information 25 is information on the time when the packet was transmitted. That is, the time when a packet (the beginning of) is transmitted or the interval between packets is counted by the reference clock, the count value is recorded together with the packet data, and the interval between packets is reproduced based on that information during reproduction. By setting, it is possible to output data in the same form as when it was transmitted.

Thus, the ratio of the number of bytes in one packet to the number of bytes in the recording area of one block is a simple integer ratio n: m.
If m packets are recorded in n blocks as shown by, it is possible to efficiently record even if the packet length is different from the recording area of one block. n
And m are values smaller than the number of bytes of one packet and the number of bytes of the recording area of one block, respectively, and the processing can be facilitated if they can be represented by integers of about 10 or less. It should be noted that even if the length of one packet is longer than the recording area of one block (n> m), the same recording can be performed. Further, if the information such as the time information has the same format even for packets of different lengths, the recording / reproducing process becomes easy. Identification when the packet lengths are different may be performed by the recording format of ID-1 in FIG. 7 or the packet length of ID-6. Of course, the packets may be recorded as they are without being associated with the blocks.

When recording m packets in n blocks, if the number of blocks in the recording area is set to be a multiple of n, the management of packets recorded in one track becomes easy. For example, in the case corresponding to FIGS. 10 and 11, the number of blocks for recording data in the data recording area 41 is 6
The number of blocks should be a multiple of.

FIG. 13 shows the structure of the block information 33. The block information 33 is information for identifying data in block units. The data information 74 is information for identifying the type of data recorded in this block. For example, 0 may be set in a block in which normal packet data is recorded, 1 in a block in which valid data is not recorded, and 2 in a block in which variable speed reproduction data is recorded. The block number 75 is information for identifying the order of blocks when packet data is recorded in units of 2 blocks or 3 blocks. For example,
It is set to 0 to 1 when recording in units of 2 blocks, and 0 to 2 when recording in units of 3 blocks. Further, if the end of the recording area can be identified by these pieces of information, the processing at the time of reproduction becomes easy.

FIG. 14 shows an example when the block information 33 is recorded in units of two blocks. Reference numeral 51 is a block in which normal packet data is recorded, 52 is a block in which variable speed reproduction data is recorded, and 53 is an unused area. In this manner, by recording the data other than the variable speed reproduction data in the justified position, the packet data input at an arbitrary interval can be efficiently recorded. If an invalid block occurs between the blocks, the data information 74 of the block may be set to 1. In the unused area 53, the data information 74 is set to 1 and the block number 75 is set to 3 so that the end of the data can be detected.

At the time of reproduction, the data information 7 is made in blocks.
4 is identified, and if it is other than 0, the block may be skipped and output. This makes it possible to maintain compatibility during reproduction regardless of where variable-speed reproduction data or invalid data is recorded. Even if other special data is recorded, there is no problem if different data information is assigned to the block. Furthermore, the data information 74 is 1
The end of the recording area can be detected by identifying the block having the block number 3 and the block number 3. This allows
Since it is not necessary to access an unnecessary area, it is possible to reduce the load during reproduction.

FIG. 15 shows the configuration of the input / output circuit 107. 300 is a packet detection circuit, 301 is a time information confirmation circuit, 302 is an output control circuit, 303 is a buffer, 30
Reference numeral 4 is a time control circuit. It is assumed that the transmission rate of data input / output from the input / output terminal 108A, that is, the frequency of the synchronization clock is the same as the reference clock of the recording / reproducing apparatus transmitted by the oscillation circuit 110.

At the time of recording, data and a synchronous clock are input from the input / output terminals 108A and 108B at the timing shown in FIG. The input data and synchronous clock are input to the packet detection circuit 300 and input to the input terminal 30.
The packet is detected by the clock output from the timing generation circuit 105 input from the S7. Then, the detected packet 71 is output from the output terminal 305A to the recording / reproducing signal processing circuit 102. In the recording / reproducing signal processing circuit 102, the packet 71 input during the period corresponding to one track of recording is arranged in the front justified, and the block information 33 and the like are added and recorded. The control signal or the like sent in addition to the packet is output from the output terminal 306A to the control circuit 104, and the type of packet is discriminated and the recording mode is determined. The time information 25 added to each packet is output to the time information confirmation circuit 301.

In the time information confirmation circuit 301, the time information 2
5 and the intervals between packets counted by the clock input from the input terminal 307 are compared. If there is a deviation between the two, a control signal output from the output terminal 308 causes
The timing control circuit 109 controls the recording processing timing and the rotation speed of the rotary head 100 so as to correct the deviation.

During reproduction, the output control circuit 3 is controlled by a control signal from the control circuit 104 input from the input terminal 306B.
02 is controlled to the output mode, and the reproduced packet 71 is output in synchronization with the reference clock transmitted from the oscillation circuit 110. The recording / reproducing signal processing circuit 102 identifies the reproduced block block information 33 and the like, and outputs only valid packets that are reproduced without error. Input terminal 3
The packet input from 05B is stored in the buffer 303. Further, the time information 25 in the packet is input to the time control circuit 304. The time control circuit 304 controls the timing of reading and outputting a packet from the buffer 303 and generation of a synchronous clock according to the time information 25 and the clock input from the input terminal 307.
The output is performed at the timing shown in FIG. 11, that is, the same timing as the timing when the recording data is input. As a result, in a device for receiving and processing a reproduced packet, such as a digital compressed video signal decoding device or another digital signal recording / reproducing device, recording / reproducing is performed by the same processing as that for processing a signal before recording as it is. Later signals can be processed.

FIG. 17 shows an example of connection between the digital signal recording / reproducing apparatus of FIG. 1 and a digital broadcast receiver. 20
Reference numeral 0 is a digital signal recording device of FIG. 1, 201 is a digital broadcast receiver, 202 is an antenna, and 206 is a receiver. Further, 203 is a tuner, 204 is a selection circuit, and 20
Reference numeral 5 is a decoding circuit, and 206 is an interface circuit.
The digital broadcast signal received by the antenna 202 is demodulated by the tuner 203, and then the necessary digital compressed video signal is selected by the selection circuit 204. The selected digital compressed video signal is decoded by the decoding circuit 205 into a normal video signal and output to the receiver 206. Also, when the received signal is subjected to scrambling or the like, the decoding circuit 205 cancels it and then performs decoding processing. When recording, the interface circuit 206 converts it to the format shown in FIG. 16 and outputs it. Then, it is input to the digital signal recording device 200 from the input / output terminal 108 and recorded. The digital compressed video signal and the like reproduced by the digital signal recording / reproducing device 200 is output to the interface circuit 206 from the input / output terminal 108. The interface circuit 206 performs the same processing as the normal reception on the input signal, and
6 is output.

The input / output circuit of FIG. 10 can be similarly applied to the input / output circuits of other devices such as the digital broadcast receiver 201. Even in a digital broadcast receiver or the like, by setting the transmission rate to an integral multiple of the frame frequency, for example, it becomes easy to synchronize the reference clock when demodulating the video signal with the transmission rate.

Further, in the embodiment, the input and output terminals are used together, but the input and output terminals may be provided separately.

[0045]

According to the present invention, a block in which a packet format digital signal is recorded by the block information added in block units and a block in which other signals such as a variable speed reproduction signal are recorded. Alternatively, a block in which a valid signal is not recorded can be discriminated from a block in which it is not recorded and the end of the recorded area can be discriminated. Can correspond to.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital signal recording / reproducing apparatus.

FIG. 2 is a recording pattern diagram of one track.

FIG. 3 is a block configuration diagram of each area.

FIG. 4 is a configuration diagram of ID information 21.

5 is a configuration diagram of data of one track in a data recording area 7. FIG.

FIG. 6 is a configuration diagram of a header 44 of the data recording area 7.

7 is a configuration diagram of format information 31. FIG.

FIG. 8 is a diagram showing an example of recording variable speed reproduction data.

FIG. 9 is a configuration diagram of a configuration of additional information 32.

10 is a block diagram of a block when recording a digital compressed video signal transmitted in a 188-byte packet format in a data recording area 41. FIG.

FIG. 11 is a block diagram of a block when the length of a packet 71 is 140 bytes.

12 is another configuration diagram of the packet of FIG. 10 or FIG.

FIG. 13 is a configuration diagram of block information 33.

FIG. 14 is a diagram when recording block information 33 in units of two blocks.

FIG. 15 is a configuration diagram of an input / output circuit 107.

FIG. 16 is a timing diagram of input / output signals.

FIG. 17 is a connection diagram between the digital signal recording / reproducing apparatus of FIG. 1 and a digital broadcast receiver.

[Explanation of symbols]

7 ... Data recording area, 20 ... Sync signal, 21 ... ID information, 22 ... Data, 23 ... C1 parity, 25 ... Time information, 31 ... Format information, 32 ... Additional information, 33 ...
Block information, 41 ... Video signal data, 43 ... C2 parity, 44 ... Header, 50 ... Variable speed data, 51 ... Ordinary packet data 52 ... Block for recording variable speed reproduction data, 53 ... Unused area, 71 … Packets, 72
... control information, 74 ... data information, 75 ... block information,
100 ... rotary head, 101 ... capstan, 102 ...
Recording / reproducing signal processing circuit, 104 ... Control circuit, 105 ... Timing generating circuit, 106 ... Servo circuit, 107 ... Input / output circuit, 109 ... Timing control circuit, 110 ... Oscillation circuit, 112 ... Analog signal recording / reproducing circuit, 300 ... Packet Detection circuit, 301 ... Time information confirmation circuit, 302 ... Output control circuit, 303 ... Buffer, 304 ... Time control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiro Owase 1410 Inada, Hitachinaka City, Ibaraki Prefecture Hitachi, Ltd. Personal Media Equipment Division (72) Keiji Noguchi 1410 Inada, Hitachinaka City, Ibaraki Hitachi Ltd. Media Equipment Division

Claims (6)

[Claims] 1. An n-byte packet format digital signal is divided into a predetermined number of bytes, and a sync signal, a control signal and an error detection and correction code are added to form a block format, and a digital signal is recorded by a predetermined number of the blocks. In a digital signal recording device for forming an area and recording on a magnetic recording medium, a recording means for recording the control signal by adding identification information for identifying the type of the signal recorded in the block in block units is provided. A digital signal recording device characterized by the above. 2. The identification information includes a block in which a packet-type digital signal is recorded and a block in which other signals are recorded or a block in which a valid signal is not recorded is not recorded. 2. The digital signal recording device according to claim 1, wherein the information is identifiable information. 3. In the packet-type digital signal, signals input at a predetermined time are arranged in order from the beginning of the digital signal recording area, and the identification information is stored in the remaining area where no signal is arranged. 2. The digital signal recording device according to claim 1, wherein the information is identifiable information. 4. An n-byte packet format digital signal is divided into a predetermined number of bytes, a sync signal, a control signal and an error detection and correction code are added to form a block format, and a digital signal is recorded by a predetermined number of the blocks. In a digital signal reproducing apparatus for reproducing a signal recorded on a magnetic recording medium by forming an area, identification information for identifying the type of the signal recorded in the block is identified from the control signal and recorded in the block. A digital signal reproducing apparatus characterized in that it is provided with reproducing means for judging whether or not to output the packet-type digital signal. 5. The reproducing means outputs only a signal of a block which is reproduced without error and which is judged by the identification information that the digital signal of the packet format is recorded. 4. The digital signal reproducing device described in 4. 6. The reproducing means performs identification of the identification information and output processing of the packet-format digital signal from the head of the digital signal recording area, and no signal is recorded after the identification information. 6. The digital signal reproducing apparatus according to claim 5, wherein when judged, the identification and output processing in the area is ended.