JPH08272738A - Compensation system for recovery time of microprocessor system - Google Patents

Abstract

PURPOSE: To compensate the recovery time through hardware without using any NOP command of a microprocessor. CONSTITUTION: In the system, wherein a microprocessor 1 is accessed by at least >=1 external circuits 21-2N, sends a command signal to asynchronous external circuits, and receives a ready response signal to make a handshake, a dummy register 3 sets the time required for the internal process of the accessed external circuit by a sending-back time control circuit 31 after the command signal from the microprocessor 1, and this time is clocked by a delay generating circuit 32 to send the ready response signal back, and when the microprocessor 1 accesses an external circuit requiring a recovery time continuously, the dummy register 3 is accessed to make the microprocessor stand by for the recovery time set in the dummy register, thereby performing necessary recovery time compensation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for controlling a recovery time by a programmable ready return time in a system for handshaking by returning a ready response signal to a command between a microprocessor and an asynchronous external circuit. .

[0002]

2. Description of the Related Art Generally, a compound instruction set computer (C
ISC: Complex Instruction C
The recovery time must be compensated for when the handshake is performed between the microprocessor and the external circuit. Here, the recovery time is a time during which an external circuit that outputs or receives data in response to a read or write command from the microprocessor prohibits access from the microprocessor until the internal processing is completed. That is, when the microprocessor continuously accesses the external circuit, the next command is executed after the recovery time or more has elapsed from the end of the previous command to compensate for the normality of data. Can be done.

As a method of compensating for such recovery time, NOP (No
Operation) is used to increase the command access interval from the microprocessor. For example, FIG. 4 is a timing chart thereof. First, after an external circuit is accessed, the microprocessor executes a NOP instruction to enter a standby state, and after a predetermined recovery time, the same external circuit is accessed. It is carried out. As a result, the access from the microprocessor is prohibited until the external circuit completes the internal processing.

In this conventional recovery time compensation method using NOP instructions, it is necessary to calculate the number of NOP instructions to be inserted from the recovery time, the machine cycle of the microprocessor and the execution machine cycle of NOP instructions, and the procedure is complicated. there were. Also, when the machine cycle changed, the program had to be modified, and the compatibility of the software could not be maintained. Furthermore, a reduced instruction set computer (RISC: Reduced Ins.
This system itself has no effect in the circuit that constitutes the microprocessor system by the "Traction Set Computer". This is because the NOP instruction does not work due to optimization when the source code is compiled for RISC.

A technique for normalizing the timing of the ready signal by the handshake between the microprocessor and the external circuit in this manner is disclosed in, for example, Japanese Patent Laid-Open No. 61-13.
There is a technique described in Japanese Patent No. 4862. In this technique, a ready response register is provided in the external device, and the microprocessor can control the return time of the ready response signal in a programmable manner, so that the waiting time for the external device in the microprocessor is arbitrarily set, It is to increase the degree of freedom.

[0006]

However, in the technique described in this publication, after the microprocessor sends the command signal to the external device, it waits until the microprocessor receives the ready response signal from the external device. It is a technique of putting in a wait state. Therefore, after receiving the ready response signal from the external device, the command signal is immediately sent to the same external device to execute the access. As described above, the accessed external circuit completes the internal processing. Until then, it cannot be applied for recovery time compensation that prohibits access from the microprocessor.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a recovery time compensation system capable of performing recovery time compensation based on a hardware configuration without using a NOP instruction.

[0008]

The recovery time compensation system of the present invention is a system in which a microprocessor is accessed to at least one or more external circuits,
It has a dummy register that can be selected by the microprocessor, and is configured to access the dummy register during these accesses when the microprocessor continuously accesses an external circuit that requires recovery time.

That is, the microprocessor is constructed as a system for transmitting a command signal to and from an asynchronous external circuit and performing a handshake by receiving a ready response signal, and the dummy register receives the command signal from the microprocessor. Thereafter, the ready response signal is transmitted after the elapse of the time required for the internal processing of the accessed external circuit.

[0010]

When the microprocessor continuously accesses an external circuit that requires recovery time, by accessing the dummy register, the microprocessor waits between two accesses during the recovery time set in the dummy register. The necessary recovery time compensation is realized.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a recovery time compensation system of the present invention. , 2N are connected to the microprocessor 1 via a data bus 11, an address bus 12, a command bus 13, and a ready bus 14. These external circuits 21 to
2N is the microprocessor 1 via the command bus 13
Address bus 12 when a command signal is sent from
The external circuit specified by is accessed, and at the same time, the data of the memory address (not shown) specified by the address bus 12 can be input / output to / from the external circuit accessed through the data bus 11. It Then, after the input / output of the data is completed, the accessed external circuit returns a ready response signal to the microprocessor 1 via the ready bus 14, and completes a predetermined internal process based on the input data. Are configured to do so.

A dummy register 3 is connected to the data bus 11, address bus 12, command bus 13 and ready bus 14. This dummy register 3
Is a ready bus 14 when a command signal is input from the microprocessor 1 via the command bus 13.
And a return time control circuit 3 for setting a time until a ready response signal is returned to
1 and a ready generation circuit 32 for generating a ready response signal based on the signal from 1 and sending it to the ready bus 14. Here, the return time control circuit 31 sets the return time of the ready response signal based on the data input from the microprocessor 1 via the data bus 11. In addition, the ready generation circuit 32, when the dummy register 3 is selected by the address bus 12, has passed the time set by the return time control circuit 31 after the command signal is input through the command bus 13. It is later configured to send a ready response signal to the ready bus 14.

The recovery time compensation operation in such a configuration will be described. FIG. 2 is a timing chart showing an example of the operation, and FIG. 3 is a flow chart showing the operation in the dummy register. As shown in these figures, here, an example is shown in which the same external circuit 2M (M ≦ N) is continuously accessed. When accessing the external circuit 2M, as described above, the external circuit 2M is selected by the address bus 12, and at the same time, the command bus 13 is selected.
A command signal is sent to the external circuit 2M via. As a result, the external circuit 2M is accessed. Then, the address bus 12 reads the data of the address of the memory (not shown), and this data is passed through the data bus 11 to the external circuit 2
Output to. When the external circuit 2M inputs data, it returns a ready response signal to the microprocessor 1 via the ready bus 14, and thereafter executes internal processing.

Upon receiving the ready response signal, the microprocessor 1 immediately receives the external circuit 2 as the next access.
Move to execution of M access. At this time, if the accessed external circuit 2M is an external circuit that does not require recovery time, the external circuit 2M is continuously accessed in the same manner as the previous access to the external circuit 2M. On the other hand, when the external circuit 2M is an external circuit requiring a recovery time, an operation of waiting for access by the microprocessor 1 until the external circuit 2M completes internal processing based on the previous data, that is, However, recovery time compensation will be required.

For this recovery time compensation, the microprocessor 1 uses the address bus 12 to set the dummy register 3
Is set to an access state, and at the same time, data of the time required for internal processing in the external circuit 2M is sent to the data bus 11. As a result, the dummy register 3
Then, the return time control circuit 31 sets the time required for the internal processing of the external circuit 2M, that is, the recovery time, based on the input data. Then, in response to the command signal subsequently sent from the microprocessor 1, the ready generation circuit 32 starts measuring time,
After measuring the recovery time, the ready response signal is sent to the ready bus 14.

After receiving the ready response signal, the microprocessor 1 again accesses the external circuit 2M in the same manner as described above. At this time, the dummy register 3
During the access in, the microprocessor 1 is in the standby state, and the internal processing in the external circuit 2M is completed during this time, so that the recovery time is compensated for the external circuit 2M, and the external circuit 2M
There is no problem even if the access is continuously made to.

When the present invention is compared with the one described in the above-mentioned publication, it is common in that the microprocessor waits for a predetermined time when accessing an external circuit. The one puts the microprocessor in a standby state until a predetermined process is completed in an external device, while the one of the present invention puts the microprocessor in a standby state while accessing an external circuit. The two are fundamentally different.
Therefore, the technique disclosed in the publication is such that even when different external devices are continuously accessed, until the ready response signal is sent from the previous external device by handshake, that is, this external device is not in a predetermined state. The microprocessor is placed in a waiting state until the processing is completed.

On the other hand, in the recovery time compensation of the present invention, the recovery time compensation is executed by the dummy register only when the external circuit requiring the recovery time is continuously accessed, and the recovery time compensation is performed for different external circuits. It is not performed when accessing continuously in succession, and the waiting state by the microprocessor becomes unnecessary. Therefore, when accessing different external circuits, unnecessary waiting in the microprocessor becomes unnecessary, and the processing speed can be improved.

[0019]

As described above, the present invention has the dummy register that can be selected by the microprocessor, and when the microprocessor continuously accesses the external circuit requiring the recovery time, these accesses can be performed. By accessing the dummy register in between, the recovery time necessary for hardware can be inserted, and NOP
The procedure can be simplified as compared with the case of using the instruction. As a result, even when the same external circuit is continuously accessed, it is possible to access it when the internal processing of the external circuit is completed. Further, when accessing different external circuits, there is an effect that an unnecessary waiting state in the microprocessor can be eliminated.

Further, according to the present invention, when the dummy register is configured as a system for handshaking between the microprocessor and the external circuit, the dummy register is accessed after receiving the command signal from the microprocessor. It is possible to realize recovery time compensation in such a handshake system by configuring the ready response signal to be sent after the time required for the internal processing of the above.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a recovery time compensation system of the present invention.

FIG. 2 is a timing diagram for explaining a recovery time compensation operation of the present invention.

FIG. 3 is a flowchart for explaining a recovery time compensation operation of the present invention.

FIG. 4 is a timing diagram for explaining a conventional recovery time compensation operation.

[Explanation of symbols]

 1 Microprocessor 11 Data Bus 12 Address Bus 13 Command Bus 14 Ready Bus 21-2N, 2M External Circuit 3 Dummy Register 31 Return Time Control Circuit 32 Ready Generation Circuit

Claims (4)

[Claims] 1. A system in which a microprocessor is accessed for at least one or more external circuits,
Having a dummy register selectable by the microprocessor, when the microprocessor continuously accesses an external circuit requiring a recovery time,
A recovery time compensation system characterized in that the dummy register is accessed during these accesses. 2. The microprocessor is configured as a system that sends a command signal to and from an asynchronous external circuit and receives a ready response signal to perform a handshake, and the dummy register receives a command signal from the microprocessor. 2. The recovery time compensation system according to claim 1, wherein a ready response signal is transmitted after a lapse of time required for internal processing of the accessed external circuit. 3. A dummy register, a return time control circuit for setting a time required for internal processing of an external circuit to be accessed, and a ready response signal after the set time has elapsed when a command signal is received. The ready time compensation system according to claim 2, further comprising: 4. The recovery time compensation system according to claim 3, wherein the return time control circuit controls the set time based on the data sent from the microprocessor.