JPH08263289A - Pipeline computer for plural instruction flows - Google Patents

Abstract

PURPOSE: To improve the arithmetic processing ability of a pipeline computer. CONSTITUTION: An instruction flow identification tag generation unit 31 generates an instruction flow identification tag for identifying plural instruction flows. A PC unit 32 is provided with the same number of program counters as the instruction flows to select the program counter of an instruction flow shown by the tag. A decoder 3 decodes an instruction specified by the program counter. A renaming register 33 executes the renaming of registers by distinguishing the instruction flow based on the instruction flow identification tag. Each reservation station 10 to 13 holds the decoded instruction and the entry values, etc., of the instruction flow identification tag and the renaming register 33. Each arithmetic unit 20 to 23 executes an instruction and sends the execution result to an entry corresponding to the renaming register 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-instruction flow pipeline computer having a function of executing a plurality of instruction sequences, and more particularly to a control configuration for using general purpose registers.

[0002]

2. Description of the Related Art In a pipeline computer that processes a single instruction stream, a superscalar system that executes a plurality of instructions at the same time in order to improve its processing performance, and an out-of-order issue that executes instructions in different order. Is used.

At this time, register renaming is used as a technique for avoiding data dependence between instructions which causes performance degradation. By using this register renaming, among the instruction dependence, the preceding instruction must read the value of that register before it can write a new value to the register, and the output that it tried to write to the same register at the same time. You can remove the two dependencies of dependence. As a result, it is possible to suppress the performance deterioration due to dependence.

[0004]

However, during execution of a pipeline computer that processes a single instruction stream as described above, execution may occur due to true dependence of data, memory store, cache miss-hit, and the like. I was kept waiting,
The computing resources of the processor may be wasted because they are not used.

In particular, in the case of the superscalar system, as the calculation resource of the processor, for example, although four instructions can be simultaneously calculated, only two instructions can be executed due to the dependency between the instructions, and the remaining calculation resources are used. There were times when it wasn't.
From such a point, it has been desired to realize a pipeline computer capable of effectively using the arithmetic unit and improving the arithmetic processing capability.

[0006]

A multiple instruction flow pipeline computer of the present invention comprises an instruction flow identification tag generation unit for generating a tag for identifying a plurality of instruction streams, and a program counter for the number of instruction streams. A PC unit that selects a corresponding program counter based on the instruction stream identification tag and a renaming register that renames the register for each instruction stream based on the instruction stream identification tag are provided. Then, the arithmetic unit is configured to execute the instruction designated by the program counter selected from the PC unit, using the value of the renaming register.

[0007]

In the multi-instruction flow pipeline computer of the present invention, the instruction flow identification tag generation unit sends a signal for selecting one of a plurality of instruction flows. This gives P
The C unit selects the corresponding program counter,
As a result, either instruction stream is selected. In addition, the renaming register changes the register name for each instruction stream based on the instruction stream identification tag. Furthermore, the arithmetic unit
The value in the renaming register is used to execute the instruction in the instruction stream selected by the program counter.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a multi-instruction flow pipeline computer according to an embodiment of the present invention. Prior to this,
The configuration of the superscalar processor will be described.

FIG. 2 is a block diagram of the superscalar processor. The apparatus shown in the figure includes an instruction memory 1, an instruction cache 2, a decoder 3, a reorder buffer 4, a register 5, a program counter (PC) 6, a data cache 7, a data memory 8, and a reservation station 10.
-13, and arithmetic units 20-23.

The instruction memory 1 is connected to the decoder 3 through the instruction cache 2. The output from the decoder 3 is connected to the reservation stations 10 to 13 of the arithmetic units 20 to 23, the reorder buffer 4 and the register 5. The output of the program counter 6 is connected to the instruction memory 1 through the instruction cache 2. The reservation stations 10 to 13 are connected to the corresponding arithmetic units 20 to 23, and the outputs of the arithmetic units 20 to 22 except the load / store unit 23 are connected to the reorder buffer 4. The output of the load / store unit 23 is connected to the data memory 8 through the data cache 7. In addition, each of the arithmetic units 20 to 23, for example, branches (Branch), arithmetic operation (AL
U), shifter (Shifter), load / store (Load / Sto
re) unit.

FIG. 3 is a block diagram of the reorder buffer 4. The reorder buffer 4 is a table having a v field, a dest field, a data field, and a C field. Here, the v field is a 1-bit value indicating whether or not the entry is valid, and the dest field indicates which register value the entry actually holds. The data field holds the value of the register or the result tag. The C field is a 1-bit flag for distinguishing whether the data field of the entry has an actual value or the completion of execution, that is, the result tag.

As described above, the reorder buffer 4 has a dest
It is an associative memory that has a field as a search key.

Next, general register renaming will be described. Even with out-of-order issuance, where instructions are issued almost independently of the original program order, the constraint on issuing individual instructions is that the instructions are issued in the original program order. It is almost the same as the case. That is, the instruction is issued when the resource competition and the dependency disappear. Out-of-order issuance simply gives a large number of instructions to be issued to the processor, and as a result makes it easier to find instructions that can be executed in parallel. However, issuing commands out-of-order places new restrictions on command issuing. This is exactly the same as out-of-order completion caused constraints on output dependencies.

This will be described using an example of an instruction sequence. R3 = R3 × R5 (1) R4 = R3 + 1 (2) R3 = R5 + 1 (3) R7 = R3 ÷ R4 (4) Here, for example, in the case of (1), the value of the register R3 and the register R5 And the value is written to the register R3.

In the above instruction sequence, the third instruction cannot be completed before the second instruction starts executing. Otherwise, the first source operand (= R3) of the second instruction is erroneously overwritten by the third instruction. The execution result of the third instruction is an inverse dependency (antide) on the first source operand of the second instruction.
pendecy). Here, the inverse dependency means the same constraint as the true dependency except that the directions are opposite. In the true dependency, the preceding instruction generates the value used by the subsequent instruction, whereas in the inverse dependency, the subsequent instruction destroys the value used by the preceding instruction. To avoid this, the processor must not issue the third instruction until the second instruction begins execution. Since the second instruction depends on the first instruction, the third instruction has to wait for the completion of the first instruction. Even if the third instruction is otherwise independent.

A means for solving this is a technique called register renaming (register name change). The processor eliminates memory contention by providing additional registers and reconstructing the correspondence between registers and values. These additional registers are dynamically allocated by the hardware at run time and are associated with the values needed by the program in register renaming. To implement register renaming, the processor allocates a new register for every newly generated value, ie every instruction that writes to it.

The instruction to read the value from the register is originally
Read the value from the newly allocated register instead of from the specified register. In this way, the hardware changes the original register name in the instruction to identify the new register and the correct value. Even with the same register name, different instructions will access different hardware registers depending on the location of the register reference to the register allocation.

When the name is changed, the above instruction sequence becomes as follows. R3 _b = R3 _a × R5 _a (1) R4 _b = R3 _b +1 (2) R3 _c = R5 _a +1 (3) R7 _b = R3 _c ÷ R4 _b (4)

In this instruction sequence, each assignment to the register is
We are creating a new instance, which is shown in the alphabetical subscript. R in the third instruction
A new instance is generated for 3, and the inverse dependency and the output dependency for the second instruction and the first instruction are deleted. Moreover, the operand is correctly supplied to the fourth instruction. The assignment of the third instruction to R3 replaces the assignment of the first instruction R3. Therefore, until another instruction assigns a value to R3, R3 _C becomes a new R3 from the viewpoint of the succeeding instruction.

Next, the operation of the superscalar processor thus constructed will be described. The program counter 6 accesses the instruction cache 2, and the output from the instruction cache 2 is sent to the decoder 3. (For example,
It is assumed that the instruction sequences (1) to (4) are sent. ) The decoder 3 interprets the instruction and determines which arithmetic unit 2
0-23, and sends the output to the corresponding reservation station 10-13. (For example, in (1) to (4) above, since it is an arithmetic operation, it is sent to the reservation station 11.

At the same time, the decoder 3 stores the value of the source register and the value of the destination register of the instruction in the reorder buffer 4, and the value of the source register in the register 5.
Send to For example, in the case of (1), the value of R3 _a, R5 _a value and R3 _b to the reorder buffer 4, also, R3 _a, R
5 and sends the value of _a in the register 5.

The reorder buffer 4 draws an associative memory by using the value of the source register as a key, and sends the latest value among the ones matching the dest field to the corresponding reservation stations 10 to 13. At this time, if the C field of the matching entry is invalid (it was a result tag), the value of the result tag is sent instead of the value.

If there is no matching entry in reorder buffer 4, the value in register 5 is sent to reservation stations 10-13. Further, the reorder buffer 4 holds the value of the destination register in the dest field of the new entry, validates the v field, invalidates the C field, generates a result tag, and holds it in the data entry. Further, the value of the entry of the reorder buffer 4 is sent to the reservation stations 10 to 13, which becomes the new destination of the instruction.

FIG. 4 is an explanatory diagram showing the values of the above-mentioned instruction sequence in the reorder buffer 4. Here, R3 from the entry of the above, a R3 _b in the above instruction sequence, the following R
4 is R4 _b , R3 next is R3 _c , and R7 is R7
It is an entry of _b . That is, this state is R3 _a , R5
The value of _a is in the register 5, R3, R4, R3, R7
Is the value of the destination register corresponding to (1) to (4) in the instruction sequence. Then, by using this reorder buffer 4, it is understood that the expression (3) can be executed independently of the expressions (1) and (2). In the v field and the C field, "1" indicates valid and "0" indicates invalid. Further, "105" to "108" in the data field indicate result tags.

The reservation stations 10 to 13 hold these decoded instructions, the entry value (destination) of the reorder buffer 4, and the source register value (or the result tag value). If the operation units 20 to 23 to be operated are empty and the values of the source register are complete, the operation unit 2
Sent to 0-23. For example, in the configuration of FIG. 2, if there are a plurality of arithmetic operation units 21 and the source registers R3 _a and R5 _{a have} the same values, the above (1)
The expression and the expression (3) are simultaneously executed.

The results executed by the arithmetic units 20 to 23 are sent to the previous entries of the reorder buffer 4 except for the store instruction, the results are written in the data field, and C
Enable the field. At that time, the reservation stations 10 to 13 are searched for those having a tag that matches the value of the result tag written in the data field, and if there is a match, the reservation stations 10 to 13 are searched. Also write the result. If the execution of the previous instruction is completed in the actual instruction order, the data value of the entry is sent to the register 5 indicated by the dest field, and the v field is invalidated.

When an interrupt or exception occurs,
The entries of the reservation stations 10 to 13 are invalidated, and the v field of the entry of the reorder buffer 4 is invalidated.

By the way, when there are a plurality of instruction streams such as execution of a plurality of applications, if the instruction streams can be executed for each instruction stream, the arithmetic unit can be effectively used.
The performance of the processor can be improved.

FIG. 5 is an explanatory diagram of such a plurality of instruction streams. This example shows two applications AP1, A
The instruction sequence of P2 is shown, and each instruction (1A)-
(4A) and the instructions (1B) to (4B) are completely unrelated to the execution order of the program. In this embodiment, in order to enable a plurality of instruction streams to be executed simultaneously in such a case, the configuration of FIG. 1 is adopted, which will be described in detail below.

The apparatus shown in FIG. 1 includes an instruction memory 1, an instruction cache 2, a data cache 7, a data memory 8, reservation stations 10 to 13, and an arithmetic unit 2.
0 to 23, an instruction stream identification tag generation unit 31, a PC unit 32, and a renaming register 33. Here, the instruction memory 1 to the arithmetic unit 23
The configuration of is the same as the configuration of FIG. 2 described above.

The instruction stream identification tag producing unit 31 is a unit for producing a tag for identifying a plurality of instruction streams.
The output is output from the reservation stations 10 to 13 of the arithmetic units 20 to 23 and the renaming register 3
3 and the PC unit 32. The PC unit 32 includes program counters (P
C), the output of which is connected to the instruction memory 1 through the instruction cache 2.

FIG. 6 is a block diagram of the renaming register 33. This renaming register 33 has an instruction stream instruction bit field IN consisting of [log ₂ n] (rounded up to the nearest decimal point, where n> 1 is the number of instruction streams) bits in the normal reorder buffer 4 shown in FIG. 1-bit completion flag field IC is added.
The associative memory uses the st field and the IN field as search keys. That is, the instruction flow instruction bit field IN
Is a value for identifying which instruction flow the value of the entry is, and the completion flag field IC is a field for handling an interrupt.

First, the instruction flow identification tag generation unit 31
Sends a signal to the PC unit 32 to select one of the PCs having an instruction stream. The PC unit 32 accesses the instruction cache 2 with the selected PC value, and the output from the instruction cache 2 is sent to the decoder 3. The decoder 3 interprets the instruction, determines which arithmetic unit 20-23 to send and sends the output to the corresponding reservation station 10-13.

At the same time, the instruction stream identification tag generating unit 31 sends an instruction stream identification tag of [log ₂ n] (rounded up to the right of the decimal point) to the same reservation station. Further, at the same time, the value of the source register and the value of the destination register of the instruction are sent from the decoder 3 and the instruction stream identification tag is sent from the instruction stream identification tag generating unit 31 to the renaming register 33. The renaming register 33 draws an associative memory using the value of the source register and the instruction stream identification tag as a key, and sends the latest value among the matching ones to the corresponding reservation stations 10 to 13.

At this time, if the C field of the matching entry is invalid, the value of the result tag is sent instead of the value. The renaming register 33 adds the value of the destination register to the dest field of the new entry and the instruction stream identification tag to the IN field, and further adds v
Enable the fields, disable the C and IC fields, generate result tags and hold them in the data field. Further, the value of the entry of the renaming register 33 is sent to the reservation stations 10 to 13.

FIG. 7 is an explanatory diagram of contents of the renaming register 33. That is, this is for the instruction sequence with two applications AP1 and AP2 shown in FIG. 5 is entered, the value of each of R3 _a and R5 _a application AP1 and AP2 have been written in the data field Therefore, the C field is valid (= 1), and the IC field is valid (= 1) because all the IC fields of the entry holding the result of the previous instruction are valid. There is. As described above, since the AP1 and AP2 have different IN field values, these instructions can be executed simultaneously. Note that “2”, “3”, “5”, and “6” in the data field are values, and “1”
05 ”-“ 108 ”and“ 201 ”-“ 204 ”
The value of the result tag.

The reservation stations 10 to 13 hold the decoded instruction and instruction stream identification tag, the entry value of the renaming register 33, and the value of the source register (or the value of the tag). If the arithmetic units 20 to 23 are empty and the values of the source register are complete, the arithmetic units 20 to
Sent to 23.

The results executed by the arithmetic units 20 to 23 and the instruction stream identification tag are sent to the previous entries of the renaming register 33 except for the store instruction, the results are written in the data field, and the C field is validated. At that time, the reservation stations 10 to 13 are searched for those having a tag that matches the value of the result tag written in the data field, and if there is a match, the reservation stations 10 to 13 are searched. Also write the result. Further, the IC field is validated when all the IC fields of the entry holding the result of the previous instruction in the actual instruction order of execution are valid. If there is an entry having the same dest entry among valid IC fields, the v field of the older entry is invalidated.

When an interrupt or exception occurs, the entries of the reservation stations 10 to 13 having the same tag as the instruction stream identification tag that caused the interrupt or exception are invalidated, and in the entry of the renaming register 33. , IN field and instruction stream identification tag match, IC
Invalidates the v field even though the field is invalid.

[0040]

As described above, according to the multi-instruction flow pipeline computer of the present invention, the multi-instruction flow pipeline computer has a program counter for accessing a plurality of instruction streams and identifies a plurality of instruction streams. Since the renaming register with a tag is used for register renaming, even if the arithmetic unit is empty, instructions cannot be issued and cannot be effectively used due to true dependence. Since the plurality of instruction streams can be executed, the arithmetic unit can be effectively used and high throughput processing can be performed while maintaining high arithmetic processing performance.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a multi-instruction flow pipeline computer of the present invention.

FIG. 2 is a configuration diagram of a general superscalar processor.

FIG. 3 is a configuration diagram of a reorder buffer.

FIG. 4 is an explanatory diagram showing an example of an instruction sequence in a reorder buffer.

FIG. 5 is an explanatory diagram of a plurality of instruction streams.

FIG. 6 is a configuration diagram of a renaming register in a multiple instruction flow pipeline computer of the present invention.

FIG. 7 is an explanatory diagram of contents of a renaming register in the multi-instruction flow pipeline computer of the present invention.

[Explanation of symbols]

 3 Decoder 20-23 Operation Unit 31 Instruction Stream Identification Tag Generation Unit 32 PC Unit 33 Renaming Register

Claims (2)

[Claims] 1. An instruction stream identification tag generation unit for generating an instruction stream identification tag for identifying which instruction stream an arbitrary instruction belongs to, and a program counter for the number of instruction streams. A PC unit that selects a program counter of the indicated instruction stream, a renaming register that renames a register for each instruction stream based on the instruction stream identification tag, and a value of the renaming register that is used by the program counter. A multi-instruction flow pipeline computer, comprising: an arithmetic unit for executing designated instructions. 2. An instruction stream identification tag generation unit for generating an instruction stream identification tag for identifying which instruction stream an arbitrary instruction belongs to, and a program counter for the number of instruction streams. A PC unit for selecting a program counter of the indicated instruction stream; a decoder for decoding an instruction designated by the program counter selected from the PC unit to obtain values of a source register and a destination register in the instruction; A renaming register that outputs data corresponding to the value of the source register and the instruction stream identification tag, and sets the value of the destination register in the instruction as a new entry for each instruction stream, and renames the register; Use the value corresponding to the source register output from the register , And executes the instruction decoded by the decoder, multiple instruction streams pipeline computer, characterized in that an arithmetic unit that writes the value of the destination register an execution result in the renaming register.