JPH08255919A - Power semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a planar power semiconductor element in which high breakdown strength can be obtained stably by presenting predetermined quantity of charges on the interface between specific insulating film and semiconductor layer or in the insulating film thereof. CONSTITUTION: The power semiconductor element comprises a heavily doped semiconductor layer 102 of second conductivity type formed selectively on the surface of a high resistance semiconductor layer 101 of first conductivity type, and a lightly doped semiconductor layer 103 of second conductivity type formed around the semiconductor layer 102 contiguously thereto. The power semiconductor element further comprises an insulating film 106 deposited on the semiconductor layers 102, 103 and the semiconductor layer 101 on the outside thereof, a first main electrode 107 provided on the semiconductor layers 102, a heavily doped semiconductor layer 105 of first or second conductivity type formed on the opposite side to the semiconductor layers 102, 103, and a second main electrode 109. Furthermore, a predetermined quantity of charges are presented on the interface between an insulating film and a lightly doped semiconductor layer 103 of second conductivity, in an insulating film 106 deposited thereon or on the insulating film 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device having a power semiconductor element such as a high breakdown voltage diode, a power transistor and a thyristor.

[0002]

[Prior art]

(First Conventional Example) Conventionally, various power semiconductor elements have been known. FIG. 6 is a sectional view showing an element structure of a high breakdown voltage planar type pn junction diode (hereinafter, simply referred to as a planar type diode) which is one of power semiconductor elements.

In this element structure, a high impurity concentration p ⁺ type layer 2 is selectively diffused on the surface of a high resistance n ⁻ type silicon layer 1, and the p ⁺ type layer 2 is in contact with the periphery of the p ⁺ type layer 2. A p ⁻ type layer (resurf layer) 3 having a low impurity concentration is formed by diffusion.

An n ⁺ type layer (stopper layer) 4 for fixing the surface potential of the n ⁻ type silicon layer 1 is diffused and formed on the surface of the n ⁻ type silicon layer at a predetermined distance from the p ⁻ type layer 3. There is. The element surface is covered with a silicon oxide film 6, a contact hole is opened in this, and the anode electrode 7 is in low resistance contact with the p ⁺ type layer 2 and the stopper electrode 8 is in low resistance contact with the n ⁺ type layer 4. There is.

On the other hand, a cathode electrode 9 is formed on the back surface of the n ⁻ silicon layer 1 via a low resistance n ⁺ type layer 5. According to such a planar diode, the electric field concentrated at the edge portion of the p ⁺ type layer 2 is relaxed by the p ⁻ type layer 3, and a high breakdown voltage is obtained.

The method of manufacturing the planar diode is as follows. First, a substrate on which the n ⁻ type silicon layer 1 is formed is prepared in contact with the n ⁺ type layer 5, and then a silicon oxide film 6 is further deposited on the surface of the n ⁻ type silicon layer 1 to remove PE.
P (Photo Engraving Procedures)
s: An opening is provided in the silicon oxide film by a photo-etching process), p-type impurities are ion-implanted using this as a mask, and then annealing / diffusion is performed to form the p ⁺ -type layer 2.

Next, after the p ⁻ type layer 3 and the n ⁺ type layer 4 are formed by the same process, a silicon oxide film 6 is deposited on the entire surface of the substrate by the CVD method. Then p ⁺ type layer 2, n
After removing a part of the silicon oxide film 6 in the region of the ⁺ type layer 4, an Al film is deposited on the entire surface and the Al film is patterned to form an anode electrode 7 and a stopper electrode 8.

FIG. 7 is a characteristic diagram showing the relationship between the breakdown voltage of the conventional planar diode and the impurity concentration of the p ⁻ type layer 3. This characteristic diagram is described in, for example, J. Kor
e.c. Held, “Comparison
of DMOS / IGBT-Compatible
High-Voltage Termination
Structures and Passivatio
nTechniques "IEEE TRANSAC
TION ON ELECTRON DEVICES,
Vol. 40, No. 10, pp. 1845,199
3. Has been announced at.

In the figure, point A indicates the maximum breakdown voltage when the length of the p ^-- type layer 3 is fixed to a certain value. As is clear from FIG. 6, the breakdown voltage sensitively changes depending on the impurity dose amount of the p ⁻ -type layer 3, and even a slight deviation from the optimum impurity amount causes the breakdown voltage to drop sharply.

However, in the conventional planar diode, the p ^-- type layer 3 and the silicon oxide film 6 are formed during the manufacturing process.
Fixed charges and ions are mixed in or generated at the interface between and, and in the silicon oxide film 6.

Therefore, in the conventional planar type diode, the spread or depletion of the surface depletion layer is changed due to the mixing or generation of the fixed charges or ions, so that a stable high breakdown voltage cannot be obtained and the breakdown voltage is lowered. There was a problem of doing. In the characteristic diagram shown in FIG. 7, the fixed charges and the ions are p
^The equivalent effect is that the amount of impurities in the -type layer 3 is shifted from the optimum value. (Second Conventional Example) Conventionally, many measures have been taken to increase the breakdown voltage of power semiconductor elements (power elements). First, in the mesa structure in which the pn junction is exposed at the end, the maximum electric field at the wafer surface is reduced by forming a bevel structure in which the end is not perpendicular to the main surface of the wafer but is offset from 90 degrees. Have been practiced (eg, RL Davies and
F. E. FIG. Gentry, IEEE Trans. Ele
ctron Devices, vol. ED-11, P
P. 313, 1964. ).

However, in order to fabricate a device with good reproducibility by this method, the thickness of the p-type diffusion layer forming the pn junction needs to be several tens of μm or more, and therefore, the miniaturized and integrated power is required. It is difficult to be compatible with the device.

Further, in the planar structure (planar termination structure) in which the end of the pn junction exists on the main surface of the wafer,
Since the pn junction surface at the end is perpendicular to the main surface of the wafer, electric field concentration is likely to occur. As a method for preventing this, for example, there is a field limiting ring.

The field limiting ring is to surround the element portion with one or more p-type diffusion layers to smooth the shape of the depletion layer and relax the electric field (see, for example, Y. C. Kao and E.
D. Wolley, Proc. IEEE, vol. 5
5, pp. 1409, 1967. ).

However, in order to increase the breakdown voltage by this method, there are problems that a large number of rings are required and the element area becomes large. As a method of increasing the breakdown voltage without increasing the element area, there is a method of using a resistive field plate. This is to reduce the electric field by connecting the anode and cathode with a high resistance film and passing a small amount of current to evenly divide the voltage between the anode and the cathode. S. Mu
kherjee, C.I. J. Chou, K .; Shaw,
D. McArthur and V.I. Rumenni
k, IEDM Technical Digest p
p. 646, 1986. ).

As the material of the resistive field plate, semi-insulating polysilicon (SIPOS) has been conventionally used. However, there is a time delay in the current that flows when a reverse voltage is suddenly applied to SIPOS,
This causes a time delay in the effect of the resistive field plate and causes a leakage current. (Third conventional example) In a semiconductor device having a semi-insulating film on the surface of a semiconductor substrate including a pn junction, particularly in a semiconductor device with an insulated gate that requires a high withstand voltage, a withstand voltage close to the ideal withstand voltage is realized. Therefore, the structure generally expressed by the term junction termination region is provided in a part of the element.

FIG. 11 is a sectional view showing an example of the junction termination region. In the junction termination region, the p ⁺ type guard ring layer 21, the p ⁻ type RESURF layer 22 and the n ⁺ diffusion layer 23 as a channel stopper for appropriately controlling the spread of the depletion layer when a high voltage is applied to the device are provided. It is formed on the surface of the n-type semiconductor substrate. Further, a semi-insulating film (resistive field plate) 24 and a metal electrode (metal field plate) 25 are partially adhered on it via a field oxide film (SiO ₂ film) 29 to form a field plate structure. ing.

With such a junction termination structure, electric field relaxation can be easily achieved, and a breakdown voltage relatively close to the designed breakdown voltage can be realized. Semi-insulating film 2 used in this junction termination structure
4, the oxygen-doped Poly-Si (nominal SIP
OS: Semining Surviving Polycry
stalline Silicon) and amorphous S
Although i is generally used, an effect can be expected with a dielectric film such as TixOy or SixTiyOz.

[0019] Generally speaking, p mentioned above ^- in the resistive field plate with type RESURF layer, p ^- although -type RESURF layer is increased relatively withstand longer, the upper limit exists in Risafudozu amount Risafudozu The larger the amount is, the higher the breakdown voltage of the main junction is, but conversely, electric field concentration is likely to occur near the resurf end, and there is a problem that avalanche breakdown is more likely to occur at the resurf end than at the main junction.

In addition, the voltage is sharply raised between the elements (for example, dv / dt = 500 to 1000 V / μse).
When applied in c), as shown in FIG. 12, dv / dt
There was a problem that a mutation current abruptly occurred in the time around the shoulder opening where the curve started to be saturated, which resulted in a large turn-off loss and the device could not be used at the expected device breakdown voltage.

Particularly, the latter phenomenon is presumed to be directly related to the magnitude of the leak current flowing through the pn junction surface, and in the junction termination structure shown in FIG. 11, the SiO ₂ film 29 under the resistive field plate 24 has the following structure. It can be interpreted that a large current is generated due to the sudden application of dv / dt because the conduction channel on the surface of the pn junction is long due to the influence of the positive charge existing in the.

This leak current gradually decreases due to the electric field relaxation effect of the resistive field plate 24 on the SiO ₂ film 29, but this response requires a time on the order of msec. Such a leak current is not preferable for the switching element.

On the other hand, as a method of avoiding such a phenomenon, the above-mentioned resistive field plate 24 is replaced with SiO _2.
A structure has been proposed in which the pn junction exposed surface on the surface of the junction termination region is directly deposited without interposing the film 29, and is used for some high breakdown voltage elements.

In the case of this structure, it is presumed that the effect will be slightly different depending on the material of the resistive field plate 24. For example, when SIPOS annealed at a temperature of 800 ° C. or higher is used, a negative charge is induced at the interface by the injection of majority carriers from the SIPOS film at the SIPOP-Si interface, which causes leakage current at the pn junction interface. A barrier is formed that suppresses the electric field relaxation. For this reason, it has been found that in this structure, the mutation current generated when dv / dt is applied is extremely small.

However, even with this structure, the mutation current does not disappear at all, and sometimes, as shown in FIG. 13, a pulse-like mutation current with a very small size is observed depending on the difference in wafer, lot, and the like. There is
This instability tends to increase as the device breakdown voltage increases, and it is difficult to completely suppress the mutation current even with this structure. (Fourth Conventional Example) A resistive field plate (RFP) is used as a junction termination structure of a high breakdown voltage planar semiconductor device.
, Metal field plate (MFP), RESURFED SURface Field,
A structure combining these is used.

Particularly, a coupling termination structure in which RFP and RESURF are combined is considered to be optimum. This is because the low-concentration RESURF layer spreads the depletion layer to suppress the electric field, and the concentration of the electric field is alleviated by the MFP to increase the breakdown voltage.

However, the conventional coupling termination structure in which RFP and RESURF are combined has the following problems. The material currently used as the RFP is oxygen-doped polysilicon (SIPOS), which has a high resistance that uniformly relaxes electric field concentration because the amorphous material has non-uniformity and the resistance value varies depending on the location. There was a problem as a film. Therefore, in the conventional combination of RFP and RESURF, the electric field concentration cannot be alleviated uniformly, and the breakdown voltage may be lowered depending on the location, and the breakdown voltage characteristic cannot be sufficiently improved. (Fifth Conventional Example) A Schottky barrier rectifying element utilizes the rectifying property of a Schottky barrier between a metal and a semiconductor. For example, there is a Schottky barrier diode made of n-type silicon and platinum.

In this type of Schottky barrier diode, the forward current is smaller than that of a normal pn junction and the reverse recovery time because the majority carriers flowing over the Schottky barrier are only electrons. Also has the advantage of being short. On the other hand, the reverse breakdown voltage is maintained by the depletion layer extending from the Schottky barrier to the inside of the semiconductor.

An ordinary Schottky barrier diode is
An oxide film having an opening is formed, and a Schottky barrier between metal and semiconductor is formed in the opening. But,
In such a Schottky barrier, there is a problem that the electric field is concentrated at the end portion and the breakdown voltage is lowered.

FIG. 27 is a sectional view showing a device structure of a Schottky barrier diode which can solve such a problem. In the figure, 42 indicates a high resistance n-type base layer, and an oxide film 44 is formed on the surface thereof. An opening is provided in the oxide film 44, and the platinum layer 45 is in contact with the n-type base layer 42 through the opening to form a Schottky barrier. An Al electrode (anode electrode 46) is provided on the platinum layer 45.

Then, a p-type guard ring layer 43 is formed on the surface of the n-type base layer 44 at the end of the Schottky barrier junction to alleviate the electric field concentration at the end.
In the figure, 41 is a high-concentration n-type layer, and 47 is a cathode electrode.

However, this type of Schottky barrier diode has the following problems. That is, as shown in FIG. 27, when the p-type guard ring layer 43 is provided in contact with the platinum layer 45, holes which are minority carriers than the p-type guard ring layer 43 are generated in the n-type base layer 42 or the like during device conduction. There is a problem that the reverse recovery time becomes long by injecting into the n-type semiconductor layer.

[0033]

As described above, in the conventional planar type diode, the breakdown voltage is lowered and is stable due to the influence of the fixed charges and ions generated or mixed in the element during the manufacturing process. There is a problem that a high breakdown voltage cannot be obtained.

The present invention has been made in consideration of the above circumstances, and a first object thereof is to provide a power semiconductor device having a planar type power semiconductor element capable of stably obtaining a high breakdown voltage as compared with a conventional one. Especially.

Further, as described above, in the power semiconductor device having the planar termination structure using the conventional SIPOS as the resistive field plate, there is a problem that a leakage current is generated when a sharp reverse voltage is applied. It was

The present invention has been made in consideration of the above circumstances. A second object of the present invention is to provide a power semiconductor device having a resistive field plate that does not generate a leak current even when a reverse voltage is applied suddenly. To provide.

Further, as described above, even in the power semiconductor device having the structure in which the resistive field plate is directly provided on the surface of the junction termination region, it is difficult to completely suppress the mutation current.

The present invention has been made in consideration of the above circumstances, and a third object of the present invention is to provide a resistive field plate capable of suppressing a mutation current more than before in the surface of a junction termination region without an insulating film. Another object of the present invention is to provide a power semiconductor device having a different structure.

Further, as described above, in the conventional coupling termination structure in which the resistive field plate and the RESURF are combined, there is no suitable material for the resistive field plate, so that the withstand voltage characteristic cannot be sufficiently improved. There was a problem.

The present invention has been made in consideration of the above circumstances, and a fourth object of the present invention is to provide a power semiconductor device using a resistive field plate and a RESURF having a higher withstand voltage characteristic than the conventional one. is there.

Further, as described above, in the conventional Schottky barrier diode, the p-type guard ring layer is provided on the surface of the n-type base layer in order to prevent the breakdown voltage from decreasing due to electric field concentration. During conduction, holes, which are minority carriers, are injected from the p-type guard ring layer into the n-type base layer and the like, which causes a problem that the reverse recovery time becomes long.

The present invention has been made in consideration of the above circumstances, and a fifth object thereof is to provide a power semiconductor device having a Schottky barrier structure capable of improving the breakdown voltage without incurring reverse recovery time. It is in.

[0043]

In order to achieve the first object, a power semiconductor device according to the present invention (Claim 1) is provided selectively on the surface of a high resistance first conductivity type semiconductor layer. The high-concentration second-conductivity-type semiconductor layer formed is in contact with the high-concentration second-conductivity-type semiconductor layer, and the low-concentration low-concentration semiconductor layer formed on the surface of the surrounding high-resistance first-conductivity-type semiconductor layer. A second conductive type semiconductor layer, an insulating film formed on the high-concentration and low-concentration second conductive type semiconductor layer and the high-resistance first conductive type semiconductor layer on the outside thereof, and an insulating film formed on this insulating film A first main electrode provided in the high-concentration second-conductivity-type semiconductor layer through an opening, and a surface of the high-resistance first-conductivity-type semiconductor layer opposite to the second-conductivity-type semiconductor layer A high-concentration first-conductivity-type semiconductor layer or a second-conductivity-type semiconductor layer formed in And a second main electrode provided on the first conductive type semiconductor layer or the second conductive type semiconductor layer,
A predetermined amount of charge is present at the interface between the insulating film and the low-concentration second conductivity type semiconductor layer, in the insulating film on the low-concentration second conductivity type semiconductor layer, or on the insulating film. Characterize.

The charges are preferably fixed charges composed of dangling bonds, atomic defects and the like, and trap charges. It is more preferable to selectively form a low concentration first conductivity type semiconductor layer (stopper layer) on the surface of the high resistance first conductivity type semiconductor layer outside the low concentration second conductivity type semiconductor layer.

The charge density is preferably 1 × 10 ¹¹ cm ^-2 or more. In order to achieve the second object, a power semiconductor device according to the present invention (claim 2) has a power semiconductor element formed on a semiconductor substrate and an insulating layer directly or insulated on a junction termination region of the semiconductor substrate. The resistive field plate is provided via a film and is composed of a laminated film of a polysilicon film and a silicon oxide film.

In order to achieve the third object, a power semiconductor device according to the present invention (claim 3) has a power semiconductor element formed on a semiconductor substrate and a junction termination region of the semiconductor substrate. And a resistive field plate provided through a coexisting thin film layer made of positive ions and negative ions.

In order to achieve the fourth object, a power semiconductor device according to the present invention (claim 4) includes a power semiconductor element formed on a semiconductor substrate and a junction termination region of the semiconductor substrate. A resistive field plate provided directly or via an insulating film, and selectively formed on the surface of the junction termination region under the resistive field plate,
A RESURF layer that is connected directly to the resistive field plate or through the insulating film, and an equipotential surface uniformizing member that is provided above or below the resistive field plate and is electrically connected to the resistive field plate. Is equipped with.

In order to achieve the fifth object, a power semiconductor device according to the present invention (claim 5) is an insulating film having an opening formed on a surface of a semiconductor substrate, and the inside of the opening. A metal / semiconductor compound layer formed on the surface of the semiconductor substrate and forming a Schottky barrier together with the semiconductor substrate, and an electrode provided on the metal / semiconductor compound layer are provided, and The insulating film is formed in a taper shape that becomes narrower in the depth direction of the semiconductor substrate, and an end portion of a joint portion between the metal / semiconductor compound layer and the semiconductor substrate has the tapered insulating film in the opening. It is characterized by being in contact with.

[0049]

According to the present invention (claim 1), the breakdown voltage of the pn junction constituted by the high-conductivity first-conductivity-type semiconductor layer and the high-concentration second-conductivity-type semiconductor layer is measured as a predetermined amount of charge. However, if the amount of electric charge corresponding to the difference between the measured value and the maximum value of the breakdown voltage theoretically determined from the impurity dose amount of the low-concentration second conductivity type semiconductor layer is selected, it may be mixed in the device during the manufacturing process. The effects of fixed charges and ions generated are compensated, and the maximum withstand voltage is obtained. Therefore, according to the present invention, it is possible to provide a power semiconductor device that can stably obtain a high breakdown voltage.

Further, according to the research conducted by the present inventors, when a laminated film of a polysilicon film and a silicon oxide film is used as the resistive field plate, the resistance is increased even if a sharp reverse voltage is applied. It was found that there is no time delay in the effect of the sex field plate. Therefore, according to the present invention (claim 2) based on the above knowledge, it becomes possible to provide a power semiconductor device having no leakage current even when a sharp reverse voltage is applied.

Further, according to the research conducted by the present inventors, a part of the insulating film of the semiconductor substrate having the insulating film formed on the surface is H
The pn junction surface formed on the surface of the semiconductor substrate is exposed by removing it with an HF solution such as F or NH ₄ F, and the exposed pn junction surface is exposed to a carboxylic acid solvent, a ketone solvent or phosphoric acid. When a field plate formed of SIPOS or the like is directly applied to the pn junction surface after being treated with a system solvent or a mixed solvent of these solvents and HF,
It was found that the generation of mutation current can be suppressed with good reproducibility.

This is because the pn junction surface was treated with HF, but the pn junction surface was abruptly hydrogen-terminated due to the F ⁻ group adsorbed on the surface. Positive charge that occurs when the hydrogen terminating group adsorbed on the exposed pn junction surface during the HF solution treatment is stably fixed and the hydrogen terminating group generated in the subsequent water washing step or the like is replaced with the hydrogen group. This is because it is possible to control the growth of a natural oxide film having a low level of 0.2 nm or less.

Here, in the washing step, the dissolved oxygen concentration is 50 p.
If ultrapure water of pb or less, preferably 10 ppb or less is used, the surface treatment effect is enhanced, and the growth of the natural oxide film can be made as low as about 0.1 to 0.2 nm.

As a result of a more detailed consideration, the reason why the generation of the mutation current can be suppressed with good reproducibility is that the above-mentioned surface treatment has positive ions in the natural oxide film slightly grown on the surface of the substrate and an amount of sufficiently canceling the positive ions. It was found that a coexisting thin film layer composed of negative ions was formed, and this coexisting thin film layer functions as a barrier for suppressing the junction leak current between the resistive field plate and the exposed pn junction surface.

Therefore, according to the present invention (Claim 3) based on such knowledge, a resistive field plate capable of suppressing a mutation current is provided on the surface of the junction termination region without an insulating film interposed therebetween, as compared with the prior art. A power semiconductor device having a structure can be provided.

Since the coexisting thin film layer is sufficiently thin, substantially the same effect as when the resistive field plate is provided directly on the surface of the junction termination region can be obtained. According to the invention (claim 4), the resistive field plate is SIPOS.
Even if it is made of a material with poor uniformity, etc., the uniform electric field distribution is improved by the equipotential surface equalizing member provided on the resistive field plate. A power semiconductor device can be provided.

According to the present invention (Claim 5), a metal / semiconductor compound layer and a semiconductor substrate are provided without providing a semiconductor layer such as a guard ring layer which is a generation source of minority carriers which causes a delay of reverse recovery time. Since the withstand voltage is improved by tapering the shape of the end portion of the junction portion with and, it is possible to provide a power semiconductor device having a Schottky barrier structure capable of improving the withstand voltage without incurring reverse recovery time. become.

Further, such a structure can be easily obtained by the following manufacturing method. That is, first, an insulating film having an opening at a portion which will be an end of a Schottky barrier junction is formed on a semiconductor substrate, and oxygen is ion-implanted using this insulating film as a mask.

Next, after removing a portion of the insulating film in the region where the Schottky barrier is formed, heat treatment is performed in an oxygen atmosphere to form a thin oxide film on the surface of the semiconductor substrate in the region where the Schottky barrier is formed. Along with the formation, a thick tapered oxide film is formed on the surface of the semiconductor substrate in the region where oxygen is ion-implanted, which is the end of the Schottky barrier junction.

Next, after removing the thin oxide film, a metal layer is formed on the entire surface. Next, the metal layer is reacted with the semiconductor substrate by heat treatment to form a metal / semiconductor compound layer on the surface of the semiconductor substrate.

Finally, a metal electrode is provided on this metal / semiconductor compound layer. At this time, the metal layer may be completely reacted, or an unreacted portion may be left. The unreacted metal layer is used as a metal electrode.

[0062]

The details of the present invention will be described below with reference to the illustrated embodiments. (First Embodiment) FIG. 1 is a sectional view showing an element structure of a planar diode according to a first embodiment of the present invention.

This will be described according to the manufacturing process. First, a substrate in contact with the n ⁺ type layer 105 and having the n ⁻ type silicon layer 101 formed thereon is prepared. Note that a p ⁺ type layer (high-concentration second conductivity type semiconductor layer) may be used instead of the n ⁺ type layer 105.

Next, after depositing a silicon oxide film 106 on the surface of the n ^-- type silicon layer 101, an opening is formed in the silicon oxide film by a photolithography technique and an etching technique.

Then, using this as a mask, p-type impurities are ion-implanted, and then annealed and diffused to form a p ⁺ -type layer 102. Then, a low-concentration p ⁻ -type layer 103 as a resurf layer is formed around the p ⁺ -type layer 102 by diffusion in a similar process, and then an n ⁻ -type silicon layer is separated from the p ⁻ -type layer 103 by a predetermined distance. A high-concentration n ⁺ -type layer 104 as a stopper layer is diffused and formed on the surface of 101.

Next, a silicon oxide film 106 is further deposited on the entire surface of the substrate by the CVD method, and then the p ^-- type layer 103, n ⁺
The silicon oxide film 6 in the region of the mold layer 104 is removed. Then, an Al film is deposited on the entire surface, and the Al film is patterned to form an anode electrode 107 and a stopper electrode 108, and a cathode electrode 109 is formed on the n ⁺ type layer 105. Here, the impurity dose amount of the p ⁻ type layer 103 is 1.4 × 10 4 which corresponds to the point A shown in the characteristic diagram of FIG.
It is set to ¹² cm ^-2 .

Therefore, if the electrodes 107, 108, 1
Unless fixed charges or ions are generated or mixed in the diode before the formation step of 09 is completed, a withstand voltage of about 1500 V should be obtained.

Next, the anode electrode 107 and the cathode electrode 1
09 is electrically connected to a breakdown voltage tester, and the breakdown voltage of the pn junction between the n ⁻ type silicon layer 101 and the p ⁺ type layer 102 is measured. Here, the actual measured value is compared with the maximum value of the breakdown voltage obtained from FIG. 7 from the impurity dose amount of the p ⁻ -type layer 103, and if there is a difference, the amount of charge (correction charge) corresponding to the difference.
Is introduced into the interface between the silicon oxide film 106 and the p ⁻ type layer 103, or into or on the silicon oxide film 106 on the p ⁻ type layer 103.

For example, if the measured value of the breakdown voltage is 1000 V corresponding to the point B in FIG. 7, the positive charge 111 of 3 × 10 ¹¹ cm ⁻² corresponding to the difference in the amount of impurities at the points A and B is introduced.
As a result, 3 × 10 ¹¹ is formed on the surface of the p ⁻ -type layer 103.
The negative charge 112 of cm ⁻² is induced, and the fixed charge mixed and generated during the manufacturing process and the positive charge of the ions are canceled, and p
The effective impurity amount of the ⁻ type layer 103 corresponds to the point A.
It is returned to 4 × 10 ¹² cm ^-2 .

FIG. 1 shows a method of irradiating an electron beam on the silicon oxide film 106 as a method of introducing charges. By irradiating with the electron beam 110, holes are trapped at the interface between the silicon (p ⁻ type layer 103) and the silicon oxide film 106, and this acts as positive fixed charges.

FIG. 2 is a characteristic diagram showing the relationship between the electron beam irradiation amount and the positive charge amount introduced by the electron beam irradiation amount. When the accelerating voltage is set to 10 MeV and the electron beam is irradiated from above the silicon oxide film 106, the electron beam irradiation amount required to introduce the positive fixed charge 111 of 3 × 10 ¹¹ cm ⁻² is shown in the figure. It is about 2 × 10 ¹² cm ^-2 indicated by the point A.

The electron beam may be applied to the entire surface of the device or may be applied only to the region of the p ⁻ type layer 103. (Second Embodiment) FIG. 3 is a sectional view showing an element structure of a planar diode according to a second embodiment of the present invention.
The parts corresponding to those of the planar diode in FIG. 1 are designated by the same reference numerals (including those with different subscripts) as in FIG. 1, and detailed description thereof will be omitted.

The feature of this embodiment is that the entire element region except a part of the p ⁺ -type layer 102a and the p ⁻ -type layer 103 is covered with the blocking plate 114, and the electron beam 1 is emitted from above the blocking plate 114.
To irradiate 10.

As a result, it becomes possible to introduce charges into only a specific region (a part of the p ⁺ type layer 102a and the p ⁻ type layer 103 in this embodiment). The opening of the blocking plate 114 is not limited to the region of the p ⁻ type layer 103, and may be, for example, the junction termination region. Further, for example, a lead thick plate can be used as the blocking plate against electron beam irradiation, and an aluminum plate can be used as the blocking plate against proton irradiation or helium ion irradiation. (Third Embodiment) FIG. 4 is a sectional view showing the device structure of a planar diode according to the third embodiment of the present invention.

The feature of this embodiment is that the silicon oxide film 106 is used.
By forming the fixed charge film 113 having a predetermined amount of positive charges on the p ⁻ type layer 103 and the silicon oxide film 106.
The purpose is to induce a predetermined amount of positive charge at the interface with and to obtain the maximum breakdown voltage.

As the fixed charge film 113, for example,
A fluororesin film such as polyvinylidene fluoride, a crystal film having spontaneous polarization such as barium titanate or lithium niobate, or an ionic coating film such as a quaternary ammonium salt can be used. (Fourth Embodiment) FIG. 5 is a process flow showing a method for manufacturing a power semiconductor device according to a fourth embodiment of the present invention.

First, each diffusion layer is formed (step S
1), and then each electrode is formed (step S2). Then, in order to control the lifetime, an electron beam is applied to the silicon substrate on which a desired diffusion layer is formed via a silicon oxide film (step S3). The irradiation amount is, for example, 5
It is × 10 ¹³ cm ^-2 . Then, annealing is performed for the purpose of eliminating charges generated at the interface between the silicon oxide film and the silicon substrate by electron beam irradiation (step S4). This is because the threshold voltage of the MOSFET fluctuates and the leak current of the pn junction increases if the charge remains.

Next, similarly to the first and second embodiments, withstand voltage measurement is performed (step S5), and then electron beam irradiation for introducing correction charges is performed (step S6). Here, the characteristic feature is that after the electron beam irradiation for introducing the correction charge is performed, the correction charge is accumulated and remains without performing a process such as a heat treatment for erasing the correction charge. is there.

The sequence is not limited to this embodiment. For example, the breakdown voltage measurement is performed before the electron beam irradiation for lifetime control is performed, and the electron beam irradiation amount for introducing the correction charge is checked in advance. It is also possible to irradiate an electron beam of an amount obtained by subtracting in order to control the lifetime. (Fifth Embodiment) FIG. 8 is a sectional view showing an element structure of a planar diode according to a fifth embodiment of the present invention.

In the figure, reference numeral 203 denotes a low-concentration n-type silicon substrate (cathode layer).
A high-concentration p-type anode layer 201 is diffused and formed in the central portion of the surface of 03.

A low-concentration p-type RESURF layer 202 is diffused around the p-type anode layer 201 in contact therewith, and a high-concentration n-type stopper layer 204 is selectively formed on the outermost edge of the substrate outside the p-type RESURF layer 202. Diffused.

An oxide film 206 is formed on the surface of the n-type silicon substrate 201 on which the p-type anode layer 201 and the like are formed. Further, the p-type anode layer 201 and the n-type stopper layer 204 are formed through the openings formed in the oxide film 206 for the anode electrode 208 and the stopper electrode 209, respectively.
It is provided in.

Anode electrode 208 and stopper electrode 209
The resistive field plate 2 made of a laminated film of a polysilicon film and a silicon oxide film is formed on the oxide film 206 between
07 is provided.

On the other hand, the cathode electrode 2 is formed on the back surface of the n-type silicon substrate 203 via the high-concentration n-type buffer layer 205.
10 are provided. FIG. 9 shows changes with time in voltage and current when a reverse voltage of 2800 V is sharply applied to the diode of this embodiment.

A current 211 was observed which increased sharply at the beginning of the voltage application and sharply decreased. This is the displacement current,
It is observed in every element. However, no leakage current was observed.

FIG. 10 is almost the same as the structure shown in FIG. 8 except that SIP is used as the material of the resistive field plate.
FIG. 6 shows changes in voltage and current with time when a reverse voltage of 1700 V is sharply applied to a conventional diode using an OS.

In addition to the displacement current 211, a leakage current 212 was observed, which was not as steep as the displacement current, but increased with time and then decreased. This leakage current increased with increasing applied voltage.

This leakage current is a phenomenon peculiar to the case where SIPOS is used as the material of the resistive field plate, and when a steep reverse voltage is applied to the diode, SI
This is because there is a time delay in the flow of current through the POS.

As described above, according to this embodiment, by using the laminated film of the polysilicon film and the silicon oxide film as the resistive feed plate, even if a steep reverse voltage is applied, the resistive feed plate There is no time delay in the current flowing through the plate, and it is possible to obtain a high breakdown voltage planar diode in which no leakage current occurs.

In the present embodiment, the case of the planar type diode as the power element has been described, but the present invention is also effective for the transistor and the thyristor having the planar junction termination structure of the same structure. (Sixth Embodiment) FIG. 14 is a sectional view showing the structure of a power semiconductor device according to the sixth embodiment of the present invention. The present inventors formed the power semiconductor device having such a structure by six manufacturing methods, and examined the characteristics of each power semiconductor device (six samples).

An n ⁺ type buffer layer 307 and a p type emitter layer 308 are selectively formed on one surface of the n type silicon substrate 306.
Are sequentially formed, and then the p ⁺ type guard ring layer 301, the p ⁻ type RESURF layer 302, and the n ⁺ type stopper layer 3 are formed on the other surface.
03, thick field oxide film 309, gate oxide film 31
A MOS gate region consisting of 1 and the polysilicon electrode 312 is formed by using the usual photo-etching technique and etching technique.

Next, the surface of the polysilicon electrode 312 is oxidized, the p-type base layer 313 is formed using the edge of the polysilicon electrode 312 as a mask, and then a predetermined region of the field oxide film 309 is subjected to photolithography. The opening is made by etching using NH ₄ F.

The process up to this point is the same for each sample. Next, an exposed p made of the p ⁺ type guard ring layer 301, the p ⁻ type RESURF layer 302 and the n type silicon substrate 306.
The n-junction surface is treated with different treatment liquids to form a plurality of 6 types of samples.

One is H ₂ O ₂ : HCl: H ₂ O = 1:
CH ₃ CO which is a carboxylic acid-based treatment liquid treated with a treatment liquid (SC-2 treatment) consisting of 1: 6 (Sample 1)
Treated with OH (Sample 2), one with H ₃ PO ₄ which is a phosphoric acid type treatment liquid (Sample 3), one with (CH ₃ ) ₂ CO which is a ketone type treatment liquid (Sample 4) One is treated with a mixed solution of CH ₃ COOH and dilute HF (Sample 5) and one is treated only with dilute HF (Sample 6).

After that, the field oxide film 3 of each sample
A SIPOS film 304, which is a semi-insulating film and has an oxygen concentration of about 20%, is deposited in the opening of 09 by a film forming method such as LPCVD, and is patterned so that the SIPOS film 304 remains only in a predetermined region.

Next, ion implantation is performed using the polysilicon gate electrode 312 of each sample as a mask to form an n-type emitter layer 315, and then a CVD oxide film 304 such as BPSG is deposited on the entire surface.

Finally, the CVD oxide film 304 of each sample
After forming a contact hole 310 and the like in the above, a cathode electrode 317 and a stopper electrode 305 are formed. A voltage was applied between the anode electrode 316 and the cathode electrode 17 to each of the six types of samples thus obtained by dv / dt.
A test of applying a voltage under the condition of 1000 v / μsec was performed.

As a result, in Sample 1, the mutation current remarkably occurred as shown in FIG. In addition, a phenomenon similar to that of Sample 1 was observed in a part of Sample 6. On the other hand, in Samples 2 to 5, almost no occurrence of the mutated current at the time of dv / dt was observed, and good withstand voltage characteristics were obtained. Further, in Samples 2 to 5, in the water washing step after the treatment of the exposed pn junction surface with the treatment liquid, no mutation current was observed even when ultrapure water having a dissolved oxygen concentration of 5 ppb was used, and particularly good reverse breakdown voltage was observed. It was confirmed that the characteristics could be obtained.

The reason why such good results were obtained is that in the case of the surface treatments of Samples 2 to 5, the coexisting thin film layer composed of positive ions and negative ions was more stably and reproducibly formed on the substrate surface. It is considered that this coexisting thin film layer is formed and functions as a barrier for suppressing a junction leak current between the SIPOS film and the exposed pn junction surface. (Seventh Embodiment) FIG. 15 is a plan view of a power semiconductor device according to a seventh embodiment of the present invention. In addition, FIG.
It is an AA 'sectional view of the same semiconductor device for electric power.

On the high-resistance n-type semiconductor substrate 401, an element region in which a desired power semiconductor element (for example, diode, transistor, FET, IGBT, thyristor) is formed and a junction termination region surrounding them are formed. There is.

On the surface of the n-type semiconductor substrate 401 in the junction termination region, a high-concentration p-type guard ring layer 403, a low-concentration p-type RESURF layer 402 in contact with this p-type guard ring layer 403, and this p-type RESURF. A high-concentration n-type stopper layer 404 is formed apart from the layer 402 by a predetermined distance. These are formed concentrically with respect to the element region. Note that the p-type guard ring layer 403 may be plural as shown in FIG.

An insulating film 405 is provided on the region from the p-type guard ring layer 403 to the n-type stopper layer 404. On the p-type RESURF layer 402 and the insulating film 405 on the n-type semiconductor substrate 401, a resistive field plate 406 made of a semi-insulating material such as SIPOS is provided. This resistive field plate 406 is connected to the metal field plate 407 through the p
It is connected to the type guard ring layer 403 and the n-type stopper layer 404.

Furthermore, the resistive field plate 406
A conductive ring 408 formed of a conductive material such as Al or polysilicon is provided on the top. The conductive ring 408 is formed in an annular shape so as to be electrically connected to the resistive field plate 406 and symmetrically surround the element region.

The resistive field plate 406 is SIP
When formed of an amorphous material such as OS, the electric field relaxation by the resistive field plate 406 becomes nonuniform. However, in this embodiment, since the conductive ring 408 is provided on the resistive field plate 406, the potential is always constant on this conductive ring 408. Therefore, the resistive field plate 40
Regardless of the material of No. 6, the electric field distribution in the junction termination region is made more uniform than in the conventional case, and the breakdown voltage is improved.

In the actual device, a passivation film is provided on the junction termination region to suppress discharge on the surface of the junction termination region. (Eighth Embodiment) FIG. 17 is a sectional view of a junction termination region of a power semiconductor device according to an eighth embodiment of the present invention. Note that a portion corresponding to the power semiconductor device in FIG.
The same reference numeral as 6 is assigned and detailed description thereof is omitted.

The difference of this embodiment from the seventh embodiment is that the resistive field plate 406 is formed directly on the junction termination region. Resistive field plate 406
This is good because the resistance is high originally. In this embodiment, the same effect as that of the seventh embodiment can be obtained. (Ninth Embodiment) FIG. 18 is a sectional view of a junction termination region of a power semiconductor device according to a ninth embodiment of the present invention.

The present embodiment is different from the seventh embodiment in that the number of conductive rings 408 is increased from two to four. According to this embodiment, the resistive field plate 4
Since the conductive ring 408 is evenly arranged on the upper side of 06, the uniformity of the electric field distribution is further advanced and a higher breakdown voltage is obtained. (Tenth Embodiment) FIG. 19 is a sectional view of a junction termination region of a power semiconductor device according to a tenth embodiment of the present invention.

The present embodiment differs from the seventh embodiment in that a protective film 409 is provided on the resistive field plate 406 to stabilize the characteristics of the resistive field plate 406. The conductive ring 408 is formed on the resistive field plate 40 through the opening formed in the protective film 409.
Connected to 6. Since the resistive field plate 406 often uses an amorphous material such as SIPOS, if it is covered with a protective film 409 in advance, its characteristics can be kept stable, and it is higher than that of the conductive ring 408 alone. Withstand voltage can be realized. (Eleventh Embodiment) FIG. 20 is a plan view of a power semiconductor device according to an eleventh embodiment of the present invention.

The difference of this embodiment from the seventh embodiment is that the shape of the element region is a quadrangle. Regardless of the shape of the element region, basically, a conductive member as an equipotential surface equalizing member such as the conductive ring 408 should be arranged at a position equidistant from the outermost circumference of the element region. For example, the electric field distribution can be made uniform and the breakdown voltage can be improved. (Twelfth Embodiment) FIG. 22 is a sectional view of a junction termination region of a power semiconductor device according to a twelfth embodiment of the present invention.

The present embodiment differs from the seventh embodiment in that the conductive ring 4 is provided below the resistive field plate 406.
08 is installed. Also in this embodiment, the effect of improving the breakdown voltage can be obtained, and if the constituent semiconductor of the n-type semiconductor substrate 401 is used as the material of the conductive ring 408, the compatibility with the process is further improved. For example, when a silicon substrate is used, polysilicon or the like is used. (Thirteenth Embodiment) FIG. 23 is a sectional view of a junction termination region of a power semiconductor device according to a thirteenth embodiment of the present invention.

This embodiment is different from the twelfth embodiment in that
This is because the resistive field plate 406 was formed directly on the junction termination region without using the insulating film. Also in this embodiment, the same effect as in the twelfth embodiment can be obtained.

As in the twelfth and thirteenth embodiments,
Conductive ring 408 and resistive field plate 407
When it is disposed under the lower part of the above, the adhesion between the conductive ring 408 and the resistive field plate 407 is improved. In particular, when SIPOS is used as the resistive field plate, the effect is high, and the breakdown voltage can be more reliably expected to improve. (Fourteenth Embodiment) FIG. 24 is a sectional view of a junction termination region of a power semiconductor device according to a fourteenth embodiment of the present invention.

The feature of this embodiment is that the voltage applied to the conductive ring 408 is detected by the detection circuit 410, and when an abnormal voltage is applied to the element, the protection circuit 411 is activated to prevent dielectric breakdown. To prevent.

Although it is possible to detect the voltage from the main circuit in the element region, a large current is usually flowing in the main circuit,
A fairly high impedance detection circuit is required. On the other hand, since a large current does not originally flow in the junction termination region and the resistive field plate 406 has high impedance, a low impedance detection circuit can be used in the present embodiment, and abnormal voltage can be detected. Easy to do.

In the seventh to fourteenth embodiments, the element region is surrounded by a single connecting conductive member such as the conductive ring 408 in order to make the electric field distribution uniform. Providing multiple conductive members at equidistant positions,
The element region may be surrounded by a plurality of conductive members.

Although the seventh to fourteenth embodiments assume vertical power semiconductor elements, horizontal power semiconductor elements may be used. (Fifteenth Embodiment) FIGS. 25 and 26 show the fifteenth embodiment of the present invention.
6A to 6C are process cross-sectional views showing the method of manufacturing the Schottky barrier diode according to the example of FIG.

First, as shown in FIG. 25A, a vapor phase growth method (CVD method) is performed on a high-concentration n-type silicon substrate 501.
On the surface of the epitaxial substrate formed by epitaxially growing the low concentration n-type silicon layer 502.
3 is formed.

Next, as shown in FIG. 25B, the thermal oxide film 503 near the region 504 which will be the end of the Schottky barrier junction in the future is selectively removed. Next, as shown in FIG. 25C, oxygen ions 505 are added to the n-type silicon layer 5 by an ion implantation method using the remaining thermal oxide film 503 as a mask.
The entire surface of 02 is irradiated with oxygen ions 505 in a region which will be an end of the Schottky barrier junction in the future.

Next, as shown in FIG. 25D, after removing the thermal oxide film 503 in the region where a Schottky barrier will be formed in the future, as shown in FIG. 25E, a diffusion furnace in an oxygen atmosphere is used. By maintaining the temperature at a high temperature, the surface of the n-type silicon layer 502 is oxidized, and at the same time, the implanted oxygen ions 505 are redistributed and oxidized.

As a result, n in the region where a Schottky barrier will be formed in the future where the oxygen ions 505 have not been implanted.
A thin thermal oxide film 506a is formed on the surface of the mold silicon layer 502.

Further, on the surface of the n-type silicon layer 502 near the end of the Schottky barrier junction where the oxygen ions 505 are implanted in the future, there is a concentration peak at a certain depth from this surface and it is distributed. The implanted oxygen ions 505 are oxidized while being diffused laterally or obliquely in the vertical direction and are advanced from the surface. As a result, as shown in FIG. 25F, which is an enlarged view, a thick thermal oxidation having a tapered shape is performed. A film 506b is formed. The thermal oxide film 506b is integrated with the thermal oxide film 503.

Next, as shown in FIG. 26A, after removing the thin thermal oxide film 506a in the region where the Schottky barrier is formed, a platinum layer 507 which is a barrier metal and an Al film 508 which is an electrode metal are removed. The platinum layer 507 and the Al film 508 in unnecessary portions are sequentially removed and then selectively removed.

Thereafter, sintering is performed at a high temperature to cause the platinum layer 507 and the n-type silicon layer 502 to react with each other to form a platinum silicide layer 509. This platinum silicide layer 5
A Schottky barrier is formed by the junction between 09 and the n-type silicon layer 502 below it.

Although the platinum layer 507 is not completely reacted and the unreacted portion is used as a barrier metal in this embodiment, the platinum layer 507 may be completely reacted. Finally,
As shown in FIG. 26B, the cathode electrode 510 is formed on the back surface of the n-type silicon layer 502, and the Schottky barrier diode is completed.

According to this embodiment, as shown in the enlarged view of FIG. 26C, the Schottky barrier junction 510 (the junction between the platinum silicide layer 509 and the n-type silicon substrate 501) is in contact with the end. Since the thick thermal oxide film 506 is formed in a tapered shape, the end of the Schottky barrier junction 510 is inclined and has a bevel structure.

Therefore, in this embodiment, the depletion layer easily grows when a reverse voltage is applied, and the electric field at the end of the Schottky barrier junction 510 is eliminated without using a guard ring or the like that causes the generation of minority carriers. You can relax your concentration.

Therefore, the breakdown voltage can be improved without delaying the reverse recovery time. Moreover, since the method of forming the Schottky barrier junction 510 is simple, there is no problem that the number of processes increases or the process becomes complicated.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. . Further, various combinations of the above embodiments may be made. In addition, various modifications can be made without departing from the scope of the present invention.

[0129]

As described above in detail, the present invention (Claim 1)
According to this, the breakdown voltage of a pn junction constituted by a high-conductivity first-conductivity-type semiconductor layer and a high-concentration second-conductivity-type semiconductor layer is measured as a predetermined amount of electric charge, and the measured value and the low-concentration first-conductivity semiconductor layer are measured. 2 By selecting an amount of charge that corresponds to the difference between the theoretical maximum withstand voltage determined from the impurity dose of the conductivity type semiconductor layer and the effects of fixed charges or ions mixed in or generated in the device during the manufacturing process, As a result, it is possible to provide a power semiconductor device having a maximum breakdown voltage.

Further, according to the present invention (claim 2), since the laminated film of the polysilicon film and the silicon oxide film is used as the resistive field plate, even if the steep reverse voltage is applied, the leakage current is increased. It becomes possible to provide a power semiconductor device without power consumption.

According to the present invention (claim 3), by providing a coexisting thin film layer composed of positive ions and negative ions between the resistive field plate and the junction termination region,
It becomes possible to provide a power semiconductor device capable of suppressing a variation current.

Further, according to the present invention (claim 4), even if the resistive field plate is made of a material having poor uniformity such as SIPOS, the equipotential surface provided on the resistive field plate is uniform. Since the uniformization of the electric field distribution is improved by the rectifying member, it is possible to provide a power semiconductor device having more excellent withstand voltage characteristics than ever before.

According to the present invention (Claim 5), a metal / semiconductor compound layer is formed without providing a semiconductor layer such as a guard ring layer which is a generation source of minority carriers which causes a delay of reverse recovery time. Since the withstand voltage is improved by tapering the shape of the end portion of the junction with the semiconductor substrate, a power semiconductor device having a Schottky barrier structure that can improve the withstand voltage without incurring reverse recovery time is provided. become able to.

[Brief description of drawings]

FIG. 1 is a sectional view showing an element structure of a planar diode according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between an electron beam dose and a positive charge amount introduced by the electron beam dose.

FIG. 3 is a sectional view showing an element structure of a planar diode according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing an element structure of a planar diode according to a third embodiment of the present invention.

FIG. 5 is a process flow showing a method for manufacturing a power semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing an element structure of a conventional planar diode.

FIG. 7 is a characteristic diagram showing the relationship between the impurity concentration of the RESURF layer and the breakdown voltage.

FIG. 8 is a sectional view showing an element structure of a planar diode according to a fifth embodiment of the present invention.

9 is a diagram showing changes in voltage and current with time when a reverse voltage of 2800 V is sharply applied to the diode of FIG.

FIG. 10 is a diagram showing changes over time in voltage and current when a reverse voltage of 1700 V is sharply applied to a conventional diode.

FIG. 11 is a sectional view showing an example of a conventional junction termination region.

FIG. 12 is a diagram for explaining the problem of the conventional resistive field plate.

FIG. 13 is a view for explaining a problem of another conventional resistive field plate.

FIG. 14 is a sectional view showing the structure of a power semiconductor device according to a sixth embodiment of the present invention.

FIG. 15 is a plan view of a power semiconductor device according to a seventh embodiment of the present invention.

16 is a cross-sectional view taken along the line AA ′ of the power semiconductor device of FIG.

FIG. 17 is a sectional view of a junction termination region of a power semiconductor device according to an eighth embodiment of the present invention.

FIG. 18 is a sectional view of a junction termination region of a power semiconductor device according to a ninth embodiment of the present invention.

FIG. 19 is a sectional view of a junction termination region of a power semiconductor device according to a tenth embodiment of the present invention.

FIG. 20 is a plan view of a power semiconductor device according to an eleventh embodiment of the present invention.

FIG. 21 is a cross-sectional view showing another pattern of the p-type guard ring layer.

FIG. 22 is a sectional view of a junction termination region of a power semiconductor device according to a twelfth embodiment of the present invention.

FIG. 23 is a sectional view of a junction termination region of a power semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 24 is a sectional view of a junction termination region of a power semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 25 is a process sectional view showing the manufacturing method of the first half of the Schottky barrier diode according to the fifteenth embodiment of the present invention.

FIG. 26 is a process sectional view showing the manufacturing method of the latter half of the Schottky barrier diode according to the 15th embodiment of the present invention.

FIG. 27 is a sectional view showing an element structure of a conventional Schottky barrier diode.

[Explanation of symbols]

101 ... N ⁻ type silicon layer (high resistance first conductivity type semiconductor layer) 102 ... P ⁺ type layer (high concentration second conductivity type semiconductor layer) 103 ... P ⁻ type layer (low concentration second conductivity type semiconductor layer) Layer 104 ... n ⁺ type layer (stopper layer) 105 ... n ⁺ type layer 106 ... silicon oxide film 107 ... anode electrode (first main electrode) 108 ... stopper electrode 109 ... cathode electrode (second main electrode) 110 Electron beam 111 ... Fixed charge 112 ... Charge 201 ... P-type anode layer 202 ... P-type RESURF layer 203 ... N-type silicon substrate (cathode layer) 204 ... N-type stopper layer 205 ... N-type buffer layer 206 ... Oxide film 207 ... resistive field plate 208: anode electrode 209 ... stopper electrode 210 ... cathode electrode 301 ... p ⁺ -type guard ring layer 302 ... p ^- -type RESURF layer 303 ... n ⁺ -type stopper layer 304 ... SIPOS film (resistive field plate) 305 ... Stopper electrode 306 ... N type silicon substrate 307 ... N ⁺ type buffer layer 308 ... P type emitter layer 309 ... Field oxide film 310 ... Contact hole 311 ... Gate oxide film 312 ... Poly Silicon electrode 313 ... P-type base layer 315 ... N-type emitter layer 317 ... Cathode electrode 318 ... Interlayer insulating film 401 ... N-type semiconductor substrate 402 ... P-type RESURF layer 403 ... P-type guard ring layer 404 ... N-type stopper layer 405 ... Insulating film 406 ... Resistive field plate 407 ... Metal field plate 408 ... Conductive ring (equipotential surface equalizing member) 501 ... N-type silicon substrate 502 ... N-type silicon layer 503 ... Thermal oxide film 504 ... Schottky barrier junction Which is the end of 505 ... Oxygen ion 506a ... Thin thermal oxide film 506b ... Thick thermal oxide film 507 ... Platinum layer 508 ... Al film 509 ... Platinum silicide layer 510 ... Cathode electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuya Nakayama, Komukai-shi, Kawasaki-shi, Kanagawa 1 Komushiba-shi, Kanagawa Prefecture, Ltd. Research & Development Center, Toshiba Corporation (72) Inventor, Shigeru Hasegawa Komukai, Kawasaki-shi, Kanagawa Toshiba Town No. 1 Inside Toshiba Research and Development Center

Claims (5)

[Claims] 1. A high-concentration second-conductivity-type semiconductor layer selectively formed on the surface of a high-resistance first-conductivity-type semiconductor layer, and a region surrounding and in contact with the high-concentration second-conductivity-type semiconductor layer. Low concentration second conductivity type semiconductor layer formed on the surface of the high resistance first conductivity type semiconductor layer, the high concentration and low concentration second conductivity type semiconductor layer and the high resistance first layer outside thereof An insulating film formed on the first-conductivity-type semiconductor layer; a first main electrode provided on the high-concentration second-conductivity-type semiconductor layer through an opening formed in the insulating film; A high concentration first conductivity type semiconductor layer or a second conductivity type semiconductor layer formed on the surface of the high resistance first conductivity type semiconductor layer on the side opposite to the conductivity type semiconductor layer; A second main electrode provided on the semiconductor layer or the second conductivity type semiconductor layer, A predetermined amount of electric charge exists in an interface between an insulating film and the low-concentration second conductivity type semiconductor layer, in the insulating film on the low-concentration second conductivity type semiconductor layer, or on the insulating film. Power semiconductor device. 2. A power semiconductor element formed on a semiconductor substrate, and a resistor formed on a junction termination region of the semiconductor substrate directly or via an insulating film, the resistor being composed of a laminated film of a polysilicon film and a silicon oxide film. Power semiconductor device, comprising a conductive field plate. 3. A power semiconductor element formed on a semiconductor substrate, and a resistive field plate provided on a junction termination region of the semiconductor substrate via a coexisting thin film layer of positive ions and negative ions. A power semiconductor device characterized by the following. 4. A power semiconductor element formed on a semiconductor substrate, a resistive field plate provided directly or via an insulating film on a junction termination region of the semiconductor substrate, and a portion below the resistive field plate. A RESURF layer selectively formed on the surface of the junction termination region and connected to the resistive field plate directly or via the insulating film; and a RESURF layer provided above or below the resistive field plate. An equipotential surface equalizing member electrically connected to the power semiconductor device. 5. An insulating film having an opening formed on the surface of a semiconductor substrate, and a metal / semiconductor compound layer formed on the surface of the semiconductor substrate in the opening and forming a Schottky barrier together with the semiconductor substrate. An electrode provided on the metal / semiconductor compound layer, wherein the insulating film in the inner portion of the opening is formed in a taper shape that becomes thinner in a depth direction of the semiconductor substrate, A power semiconductor device, wherein an end of a junction between the semiconductor compound layer and the semiconductor substrate is in contact with the tapered insulating film of the opening.