JPH08254570A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit incorporating a macro cell which can be observed easily and surely in a short time. CONSTITUTION: A semiconductor integrated circuit (e.g. an ASIC including a standard cell) 100 comprising a plurality of macro cells (RAM) R1 , R2 ,..., is provided with I/O parts I1 , O1 for inputting a test data comprising a predetermined number of bits from an external terminal (D1 /D0 ) and outputting an output data read out from the macro cell to the external terminal. The semiconductor integrated circuit further comprises dedicated test circuits (e.g. parallel I/O shift registers) I2, I3,..., O2, O3,... for feeding a test data inputted from the I/O part to each macro cell and transferring the output data therefrom to the I/O part.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ASIC (Applicatio)
In particular, it relates to the measurement of semiconductor integrated circuits such as n Specific IC)
cell) and other large-scale LSIs for improving macrocell observation technology.

In the field of recent ASICs, a plurality of basic cells form a circuit unit (macrocell) having a certain logical function, and a plurality of these macrocells are combined to individually design an IC for a specific application. Many cells are used. In particular, RA with a predetermined capacity
Large scale LS by adopting M as macro cell
Attempts have been made to facilitate the design of I.

In the LSI having these RAMs as macro cells, a technical problem is how to inspect and measure the macro cells in which the built-in RAM is a unit. this is,
This is because it is difficult to pull out the I / O terminals of all the RAM macro cells to the outside of the package because the size of the LSI package is limited. Therefore, built-in RAM
Studies have been conducted on methods for measuring these macrocells without pulling out the I / O terminals of the macrocells to the outside.

[0004]

2. Description of the Related Art Conventionally, as a method of observing a semiconductor integrated circuit including a macrocell of a built-in RAM (quality inspection, etc.), a boundary scan design method, a method of observing by activating peripheral logic, etc. Was used.

Here, the boundary scan method is a method for facilitating the test of a semiconductor integrated circuit, in which a shift register (flip-flop) for performing a scan operation is connected to an I / O terminal of a circuit under test. . In Figure 7,
1 shows a conventional semiconductor integrated circuit using a boundary scan method.

As shown in FIG. 7, in the boundary scan method, test dedicated circuits (I _{11 to} I) are provided on the input side and the output side of the built-in RAM (R _{11 to} R ₁₃ ) which are macro cells.
₁₃ , O _{11 to} O ₁₃ : Here, a flip-flop (FF)
Shift register) is provided. Also, dedicated test circuits L _{11 to} L ₁₆ are provided for peripheral logics provided with a specific function in response to a user's request.
The test dedicated circuits related to the respective built-in RAMs and the peripheral logic are connected to each other in cascade.

When testing the conventional semiconductor integrated circuit 200, data for a specific scan (scan) is input from an external input terminal.
data), the scan clock for the shift (scan clock)
Is supplied to the line in which each test dedicated circuit is connected in cascade. The input data is stored in the built-in RAM, and the stored data is output to the test dedicated circuit on the output side. The data read to the test-dedicated circuit on the output side is externally read according to the scan clock. And
The built-in RAM is measured by changing the input scan data in various ways and inspecting the read data.

Further, in the method of activating peripheral logic, a specific activation signal is supplied to the peripheral logic existing between the built-in RAM and the external terminal of the LSI so that the peripheral logic does not substantially go through the peripheral circuit. The contents of the internal RAM are directly observed from the outside.

[0009]

However, in the conventional boundary scan method, since a plurality of types of macro cells are connected in series, a large number of test patterns are required for reading scan data. Further, it is difficult to identify the defective bit and defective address from the read data pattern and detect which macro cell has a defect.

Further, the observing method by activating the peripheral logic has a problem that the activation pattern for directly observing data from the outside becomes complicated when the built-in RAM is located far below the peripheral logic. . In addition, the peripheral logic is used in various ways according to the user's request, which causes a problem that the activation pattern is likely to be defective.

Therefore, in view of the above problems, it is an object of the present invention to provide a semiconductor integrated circuit which enables easy observation of a built-in macro cell in a short time.

[0012]

FIG. 1 shows a principle explanatory view of a semiconductor integrated circuit of the present invention. FIG. 1A shows a structure of a semiconductor integrated circuit of the present invention, and FIG. 1B is an example of a timing chart showing its operation.

According to a first aspect of the invention, in a semiconductor integrated circuit (for example, an ASIC such as a standard cell) 100 including a plurality of macro cells (RAM or the like) R ₁ , R ₂ , ..., External terminals (D _I / D). _O ) is provided with input / output units I ₁ and O ₁ for inputting test data having a predetermined number of bits and outputting output data read from the macrocell to an external terminal. A test-dedicated circuit (for example, parallel input / output shift register) I ₂ , I ₃ , which supplies the test data input from the output unit to the macro cell and transfers the output data output from the macro cell to the input / output unit, , O ₂ , O ₃ , ...

According to a second aspect of the invention, in a semiconductor integrated circuit (for example, an ASIC such as a standard cell) 100 including a plurality of macro cells (RAM or the like) R ₁ , R ₂ , ... An external input circuit I ₁ for inputting test data consisting of the number of bits in parallel from an external input terminal D _I and serially outputting the input test data based on a scan clock is provided. The test data is serially input based on the clock SC, the input test data is serially output while being sequentially shifted, and the external input circuit is based on the instruction signal RC for instructing input / output to the macro cell. Input test data consisting of the same number of bits as the number of input bits of Circuit I ₂ , I ₃ , ...

The serial output of the external input circuit is serially input to the input test dedicated circuit to be shifted first, and the serial output of one input test dedicated circuit is serially input to the other input test dedicated circuit. So as to be input to the input test circuit.

In FIG. 1, the connection line between the input test dedicated circuits transfers the scan clock SC and the test data. The invention described in claim 3 is the invention according to claim 2.
In the semiconductor integrated circuit described in the paragraph 1, when a setting signal for setting the test data is input to the macro cell, the semiconductor integrated circuit operates as a supply circuit for directly supplying the test data from the external input terminal to the external input circuit. It is configured to include a logic circuit (for example, a peripheral logic circuit manufactured to suit a customer).

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the second or third aspect, the test data is externally input based on a control signal for instructing observation of a specific macro cell. Is provided with a data supply line for directly supplying a part of the plurality of input test dedicated circuits to the input test dedicated circuit.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the fourth aspect, a plurality of different types of macro cells (for example, a mixture of RAM and peripheral logic circuits) are included as macro cells, and the data supply lines are the same. Connect only macro cells of type in a column.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit 100 including a plurality of macro cells R ₁ , R ₂ , ..., Transfer data consisting of a predetermined number of bits is supplied to each macro cell based on the scan clock SC. The input data is serially input, the input transfer data is serially output while being sequentially shifted, and the data output from one macro cell is input in parallel based on the instruction signal RC for instructing the macro cell to perform input / output. , Which are stored as part of the output test dedicated circuits O ₂ , O ₃ , ..., And the input / output unit has a predetermined number of bits of transfer data transferred from the output test dedicated circuits O ₂ , O ₃ ,. The external output circuit O ₁ which stores the stored transfer data in parallel and supplies the stored transfer data to the external output terminal D _{O in} parallel is provided. Multiple output test circuits are serially connected in series so that they are serially input to the output test circuit, and the serial output of the output test circuit that transfers the transfer data at the end is supplied to the external output circuit. It

In FIG. 1, the connection line between the output dedicated test circuits transfers the scan clock SC and the transfer data. The invention according to claim 7 is the semiconductor integrated circuit according to claim 6, wherein when an observation signal for instructing observation of transfer data from the macro cell is supplied, a test stored in the external output circuit. It is configured to include a logic circuit (for example, a peripheral logic circuit manufactured according to the customer) that operates as an output circuit for directly outputting the use data to the external output terminal.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the sixth or seventh aspect, transfer data is output for a plurality of outputs based on a control signal for instructing observation of a specific macro cell. A data output line is provided for outputting directly from a part of the output dedicated circuit of the test dedicated circuit to the external output circuit.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the eighth aspect, the macro cells include a plurality of different types of macro cells, and the data output line connects only the same type of macro cells in a column.

The invention described in claim 10 is the semiconductor integrated circuit according to any one of claims 2 to 5, and 6
The semiconductor integrated circuit according to claim 9. The number of bits stored in the input test dedicated circuit and the number of bits stored in the output test dedicated circuit are the same.

The invention described in claim 11 comprises the semiconductor integrated circuit according to any one of claims 2 to 5 and the semiconductor integrated circuit according to any one of claims 6 to 9. The frequency of the scan clock for shifting each of the input test dedicated circuit or the output test dedicated circuit is
The frequency is set to be substantially proportional to the number of bits stored in each test dedicated circuit.

According to a twelfth aspect of the present invention, in the semiconductor integrated circuit according to the tenth or eleventh aspect, the test data stored in the external input circuit is input, and the data that the macrocell should originally output is externally output. A measurement macrocell (for example, RAM) to be output to the circuit is provided, and the external output circuit compares the test data shifted from the output test dedicated circuit with the output data output from the measurement macrocell and compares them. The result is output to the external output terminal (eg, operates as a comparison circuit).

[0026]

According to the invention described in claim 1, the input / output section is
Test data having a predetermined number of bits is input to the external terminal (D _I / D _O ) and output data read from the macro cell is output to the external terminal. The test-dedicated circuits I ₂ , I ₃ , ..., O ₂ , O ₃ , ... Are provided for each macro cell, supply the test data input from the input / output unit to the macro cell, and output the output data output from the macro cell. Transfer to the input / output unit.

According to the second aspect of the invention, the external input circuit I ₁ inputs the test data as parallel data from the external input terminal D _I. Then, based on the scan clock SC, this data is sequentially supplied to the input test dedicated circuit I ₂ to be first shifted. Therefore, the supplied test data is sequentially moved along the input test-dedicated circuits connected in series. When the instruction signal RC is input, the data stored in the input test dedicated circuit is supplied to each macro cell (see FIG. 1B). Therefore, by writing the test data with a predetermined number of bits as the minimum unit and transferring the test data by the scan clock SC, the test data required for a desired macro cell can be easily set.

According to the third aspect of the invention, when the setting signal is supplied to the logic circuit, the internal connection is changed so that the test data is directly supplied from the external input terminal to the external input circuit. Therefore, when the macro cell needs to be tested (observed), the normal operation state can be easily changed to the circuit state for inputting the test data by controlling the setting signal.

According to the invention described in claim 4, the data supply line is connected to a part of the plurality of input test dedicated circuits connected in series by the control signal when observing a specific macro cell. On the other hand, the test data is directly supplied from the external input circuit. Therefore, it is possible to set the test data in a short time even for the input test dedicated circuit in the subsequent stage, which takes time to sequentially shift and supply the test data.

According to the fifth aspect of the present invention, the data supply line connects only macrocells of the same type among a plurality of macrocells of different types in cascade, so that the test data can be supplied only to the macrocells of the same type. Can be set in a short time.

According to the invention described in claim 6, the output test
Strike dedicated circuit O₂, O₃, ... are based on the instruction signal RC
The data output from each macro cell is input and stored.
In addition, another output test is performed based on the scan clock SC.
Input the transfer data transferred from the dedicated circuit
Transferred data together with the data output from the cell
Output while shifting. Dedicated test circuit for multiple outputs
O₂, O₃, ... shift the transfer data sequentially and transfer
External output circuit O₁The macro cell O ₂,
O₃The data output by,… are transferred in order.
become. Therefore, a predetermined bit is set to the scan clock SC
External output terminal D every time_ONew from
Directly observe the output data of the transferred macro cell
be able to. Therefore, the scan clock SC
By repeating the transfer of a predetermined number of bits,
The operating status of the macro cell is read in order as parallel data.
It can be taken out and observed. These read data are macros
Data analysis itself, so the data is analyzed
It can be used directly for inspection of macro cells without performing the above.

According to the invention described in claim 7, when the observation signal is supplied, the logic circuit changes the internal connection so as to directly output the transfer data transferred to the external output circuit to the external output terminal. To do. Therefore, when the test (observation) of the macro cell is necessary, the transfer data from the macro cell can be directly output from the normal operation state to the external output terminal only by controlling the observation signal.

According to the invention described in claim 8, when the control signal is supplied to the data output line, the transfer data is directly output from a part of the output test dedicated circuit to the external output circuit. Therefore, as compared with the case where the output test dedicated circuits are sequentially shifted, a part of the output test dedicated circuits can be observed in a short time.

According to the ninth aspect of the invention, the data output line connects only the macrocells of the same type among the plurality of macrocells of different types in a column, so that the transfer data of only the macrocells of the same type is selectively selected. It can be observed in

According to the tenth aspect of the invention, the same number of bits is stored in both the input test dedicated circuit and the output test dedicated circuit. Therefore, when one test data is input to the external input circuit and shifted,
Output data read from one macro cell can be observed from the external output circuit using the same scan clock. Therefore, there is a one-to-one relationship between the time required to input one test data and the time required to output data from one macro cell, and data analysis becomes easy.

According to the eleventh aspect of the invention, the frequency of each scan clock supplied to shift the input test dedicated circuit and the output test dedicated circuit is the number of bits stored in each test dedicated circuit. Is set to a frequency approximately proportional to. This is equal to the time until one test data is rewritten in the one input test dedicated circuit and the time until one data read out in the one output test dedicated circuit is transferred. Means that. Therefore, there is a one-to-one relationship between the time required to input one test data and the time required to output data from one macro cell to the outside, and data analysis becomes easy.

According to the twelfth aspect of the present invention, the measuring macro cell performs the same operation as the other macro cells, and when the same test data is supplied to the other internal macro cells, The same data as the macro cell of is output. If a defect occurs in another macro cell, the output of the measurement macro cell (normal value) and the data transferred from the other macro cell (abnormal value) will be inconsistent in the data content. Therefore, in the external output circuit,
By comparing the output of the measuring macro cell, which is the reference circuit, with the test data output from the other macro cell and transferred, it is possible to observe from the external output terminal whether or not the operation of the other macro cell is defective.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the apparatus of the present invention will be described with reference to the drawings. (I) First Example The first example of the present invention is defined by claim 1, claim 2, and claim 6.
And a semiconductor integrated circuit to which the invention according to claim 10 is applied.

FIG. 2 shows the semiconductor integrated circuit 10 of the first embodiment.
1 shows the configuration of No. 1. Reference symbols R ₁ and R ₂ are macro cells to be measured, and are RAMs in this embodiment. R
AM normally has the same number of input terminals and output terminals, but if the number of output terminals is less than the number of input terminals, it is treated as if a dummy terminal has been inserted, and the data of the bit corresponding to the dummy terminal is used. Is ignored.

R _T is a measuring RAM, and has the same function and the same number of input / output terminals as the other macro cells R ₁ and R ₂ . However, in this embodiment, it is not an essential configuration. I ₁ is an external input circuit, which inputs a predetermined number of bits (6 bits in FIG. 2) in parallel from the external input terminal D _I and shifts the storage data according to the scan clock SC.

I ₂ and I ₃ are input test-dedicated circuits, which have at least the same configuration as the external input circuit I ₁ , but may also have a macrocell test function. The input test dedicated circuits I ₂ and I ₃ output the stored test data to the RAM in accordance with an instruction signal RC for instructing the RAM to perform input / output.

O ₂ and O ₃ are output test-dedicated circuits, which store the data output from the RAM according to the RC. Further, the data is shifted bit by bit according to the scan clock SC.

O ₁ is an external output circuit, which stores the data transferred from the output test dedicated circuits O ₂ and O ₃ according to the scan clock SC and outputs it to the external output terminal D _O.

In FIG. 2, the connection lines connecting the test-dedicated circuits are composed of two lines, one for the scan clock and the other for the shifted data. In the above configuration, the operation of this embodiment is performed as follows.

When observing the semiconductor integrated circuit 101 (inspecting the internal macrocell quality), the user supplies test data from the external input terminal D _I. For example, test data for the macro cell R ₂ is input from the external input terminal D _I and shifted by 6 bits by the scan clock SC. Further, the test data for the macro cell R ₁ is input and shifted by 6 bits.

After the test data is set in the input test-dedicated circuits I ₂ and I ₃ as planned, the instruction signal RC is validated to transfer the test data to the macrocell R ₁ ,
Written to R ₂ .

Macrocell R₁, R₂Tests stored in
When reading the use data, the instruction signal RC is made valid again.
It The data from the macro cell is the corresponding output macro cell.
Le O ₂, O₃Stored in. Is each macro cell read
These data are sequentially output to the outside by the scan clock SC.
Circuit O₁Transferred to.

When the first 6 bits are shifted to the external output circuit O ₁ , the macro cell R _{1 is} fed from the external output terminal D _0.
The stored data regarding the next macro cell R ₂ is observed at the stage when the next 6 bits are shifted.

If the macrocells R ₁ and R ₂ operate normally, the data as input from the external input terminal D _I can be observed from the external output terminal D _O. Therefore, by comparing and examining the input data and the output data, it is possible to determine which macro cell has a defect.
In particular, when there are a large number of macro cells, the presence or absence of a defect may be determined by sequentially accumulating the data from the macro cells that have been read out successively and creating and displaying a so-called fail bit map. .

It is also possible to record the test data in the measurement RAM (R _T ) and read the data for comparison with the data transferred from the built-in macro cell.
As described above, according to the first embodiment, the macro cell has the same number of input bits and the same number of output bits, and since the scan clocks of the input test dedicated circuit and the output test dedicated circuit use the same clocks, they are supplied from the outside. The control scan clock and the instruction signal can be unified. (II) Second Embodiment A second embodiment of the present invention is an application of the inventions of claims 3, 7, and 10.

FIG. 3 shows the structure of the semiconductor integrated circuit of the second embodiment.
Indicates success. The semiconductor integrated circuit 102 of the second embodiment is
Input terminal D_IAnd external input circuit I ₁And the surrounding logic
Kuk Gate G₁Equipped with. Also, the external output terminal D_OAnd outside
Output circuit O₁Between the peripheral logic gate G₂Equipped
Get Other components are the same as those in the first embodiment.
Therefore, the same reference numerals as in the first embodiment are used and the description thereof is omitted.
I do.

The peripheral logic gate is a set of gates designed to meet the operating conditions desired by the user.
Under normal operating conditions, it primarily acts as an I / O interface.

However, the input terminal for observation of the macro cell,
The output terminal is required only when measuring the internal macro cell, and is not required during normal operation. Providing a dedicated terminal for measurement reduces the space for providing other terminals.

Therefore, in this embodiment, whether the peripheral logic gate is normally operated or used for measuring the macro cell is selected by the measuring signal. When the externally supplied measurement signal indicates non-selection, the peripheral logic gate G ₁ ,
G ₂ is a logic adapted to the specifications of the user, and inputs / outputs data.

When the measurement signal specifies selection, the peripheral logic
Kuk Gate G₁Is the external input terminal D _IIs the external input circuit I
₁It is equivalent to being connected in parallel to. Peripheral logic
Kuk Gate G₂Is the external output terminal O₁And connected in parallel
It is equivalent to the state that was done. That is, the measurement signal is selected
Then, the external input circuit is substantially the same as in the first embodiment.
I₁Is the external input terminal D_IConnected to the external output circuit
O₁Is the external output terminal D_OWill be connected to.

By the above operation, the test data is directly supplied from the external input terminal D _I used as another I / O terminal during the normal operation under the control of the measurement signal. This allows the data to be measured and read directly from the external output terminal D _O.

As described above, according to the second embodiment, the terminals can be switched and used according to normal operation or observation.
Good terminal utilization efficiency. (III) Third Embodiment A third embodiment of the present invention is an application of the invention described in claims 4 and 8.

FIG. 4 shows the structure of the semiconductor integrated circuit of the third embodiment. As shown in FIG. 4, the configuration of the semiconductor integrated circuit 103 of the third embodiment is basically the same as that of the first embodiment, but the data supply line activated externally by the through signal TH. Or, there is a data output line. Further, the input test-dedicated circuits I ₁ ′ to I ₃ ′ of each macro cell are based on the through signal TH _I, and the input test-dedicated circuit of the specific RAM and the external input circuit I
₁ 'and the direct connection via a data supply line. Output test circuit O ₁ 'of each macro cell
~ O ₃ 'also has a specific RAM based on the through signal TH _O.
The test dedicated circuit for output and the external output circuit O ₁ 'can be directly connected via the data output line.

Next, the operation will be described. In the third embodiment,
For example, the through signal TH_IWhen is selected, input
Test circuit I₂’Bypassing the external input circuit I
₁Test circuit for direct input of test data
I₃’. Also, the through signal TH
_OWhen is selected, output dedicated circuit O₂’Viper
And output test dedicated circuit O₃From the external output circuit
O₃′ Shall be directly transferred.

Since there may be a dozen or more macro cells included, the first half macro cells and the second half macro cells may be selected by the through signal line of this embodiment. To observe only the latter half macro cell,
By selecting the through signal, it is possible to quickly transfer the test data and the read output data to the test dedicated circuit for the latter half macro cell.

As described above, according to the third embodiment, it takes time if data is transferred in order over the existing macro cells, and direct data input / output is performed with the macro cell. Therefore, the observation time of the macro cell may be shortened in some cases. In particular, it is not necessary to inspect all macrocells, and when only macrocells that take a relatively long time to transfer data in terms of transfer order are observed, the time can be greatly shortened. (IV) Fourth Embodiment A fourth embodiment of the present invention is an application of the inventions of claims 5 and 9, and relates to an application of the third embodiment.

FIG. 5 shows the structure of the semiconductor integrated circuit of the fourth embodiment. Depending on the specifications required for the standard cell, not only the RAM test but also the important logic circuit test is required. Therefore, in the fourth embodiment, the line for scanning the data is wired not only through the RAM but also through a test dedicated circuit for observing the operation of some logic circuits.

The semiconductor integrated circuit 104 of the fourth embodiment is
Macrocell R₁~ R₃And also has a logic circuit
And I₁~ I₃Is a dedicated input test for RAM.
It is a circuit for₁~ O₃Is output to these RAMs
It is a dedicated circuit for testing. L ₁~ L₆Do the test
Logic that can monitor the operating status of a logic circuit
It is a dedicated circuit for test for clock.

A connection line for transferring data and a scan clock connects all the test dedicated circuits in cascade. Further, as in the third embodiment, the data supply line is connected through all the test dedicated circuits. In the present embodiment, by selecting the through signal TH, for example, RA
Only M macro cells shall be connected.

In FIG. 5, the structure of the input / output unit is omitted for simplicity. Further, in the configuration of FIG. 5, the input test dedicated circuits and the output test dedicated circuits for the RAM are connected in series, but as in the first to third embodiments, the transfer lines on the output side on the input side are connected. May be provided separately.

In the above structure, the through signal T
When H is selected, RAM is selected from among the dedicated test circuits.
Only the test-only circuit corresponding to the macrocell for is selected. When it is desired to observe only the RAM, only the RAM can be selected and the observation can be completed in a short time by controlling the through signal TH.

Further, the macro cell and the logic relating to the RAM may be alternately selectable. That is, when the through signal TH is at the H level, the macro cell test dedicated circuits I _{1 to} I ₃ and O _{1 to} O ₃ for the RAM are selected, and when the through signal TH is at the L level, the logic dedicated test circuits L _{1 to} L _{6 are selected.} Is selected.

As described above, according to the fourth embodiment, by switching each macro cell type by the through signal TH, only the necessary macro cell test can be easily performed in a short time. Compared to the case where a plurality of normal macro cells are mixed and connected, data supply and analysis become easier. (V) Fifth Embodiment A fifth embodiment of the present invention is an application of the invention described in claim 12.

FIG. 6 shows the configuration of the input / output unit in the semiconductor integrated circuit of the fifth embodiment. Specifically, in the first to third embodiments, the external output dedicated circuit O of the input / output unit is used.
It is possible to replace ₁ (O ₁ ') with the comparator C ₁ of this embodiment.

As shown in FIG. 6, in the semiconductor integrated circuit 105 of this embodiment, it is possible to select only the output of the data transferred from the internal macro cell or the output of the measurement RAM ( _RT ). Dedicated external output circuit O
Instead of ₁ (O ₁ '), a comparator C ₁ is provided which compares the transfer data from the internal macro cell with the output of the measuring RAM ( _RT ) and outputs the comparison result to the external output terminal D _O. Has been.

Next, the operation will be described. In the above configuration, when predetermined test data is transferred from the external input circuit I ₁ to inspect a certain macro cell, the test data is measured based on the instruction signal RC before the test data is transferred by the scan clock SC. The test data is stored in the RAM ( _RT ).

Then, the scan clock SC is supplied to store the test data in the macro cell to be tested. This time, the output test dedicated circuit reads the data stored in the macro cell by the instruction signal RC, and transfers the read data to the comparator C ₁ by the scan clock SC. When the read data is transferred to the comparator C _{1, the} measuring RAM is instructed by the instruction signal RC.
The data stored in (R _T ) is supplied to the comparator C ₁ .

The comparator C ₁ is a standard measuring RAM for measurement.
The data read from (R _T ) is compared with the data transferred from the macro cell to be tested. RA for measurement
Since M (R _T ) has the same operation characteristics as the RAM which is an internal macro cell, the same result is output when the same test data is supplied. However, if some defect occurs in the internal macro cell, both output data will be different.

Therefore, the comparator C ₁ is the measuring RAM.
By comparing the output of (R _T ) with the data read and transferred from the internal macro cell, it becomes possible to directly observe the quality of the output of each bit of the macro cell from the external output terminal D _O.

As described above, according to the fifth embodiment, the determination result of the macro cell is directly output to the external output terminal, so that it is not necessary to compare the input data with the input test data after reading the transfer data. , Macro cell measurement can be done easily. (VI) Other Modifications Various modifications are possible without being limited to the above embodiment of the present invention.

For example, in the first to third embodiments, the data supply on the input side and the data output on the output side are performed based on the same scan clock, but they are based on clocks having different frequencies. It may be. That is, as described in claim 11, a scan clock having a frequency proportional to the number of bits of the input test dedicated circuit and the number of bits of the output test dedicated circuit is used. For example,
When the input of a certain macro cell is 6 bits and the output is composed of 3 bits, the frequency of the scan clock for shifting the input test dedicated circuit provided on the input side is set for the output provided on the output side. Double the frequency of the scan clock for shifting the test circuit.
If the output is 2 bits, a scan clock having a triple frequency is used.

According to the frequency relationship of this scan clock, the time required to input one data and the time required to output one data match, so that the data can be input without timing adjustment. Input processing and output processing can be performed alternately. Therefore, the handling of the data is simplified.

Further, since the transfer time can be made constant regardless of the number of input bits and the number of output bits as described above, the macro cell has the same number of input bits and output as the RAM exemplified in the above embodiment. The number of bits does not have to be equal, and may be a macro cell having another function.

[0079]

According to the inventions of claims 1 to 12, since the number of input and output bits of the macro cell to be measured is equal to one unit, data input and output results can be observed. Measurement can be performed under the same conditions as when data is written and read directly in the macro cell without being affected by logic circuits other than the macro cell. Therefore, as compared with the conventional semiconductor integrated circuit, the internal macro cell can be observed easily, in a short time, and reliably.

According to the invention of claim 3 or claim 7, since it can be used as an input / output terminal for observation during observation and as an input / output terminal for normal operation during normal operation, the external terminal Use efficiency can be improved.

According to the invention described in claim 4 or claim 8, since a specific part of the macrocells can be observed by the control signal, the macrocells which are frequently observed can be easily observed in a short time. .

According to the invention described in claim 5 or claim 9, the data supply line connects only macrocells of the same type among a plurality of macrocells of different types in a column, so that observation of macrocells of the same type is performed. Can be done in a short time.

According to the tenth or eleventh aspect of the present invention, the time relationship between one test data input and one test data output is one-to-one. Therefore, data analysis and comparison are easy and reliable. You can do it.

According to the twelfth aspect of the present invention, it is possible to easily compare the output of the reference measurement macrocell with the output of another measurement target macrocell. Therefore, it is possible to analyze the test data. Instead, the quality of the macro cell can be directly and easily determined.

[Brief description of drawings]

FIG. 1 is a principle explanatory view of a semiconductor integrated circuit of the present invention,
(A) is a principle configuration diagram, and (B) is a timing chart.

FIG. 2 is a configuration diagram of a semiconductor integrated circuit of a first embodiment.

FIG. 3 is a configuration diagram of a semiconductor integrated circuit of a second embodiment.

FIG. 4 is a configuration diagram of a semiconductor integrated circuit of a third embodiment.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit of a fourth embodiment.

FIG. 6 is a configuration diagram of a semiconductor integrated circuit of a fifth embodiment.

FIG. 7 is an explanatory diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

D _I ... External input terminal D _O ... External output terminal I _{1 to} I ₃ , I ₁ ′ to I ₃ ′, I _{11 to} I ₁₃・ ・ ・ Input test dedicated circuit O _{1 to} O ₃ , O ₁ ′ to O ₃ ′ , O _{11 to} O ₁₃ ... Output test dedicated circuit L _{1 to} L ₆ , L _{11 to} L ₁₆ ... Test dedicated circuit R _{1 to} R ₃ , R _{11 to} R ₁₃ ... Macro cell (RAM) _RT ... Measurement RAM G ₁ , G ₂ ... Peripheral logic gate C ₁ ... Comparator 100-105, 200 ... Semiconductor integrated circuit

Claims (12)

[Claims] 1. In a semiconductor integrated circuit including a plurality of macro cells, test data having a predetermined number of bits is input to an external terminal and output data read from the macro cell is output to the external terminal. A test-dedicated circuit that includes an input / output unit, supplies test data input from the input / output unit to the macrocell, and transfers output data output from the macrocell to the input / output unit, for each macrocell. A semiconductor integrated circuit comprising: 2. In a semiconductor integrated circuit including a plurality of macro cells, test data having a predetermined number of bits is input in parallel from an external input terminal to an input / output unit, and the input test data is input based on a scan clock. An external input circuit that sequentially outputs data is provided.For each macro cell, the test data is serially input based on the scan clock, and the input test data is serially output while being sequentially shifted. ,
An input test that outputs test data having the same number of bits as the number of bits input to the external input circuit to one macro cell in parallel based on an instruction signal for instructing input / output to the macro cell A dedicated circuit is provided, and the serial output of the external input circuit is serially input to the input test dedicated circuit to be shifted first, and the serial output of one input test dedicated circuit is input to the other input test dedicated circuit. A semiconductor integrated circuit, wherein a plurality of said input test circuits are serially connected in series so as to be input serially. 3. The semiconductor integrated circuit according to claim 2, wherein when a setting signal for setting test data is input to the macro cell, a test signal is directly input from the external input terminal to the external input circuit. A semiconductor integrated circuit comprising a logic circuit that operates as a supply circuit for supplying data. 4. The semiconductor integrated circuit according to claim 2, wherein the test data is input from the external input circuit based on a control signal for instructing observation of a specific macro cell. Integrated circuit having a data supply line for directly supplying to a part of the input test dedicated circuit of the input test dedicated circuit. 5. The semiconductor integrated circuit according to claim 4, wherein the macro cells include a plurality of different types of macro cells, and the data supply line connects only the same type of macro cells in a column. circuit. 6. A semiconductor integrated circuit including a plurality of macro cells, wherein transfer data having a predetermined number of bits is serially input to each macro cell based on a scan clock,
The input transfer data is serially output while being sequentially shifted, and the data output from one macro cell is input in parallel based on an instruction signal for instructing input / output to the macro cell, and as a part of the transfer data. An output test dedicated circuit to be stored is provided, and the input / output unit stores transfer data transferred from the output test dedicated circuit for the predetermined number of bits, and stores the stored transfer data to an external output terminal. An external output circuit that supplies in parallel is provided, and a plurality of the above output test circuits are serially arranged in series so that the serial output of one output test circuit is serially input to another output test circuit. A semiconductor integrated circuit characterized in that the serial output of an output test-dedicated circuit to which the transfer data is transferred and finally transferred is supplied to the external output circuit. Road. 7. The semiconductor integrated circuit according to claim 6, wherein when an observation signal for observing transfer data from the macro cell is supplied, the transfer data stored in the external output circuit is transferred to the external device. A semiconductor integrated circuit comprising a logic circuit that operates as an output circuit for directly outputting to an output terminal. 8. The semiconductor integrated circuit according to claim 6 or 7, wherein the transfer data is transferred among the plurality of output test dedicated circuits based on a control signal for instructing observation of a specific macro cell. 7. A semiconductor integrated circuit, comprising a data output line for directly outputting a part of the output test dedicated circuit to the external output circuit. 9. The semiconductor integrated circuit according to claim 8, wherein the macro cells include a plurality of different types of macro cells, and the data output lines connect only the same type of macro cells in cascade. circuit. 10. A semiconductor integrated circuit according to any one of claims 2 to 5 and a semiconductor integrated circuit according to any one of claims 6 to 9, wherein the memory for the input test dedicated circuit is provided. The semiconductor integrated circuit is characterized in that the number of bits to be performed and the number of bits stored in the output test dedicated circuit are the same. 11. A semiconductor integrated circuit according to any one of claims 2 to 5 and a semiconductor integrated circuit according to any one of claims 6 to 9, wherein the input dedicated test circuit or the A semiconductor integrated circuit, wherein a frequency of a scan clock for shifting each of the output test dedicated circuits is set to a frequency substantially proportional to the number of bits stored in each test dedicated circuit. 12. The semiconductor integrated circuit according to claim 10, wherein the test data stored in the external input circuit is input,
A measurement macrocell that outputs the output data that the macrocell should output to the external output circuit is provided, and the external output circuit outputs the test data and the measurement macrocell that have been shifted from the output test dedicated circuit. The semiconductor integrated circuit is characterized in that the output data is compared and the comparison result is output to the external output terminal.