JPH08251151A - Synchronized changing device - Google Patents

Abstract

PURPOSE: To obtain the concrete constitution of a synchronized switching device capable of switching line without hit. CONSTITUTION: An active-side data signal DATAI is directly inputted to a switching circuit-7 and a reserving-side data signal DATAIS is delayed by a FIFO memory 12 to be a data signal DATAR and inputted to the switching circuit 7. A counting circuit 5 detects the relative delay time difference between both data signals inputted to the switching circuit 7 from a frame pulse generated by frame synchronization circuits 3 and 4. A control circuit 6 controls the frequency dividing rate N of an N-frequency divider 12 so as to eliminate the relative delay time difference. When a frequency dividing rate N is made larger than the frequency dividing rate M of an M-frequency divider 11, the delay quantity of the FIFO memory 12 is increased but when being made smaller, the delay quantity is reduced. This control eliminates the relative delay time difference between both data signals inputted to the switching circuit 7 to attain syncronized switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous switching device used in a digital wireless communication system, and more particularly to a synchronous switching device for switching a working line to a protection line at a receiving end of the digital wireless communication system without interruption.

[0002]

2. Description of the Related Art When switching a working line of a communication system to a protection line, first a transmission line connects the protection line to the working line in parallel and a signal to be transmitted is also passed through the protection line. Switch to the protection line. When the signal to be transmitted is a digital signal and the relative delay time difference between the working line and the protection line is 1 clock cycle or more, the signal transmitted on the working line and the signal transmitted on the protection line are directly switched at the receiving end. And a bit is missing or duplicated and a momentary interruption occurs. To avoid this interruption, set the relative delay time difference to 1
Must be adjusted within the clock period.

When the line is a wireless line, the propagation time may fluctuate due to fading or the like, and the relative delay time difference between the working line and the protection line may fluctuate by one clock cycle or more. Therefore, although the average of the relative delay time differences, in other words, the fixed component of the relative delay time differences is initially adjusted so as to be within one clock cycle, it is necessary to further adjust the fluctuation component.

A variable delay circuit is provided to adjust the relative delay time difference, and the relative delay time difference is detected by comparing the frame phases of the signal transmitted on the working line and the signal transmitted on the protection line. There is known a synchronous switching device of a system that controls a delay amount of a variable delay circuit based on a detection result.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a concrete structure of a synchronous switching device adopting such a system.

[0006]

SUMMARY OF THE INVENTION A synchronous switching device of the present invention comprises a working side data signal transmitted by a working wireless line and a standby side data signal transmitted by a spare wireless line for switching the working wireless line. Is a synchronous switching device that adjusts the relative delay time difference between the active side data signal and the standby side data signal without instantaneous interruption, and the input clock signal is divided by a division ratio M (M is an integer of 2 or more). A first frequency divider for dividing and outputting, and a second divider for dividing and outputting a spare side clock signal which is a clock of the spare side data signal by a dividing ratio N (N is an integer of 2 or more). A frequency divider, a phase comparator for detecting the phase difference between the signals output by the first and second frequency dividers, and output so that the phase difference detected by the phase comparator becomes small. Generates the clock signal with controlled phase A variable frequency oscillator for outputting to the first frequency divider; a read control unit for outputting the clock signal as a read clock signal; and a sequence for inputting the spare side data signal and using the spare side clock signal as a write clock. A FIFO memory that sequentially reads and outputs the read clock signal supplied from the read control unit as a read clock, and a standby frame synchronization circuit that outputs a standby frame pulse in frame synchronization with the data signal read by the FIFO memory. A working-side frame synchronizing circuit that outputs a working-side frame pulse in frame synchronization with the working-side data signal; The value N / M, which is the ratio of the dividing ratio N to the dividing ratio M, is set to 1 Timing of the working side frame pulse and the spare side frame pulse by controlling the frequency division ratio of at least one of the first and second frequency dividers so as to make the value smaller than 1 When the two coincide with each other, a control means for outputting a switching control signal, a working side data signal, a working side clock signal which is a clock of the working side data signal, a data signal read by the FIFO memory and the read clock signal are inputted. Until the switching control signal is input from the control means, the active side data signal and the active side clock signal are selected and output, and when the switching control signal is input, the data signal read by the FIFO memory and the read clock And a switching circuit for selecting and outputting a signal.

In the present invention, the control means counts the read clock signal input during the period from the input of the working frame pulse to the input of the standby frame pulse, and outputs a count value. And detecting the advance or lag of the spare side frame pulse with respect to the working side frame pulse based on the frame length information of the working side data signal and the spare side data signal and the count value output from the counting circuit. The frequency division ratio N is made larger than the frequency division ratio M when advancing, and is made smaller than the frequency division ratio M when being delayed, and equalized to the frequency division ratio M when there is no advance or delay. A control circuit for controlling the frequency division ratio N of the second frequency divider may be included.

[0008]

The present invention will be described below with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, an M divider 11 of the read control unit 1 divides an input clock signal by M and outputs it. The N frequency divider 12 is a frequency divider having a variable frequency division ratio N, and divides the frequency of the standby side clock signal CLKIs, which is the clock of the standby side data signal DATAIS, transmitted through the standby line by N and outputs the result. The phase comparator 13 detects the phase difference between the output of the M frequency divider 11 and the output of the N frequency divider 12 and outputs the detection result. An exclusive OR circuit can be used as the phase comparator 13. The filter 14 smoothes the output of the phase comparator 13 and outputs it. VC
O15 is a clock generator whose output phase is controlled by the output of the filter 14 and outputs the generated clock signal to the M frequency divider 11 and also as the read clock signal CLKR. The output phase of the VCO 15 is controlled so that the output of the filter 14 becomes small, in other words, the phase difference between the output of the M divider 11 and the output of the N divider 12 becomes small. If the frequency division ratio N of the N frequency divider 12 is equal to the frequency division ratio M of the M frequency divider 11, the read clock signal CLKR output from the VCO 15 is in phase synchronization with the standby side clock signal CLKIs.

The FIFO memory 2 uses the spare side clock signal CLKIS as a write clock for the spare side data signal D.
The ATAIS is sequentially written, the read clock signal CLKR output from the VCO 15 is sequentially read as the read clock, and the data signal DATAR is output.

The frame synchronization circuit 3 includes a FIFO memory 2
The data signal DATAR output by the CPU and the read clock signal CLKR that is the clock thereof are input, and the data signal D
Frame pulse FP on the spare side in frame synchronization with ATAR
Output S. The frame synchronization circuit 4 receives the working side data signal DATAI transmitted through the working line and the working side clock signal CLKI which is the clock thereof, and outputs the working side frame pulse FP in frame synchronization with the working side data signal DATAI. .

The counting circuit 5 uses the active-side frame pulse FP.
Is used as a start signal and the spare frame pulse FPS is used as a stop signal to count the read clock signal CLKR,
Output the count value. This count value is a signal indicating how many clock cycles the standby frame pulse FPS is delayed with respect to the active frame pulse FP, and the data signal DATAR is referenced with the active data signal DATAI as a reference.
Is a signal indicating how many clock cycles are delayed. Working side data signal DATAI and data signal DATA
If there is no relative delay time difference with R, the count value becomes zero.
The control circuit 6, the frame length information and count value counting circuit 5 and outputs the line switching controller of the data signal based on the (not shown) or ^these line switching command, use side data signal DATAI and data signals DATAR The frequency division ratio N of the N frequency divider 12 is controlled so that the relative delay time difference between the control circuit and the control circuit is reduced, and when the count value output from the counting circuit 5 becomes zero, a switching control signal is generated and output.

The switching circuit 7 has a working data signal DAT.
AI, working clock signal CLKI, data signal DAT
When the AR and the read clock signal CLKR are input and the switching control signal is input from the control circuit 6, the output data signal D
The signals selectively output as the ATAO and the output clock signal CLKO are switched from the currently used data signal DATAI and the currently used clock signal CLKI to the data signal DATAR and the read clock signal CLKR.

Since the embodiment shown in FIG. 1 has the configuration described above, the working side data signal DATAI transmitted through the working line and the working side clock signal CLKI which is the clock thereof are directly input to the switching circuit 7. . The spare side data signal DATAIS transmitted by the spare line connected in parallel to the working line at the sending end in response to the line switch command from the line switch control device is sequentially written in the FIFO memory 2 and delayed by reading the data, Signal DATAR
And its clock is the read clock signal CLK
It is input to the switching circuit 7 together with R.

Assuming that the maximum fluctuation width of the relative delay time difference between the data signal DATAI on the working side and the data signal DATAIS on the protection side is ± m clock cycles, the FIFO memory 2 adjusts the maximum fluctuation width, and therefore the data in the FIFO memory 2 is adjusted. The signal storage capacity is set to 2m + 1 clock cycle.
In addition, the working side data signal DATAI is the spare side data signal D.
The fixed component of the relative delay time difference is initially adjusted so as to be delayed by m clock cycles on average with respect to ATAIS.
With these settings, the delay amount by the FIFO memory 2 becomes a minimum of 0 and a maximum of 2 m clock cycle, and the data signal DAT
Since AR is delayed from the spare side data signal DATAIS by a minimum of 0 and a maximum of 2 m clock cycles, the relative delay time difference between both data signals input to the switching circuit 7 is ± m clock cycles or less. By adjusting the delay amount by the FIFO memory 1, the relative delay time difference between both data signals input to the switching circuit 7 can be set within one clock cycle.

The count value output from the counting circuit 5 is n,
When the data signal DATAR lags the working data signal DATAI, the count value n is the delay itself in clock cycle units. If you are going in reverse,
The standby-side frame pulse FPS, which is the stop signal of the counting circuit 5, is the active-side frame pulse FP, which is the start signal.
Since it is a frame pulse of a frame one frame after the frame of, the value f−n is the advance with the frame length as f clock cycles. Since the relative delay time difference between the data signal DATAR and the working data signal DATAI is ± m clock cycles or less, and the frame length f clock cycle is much larger than the maximum fluctuation width ± m clock cycles of the relative delay time difference. The value n in this case is slightly smaller than the value f and much larger than the value m. From this, it is possible to judge whether the count value n is a threshold value by a threshold value between the value f and the value m, and to discriminate whether it is a lead or a lag.

The control circuit 6 controls the frequency division ratio N of the N frequency divider 12 to be equal to the frequency division ratio M of the M frequency divider 11 when no line switching command is input. Therefore,
At this time, the read clock signal CLKR, which is the read clock of the FIFO memory 1, is in phase synchronization with the standby clock signal CLKIs, which is the write clock.
The delay amount due to the FO memory 1 continues to be the amount determined by the initial state.

When the circuit switching command is inputted, the control circuit 6 judges the count value n output from the counting circuit 5 as a threshold value,
If the value n is smaller than the threshold value, the data signal DATAR
Is delayed with respect to the working data signal DATAI. In this case, the control circuit 6 controls the frequency division ratio N of the N frequency divider 12 to be smaller than the frequency division ratio M of the M frequency divider 11 according to the value n. By this control, the frequency of the read clock signal CLKR, which is the read clock, becomes higher than the frequency of the standby clock signal CLKIs, which is the write clock, and the phase of the read clock advances with time with respect to the phase of the write clock. Of the data signal D becomes faster than the writing speed, the delay amount by the FIFO memory 1 decreases with time.
The delay of ATAR with respect to the working data signal DATAI decreases. As a result, when the delay disappears and the count value n output from the counter circuit 5 becomes zero, the control circuit 6 sets the frequency division ratio N of the N frequency divider 12 to be equal to the frequency division ratio M of the M frequency divider 11 and switches. The control signal is output to the switching circuit 7.

If the value n is larger than the threshold value in the threshold value judgment, the control circuit 6 judges that the data signal DATAR is ahead of the working data signal DATAI. In this case, the control circuit 6 calculates the value f−n, and the N frequency divider 12
The frequency division ratio N is controlled to be larger than the frequency division ratio M of the M frequency divider 11 according to the value f−n. By this control, the frequency of the read clock signal CLKR, which is the read clock, becomes lower than the frequency of the standby clock signal CLKIs, which is the write clock, and the phase of the read clock lags the phase of the write clock with time.
The read speed from the O memory 1 becomes slower than the write speed, the delay amount due to the FIFO memory 1 increases with time, and the active side data signal DATA of the data signal DATAR.
The progress toward I decreases. As a result, when there is no progress and the count value n output from the counting circuit 5 becomes zero,
The control circuit 6 makes the frequency division ratio N of the N frequency divider 12 equal to the frequency division ratio M of the M frequency divider 11 and outputs a switching control signal to the switching circuit 7.

The switching circuit 7 receives the active side data signal DATAI and the data signal DAT when the switching control signal is input.
Since the relative delay time difference from the AR is within one clock cycle, the output data signal DATAO to be selectively output can be switched from the working side data signal DATAI to the data signal DATAR without interruption.

The control circuit 6 makes the FI by setting the frequency division ratio N of the N frequency divider 12 smaller than the frequency division ratio M of the M frequency divider 11.
The delay amount by the FO memory 1 is reduced with time, and the frequency division ratio N is made larger than the frequency division ratio M to increase the delay amount with time to adjust the relative delay time difference between the working data signal DATAI and the data signal DATAR. However, instead of fixing the frequency division ratio N of the N frequency divider 12 and decreasing the frequency division ratio N, the frequency division ratio M of the M frequency divider 11 is increased and the frequency division ratio N is increased. Further, the frequency division ratio M of the M frequency divider 11 may be controlled so as to reduce the frequency division ratio M.

[0022]

As described above, according to the present invention, the spare side data signal is once written in the FIFO memory using the spare side clock signal as a write clock, and the variable frequency oscillator output is divided by the first frequency divider to obtain an output. The spare side data signal is delayed by reading with a read clock generated by a phase locked loop that compares the phase of the spare side clock signal with the output obtained by frequency division by the second frequency divider, and a frame pulse of the delayed data signal And the frame pulse of the working side data signal are detected, and the FI is controlled by controlling the ratio between the frequency division ratio of the first frequency divider and the frequency division ratio of the second frequency divider based on the detection result.
Provide a specific configuration of a synchronous switching device capable of line switching without interruption, that is, switching is performed after eliminating a relative delay time difference between a delayed data signal and a working data signal by increasing or decreasing a delay amount of a FO memory. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Read Control Unit 2 FIFO Memory 3, 4 Frame Synchronization Circuit 5 Counting Circuit 6 Control Circuit 7 Switching Circuit 11 M Divider 12 N Divider 13 Phase Comparator 15 VCO

Claims (2)

[Claims] 1. The working side data by adjusting the relative delay time difference between the working side data signal transmitted on the working radio line and the protection side data signal transmitted on the protection radio line to switch the working radio line. A synchronization switching device for switching a signal to the data signal on the spare side without instantaneous interruption, the first frequency divider outputting a signal by dividing an input clock signal by a frequency division ratio M (M is an integer of 2 or more). And a frequency division ratio N (N
Is an integer greater than or equal to 2) and outputs the second frequency divider,
A phase comparator for detecting the phase difference between the signals output by the first and second frequency dividers, and an output phase controlled so that the phase difference detected by the phase comparator becomes small. A variable frequency oscillator that generates the clock signal and outputs the clock signal to the first frequency divider, a read control unit that outputs the clock signal as a read clock signal, and the standby side clock that receives the standby side data signal. Sequential write using signals as write clocks, a FIFO memory that sequentially reads and outputs the read clock signals supplied from the read control unit as read clocks, and the FIFO memory
A spare side frame synchronization circuit that outputs a spare side frame pulse in frame synchronization with the data signal read by the memory,
A working-side frame synchronizing circuit that outputs a working-side frame pulse in frame synchronization with the working-side data signal, and a division ratio when the lead-lag of the protection-side frame pulse with respect to the working-side frame pulse is detected and progressing. The value N / M, which is the ratio of the frequency division ratio N to M, is set to be larger than 1 and smaller than 1 when delayed.
And a control means for controlling a frequency division ratio of at least one of the second frequency divider and outputting a switching control signal when the timings of the working side frame pulse and the protection side frame pulse match, and the working side data. Signal, the active clock signal which is the clock of the active data signal, the data signal read by the FIFO memory and the read clock signal, and the active side data until the switching control signal is input from the control means. A switching circuit for selecting and outputting a signal and the working clock signal and selecting and outputting the data signal read by the FIFO memory and the read clock signal when the switching control signal is input. Synchronous switching device. 2. The counting circuit, wherein the control means counts the read clock signal input during the period from the input of the working frame pulse to the input of the standby frame pulse and outputs a count value. , Detecting the advance or lag of the spare side frame pulse with respect to the active side frame pulse based on the frame length information of the working side data signal and the spare side data signal and the count value output from the counting circuit, When the frequency division ratio N is larger than the frequency division ratio M and is delayed, the frequency division ratio N is smaller than the frequency division ratio M, and when there is no advance or delay, the frequency division ratio N is made equal to the frequency division ratio M. The synchronization switching device according to claim 1, further comprising a control circuit that controls a frequency division ratio N of the frequency divider.