JPH08249889A - Sense circuit - Google Patents

Abstract

PURPOSE: To read out a minute difference voltage signal with less power consumption and at a high speed and to enable a sense circuit to be applied for the read-out of a DRAM by providing a circuit amplifying an input signal in accordance with a potential of the minute difference voltage signal read out by a sense amplifier. CONSTITUTION: In a sense circuit 10, a minute difference voltage signal outputted to a pair of bit line BL is sensed and amplified by a current amplifying type sense amplifier 12, and latch-outputted to a pair of data output line 'OUT'. Then the pair of bit line is amplified by a pair of input signal line amplifying circuit 14 in accordance with a potential of the pair of data output line 'OUT', that is, a potential of a minute difference voltage signal read out to the pair of data output line 'OUT'. Thereby, a minute difference voltage signal is sensed and amplified at a high speed, while it can be applied for even a memory in which stored information is destroyed by reading out data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense circuit, and more particularly, to a sense amplifier which reads out a minute difference voltage signal to an input signal line pair, senses / amplifies this signal and outputs it to an output signal line pair. The present invention relates to a sense circuit including means for amplifying an input signal line pair according to the potential of the signal line pair.

[0002]

2. Description of the Related Art For example, SRAM (static RA
M), DRAM (dynamic RAM), CAM (content address memory), and the like, as a means for detecting and amplifying a minute difference voltage signal read from a semiconductor memory at high speed,
A minute potential detection circuit called a sense amplifier is used. Typical sense amplifiers include a latch type sense amplifier, a current mirror type sense amplifier, a current detection type sense amplifier, etc., each of which is used according to its application. The structure, operation, and problems of these sense amplifiers will be described below.

First, FIG. 5 is a configuration circuit diagram of an example of a latch type sense amplifier. This latch type sense amplifier 40
Is composed of P-type MOS transistors (hereinafter referred to as PMOS) 42a, 42b, 46 and N-type MOS transistors (hereinafter referred to as NMOS) 44a, 44b, 48.

In the latch type sense amplifier 40,
PMOS 42a and NMOS 44a, and PMOS 42
b and the NMOS 44b together form a CMOS inverter, and the input terminal and the output terminal of these inverters are cross-coupled to each other and connected to the bit line BL and the inverted bit line BL_, respectively. The source ends of the PMOSs 42a and 42b forming the inverter are short-circuited and connected to the drain end of the PMOS 46. Similarly, the source ends of the NMOSs 44a and 44b are short-circuited to N.
It is connected to the drain end of the MOS 48. The source ends of the PMOS 46 and the NMOS 48 are connected to the power supply line and the ground line, respectively, and the gate ends thereof are connected to the control lines SAP and SAN, respectively.

Next, the operation of reading the data stored in the memory cell using the latch type sense amplifier 40 will be described assuming that the high level is stored in the memory cell. First, the control lines SAP and SAN are set to high level and low level, respectively, and the data line B
L and the inverted data line BL are precharged to the same potential, for example, the power supply potential, and kept in the high state. In this state, the PMOSs 42a, 42b, 46 and the NMOS 44 are
a, 44b, and 48 are all off.

Next, the precharge of the data line BL and the inverted data line BL is stopped, and the data signal (high level) and its inverted data signal (low level) are transferred from the memory cell to the data line BL and the inverted data line BL_, respectively. ) Is read. At this time, the data line BL is kept in the floating high state, but the inverted data line BL- is lowered from the floating high state by a minute voltage. Therefore, a minute voltage difference is generated between the data line BL and the inverted data line BL.

Subsequently, when the control line SAN is gradually set to the high level, the NMOS 48 gradually turns on,
The potentials at the source ends of the NMOSs 44a and 44b also gradually become low level. When the potential difference between the gate end and the source end of the NMOS 44b exceeds a threshold value, the NMOS 44b is turned on, and the drain end thereof, that is, the gate end of the NMOS 44a is turned to the low level, so that the NMOS 44a is turned off.

Finally, when the control lines SAP and SAN are set to low level and high level, respectively, the NMOS 44
Since the drain end of b, that is, the gate end of the PMOS 42a is at a low level, the PMOS 42a is turned on, and the drain end thereof, that is, the gate end of the PMOS 42b is turned to a high level, so that the PMOS 42b is turned off. In this way, the data signal and the inverted data signal read from the memory cell to the data line BL and the inverted data line BL_ are amplified and latched by the latch type sense amplifier 40, respectively, and the data line BL and the inverted data line BL_, respectively. Is output to.

In the latch type sense amplifier 40, a large number of memory cells are commonly connected to the data line BL and the inverted data line BL. Therefore, in an element such as a memory cell having a small driving capability for outputting a minute difference voltage signal, the data line BL and the inverted data line BL
It is impossible to change the electric potential of the instantly. Therefore, in the latch type sense amplifier 40, there is a possibility that the latch type sense amplifier 40 malfunctions and latches wrong data unless the operation is started after a sufficient voltage difference is provided between the data line BL and the inverted data line BL. , The latch type sense amplifier 4 after reading the data signal and the inverted data signal
There is a problem that a time margin is required before 0 is operated.

Next, FIG. 6 is a configuration circuit diagram of an example of a current mirror type sense amplifier. This current mirror type sense amplifier 50 is a current mirror type load PM.
OS 52a, 52b and NM for inputting a minute difference voltage signal
The OS 54a and 54b and the NMOS 56 which is a constant current source.

In the current mirror type sense amplifier 50, the source terminals of the PMOSs 52a and 52b are both connected to the power supply line, and the gate terminals thereof are short-circuited to make the PMOS5.
The drain end of the PMOS 52b is connected to the data output line OUT. Also, N
The gate ends of the MOSs 54a and 54b are data lines B, respectively.
It is connected to the L and inverted data lines BL, its drain ends are connected to the drain ends of the PMOSs 52a and 52b, respectively, and its source end is short-circuited and connected to the drain end of the NMOS 56. The source end of the NMOS 56 is connected to the ground line, and the gate end thereof is the control line SA.
It is connected to N.

Next, the operation of reading the data stored in the memory cell using the current mirror type sense amplifier 50 will be described. First, the control line SAN is set to the high level, and the NMOS 56 is always on.
Further, the data line BL and the inverted data line BL- are precharged to the same potential, for example, the power supply potential, to be in the high state.

Then, the precharge is stopped and the data line B
A data signal and its inverted data signal are read from the memory cell to the L and inverted data line BL. At this time, one of the data line BL and the inverted data line BL from which the high level is read is maintained in the floating high state, but the other is lowered from the floating high state by a minute voltage. Therefore, a minute voltage difference is generated between the data line BL and the inverted data line BL.

For example, when the potential of the inverted data line BL- is lower than that of the data line BL, the NM level is higher than that of the NMOS 54a.
Since the current drive capacity g _{m of the} OS 54b decreases, the NMO
NMOS rather than the drain end (data output line) of S54b
The potential is lower at the drain end of 54a. As a result, the current drive capability g _m of the PMOS 52b is increased, the amplification is accelerated, and the potential of the data output line OUT is rapidly increased.

On the other hand, when the potential of the data line BL becomes lower than the potential of the inverted data line BL_, the current driving capability g _{m of the} NMOS 54a becomes smaller than that of the NMOS 54b.
The potential at the drain end (data output line) of the NMOS 54b is lower than that at the drain end of the MOS 54a. As a result, the current driving capability g _m of the PMOS 52b is reduced, the amplification is accelerated, and the potential of the data output line OUT is rapidly lowered. In this way, from the memory cell to the data line B
The data signal and the inverted data signal read to the L and the inverted data line BL are amplified by the current mirror type sense amplifier 50 and output to the data output line OUT.

The current mirror type sense amplifier 50
Since the logic level of the data output line OUT does not reach from the power supply potential to the ground potential, it is usually configured in multiple stages or a level shifter or the like is used at the same time. In addition, the current mirror type sense amplifier 50 is used as a pair, the data line BL and the inverted data line BL of the other current mirror type sense amplifier 50 are exchanged, and the inverted data output line OUT.
It is generally configured to get ￣.

Unlike the latch type sense amplifier 40, the current mirror type sense amplifier 50 does not latch the data output signal and the inverted data output signal, so that there is no fear of malfunction. However, in the current mirror type sense amplifier 50, since the potential of the data output line OUT is determined by the ratio of the currents flowing in the NMOSs 54a and 54b, the current always flows as described above. Therefore, since the current consumption increases, the power consumption increases when a large number of bits are read at the same time.

Next, FIG. 7 is a configuration circuit diagram of an example of a current detection type sense amplifier. The current detection type sense amplifier 60 includes PMOS 20a, 20b and NMOS 22.
current driving type latch circuit 16 including a and 22b, and NM
The current drive circuit 18 includes OSs 24a, 24b, and 26.

In the current drive type sense amplifier 60, the PMOS 20 constituting the current drive type latch circuit 16 is provided.
a and NMOS 22a, and PMOS 20b and NM
Together with the OS 22b, a CMOS inverter is formed, and the input terminal and the output terminal of these inverters are cross-coupled to each other, and the inverted data output line OUT
And a data output line OUT. Also,
Source ends of the PMOSs 20a and 20b forming the inverter are short-circuited and connected to the power supply line.

The NMO which constitutes the current drive circuit 18
The drain ends of S24a and S24b are connected to the source ends of the NMOSs 22a and 22b of the current drive type latch circuit 16, the gate ends thereof are connected to the bit line BL and the inverted bit line BL, respectively, and the source ends thereof are short-circuited. Is connected to the drain end of the NMOS 26. The gate end of the NMOS 26 is connected to the control line SAN, and the source end thereof is connected to the ground line.

Next, the operation of reading the data stored in the memory cell using the current detection type sense amplifier 60 will be described assuming that the high level is stored in the memory cell.

First, the control line SAN is set to the low level, and the data line BL and the inverted data line BL- are precharged to the same potential, for example, the power supply potential, and set to the high state. In addition, the data output line OUT, the inverted data output lines OUT and N by a precharge means (not shown).
The drain ends of the MOSs 24a and 24b are both precharged to the power supply potential. In this state, the PMOSs 20a, 20b and NMO which constitute the current drive type latch circuit 16 are formed.
The S22a, 22b, and the NMOSs 24a, 24b and the NMOS 26 forming the current drive circuit 18 are all in the off state.

Then, the precharge is stopped and the data signal (high level) and its inverted data signal (low level) are read from the memory cell to the data line BL and the inverted data line BL. At this time, the potential of the data line BL is maintained in the floating high state, but the potential of the inversion data line BL- drops by a minute voltage from the floating high state. Therefore, a minute voltage difference is generated between the data line BL and the inverted data line BL.

Subsequently, when the control line SAN is set to the high level, the NMOS 26 is turned on, and the NMOSs 24a and 2a.
4b includes a data line BL and an inverted data line BL, respectively.
Since the drain current according to the potential of ￣ flows,
The charge at the drain end of the NMOS 24a is extracted faster than at the drain end of 24b. And the NMOS 24
When the potential difference between the gate end and the source end of the a exceeds a threshold value, the a turns on, and the drain end, that is,
The inverted data output line OUT_ becomes low level.

When the inverted data output line OUT_ goes low, the PMOS 20b and the NMOS 22b are turned on and off, respectively, and the data output line OUT goes high. Further, when the data output line OUT becomes high level, the PMOSs 20a and N
Since the MOS 22a is turned off and turned on respectively, the low level of the inverted data output line OUT-is determined. In this way, the data signal and the inverted data signal read from the memory cell to the data line BL and the inverted data line BL are amplified and latched by the current detection type sense amplifier 60, and the data output line OUT and the inverted data output, respectively. Output to line OUT.

The current detection type sense amplifier 60 is superior to the latch type sense amplifier 40 in terms of high speed operation and superior to the current mirror type sense amplifier 50 in terms of low power consumption.

However, like the current detection type sense amplifier 60 and the current mirror type sense amplifier 50, the minute difference voltage signal outputted to the input signal line pair consisting of the bit line BL and the inverted bit line BL is amplified, In the sense amplifier which outputs this to the output signal line pair consisting of the data output line OUT and the inverted data output line OUT_, the bit line BL and the inverted bit line BL_ which are the input signal line pair are not amplified. For this reason, it becomes necessary to rewrite a memory, such as a DRAM, whose stored information is destroyed when the data of the memory cell is read, and these sense amplifiers 60 and 50 can be used. There was a problem that it could not be done.

[0028]

SUMMARY OF THE INVENTION The object of the present invention is to solve various problems based on the above-mentioned prior art, to read a minute difference voltage signal to a pair of input signal lines, and to detect and amplify the minute difference voltage signal to output the signal line. In the sense amplifier for outputting to the pair, by further amplifying the input signal line pair from which the minute difference voltage signal is read, the reading operation can be performed at high speed with low power consumption, and the stored information can be read by reading the data. It is an object of the present invention to provide a sense circuit which can be applied to a memory in which memory is destroyed.

[0029]

In order to achieve the above object, the present invention provides a small difference voltage signal which is controlled by a first control line and read to an input signal line pair consisting of a bit line and an inverted bit line. A sense amplifier that senses and amplifies and outputs to an output signal line pair consisting of a data output line and an inverted data output line, and a second control line, and controls the input according to the potential of the output signal line pair. A sense circuit comprising an input signal line pair amplifier circuit for amplifying a signal line pair.

Here, it is preferable that the first and second control lines are the same.

Further, the input signal line pair amplifier circuit has its source terminals both connected to the power supply line, its gate terminals connected to the inverted data output line and the data output line, and its drain terminals respectively connected to the above-mentioned data output line. First and second P-type MOS transistors connected to the bit line and the inverted bit line, and a source N connected to the ground line and a gate end connected to the second control line for grounding N -Type MOS transistor and its source end are both connected to the drain end of the grounding N-type MOS transistor, its gate end is connected to the inversion bit line and the bit line, and its drain end is the bit line and the bit line, respectively. First connected to the inverted bit line
And a second N-type MOS transistor.

In the input signal line pair amplifier circuit, the source ends thereof are both connected to the power supply line, the gate ends thereof are connected to the inverted data output line and the data output line, and the drain ends thereof are respectively set to the above-mentioned. First and second P-type MOS transistors connected to the bit line and the inverted bit line, and a source N connected to the ground line and a gate end connected to the second control line for grounding N -Type MOS transistor and its source end are both connected to the drain end of the grounding N-type MOS transistor, its gate end is connected to the inverted data output line and the data output line, and its drain end is the bit, respectively. A line and first and second N-type MOS transistors connected to the inverted bit line.

Further, it is preferable that the grounding N-type MOS transistors are individually provided at the source ends of the first and second N-type MOS transistors.

[0034]

The sense circuit of the present invention is a sense amplifier which senses and amplifies a minute difference voltage signal read to an input signal line pair and outputs it to an output signal line pair. The input signal line pair amplifying circuit for amplifying the input signal line pair is provided. Therefore, according to the sense circuit of the present invention, the minute difference voltage signal read to the input signal line pair is sensed and amplified at high speed with low power consumption by the sense amplifier, and is output by the input signal line pair amplifier circuit. Since the input signal line pair is also amplified in accordance with the potential of the signal line pair, the present invention can be applied to a memory such as a DRAM whose information is destroyed by reading the data.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The sense circuit of the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a configuration circuit diagram of an embodiment of the sense circuit of the present invention. This sense circuit 10 has a bit line B
The minute difference voltage signal read to the input signal line pair consisting of the L and the inverted bit line BL is amplified and latched, and the data output line OUT and the inverted data output line OUT
Of the current detection type sense amplifier 12 which outputs to the output signal line pair consisting of, and the bit line BL and the inverted bit line BL depending on the potentials of the data output line and the inverted data output line amplified by the current detection type sense amplifier 12, respectively. BL￣
And an input signal line pair amplifying circuit 14 for amplifying.

In the sense circuit 10, the configuration of the current detection type sense amplifier 12 is different from that of the current detection type sense amplifier 60 shown in FIG. 7 in that it includes a data output line BL, an inverted data output line BL and a power supply line. The difference between them is that they have precharge PMOSs 28a and 28b, respectively. Therefore, the same components are designated by the same reference numerals and the description thereof will be omitted. That is, in the current detection type sense amplifier 12, the source ends of the PMOSs 28a and 28b are both connected to the power supply line, the gate ends thereof are both connected to the control line EQ, and the drain ends thereof are the inverted data output lines OUT and. Data output line OUT
It is connected to the. The control lines EQ and SAN may be configured to use the same signal.

On the other hand, the input signal line pair amplifier circuit 14 has a PM
OS 30a, 30b, NMOS 32a, 32b, N
It is composed of a MOS 34. In the input signal line pair amplifier circuit 14, the source ends of the PMOSs 30a and 30b are both connected to the power supply line, and the gate ends thereof are connected to the inverted data output line OUT_ and the data output line OUT, respectively. Also, the gate end of the NMOS 32b and P
The drain ends of the MOS 30a and the NMOS 32a are both connected to the bit line BL.
And the drain ends of the PMOS 30b and the NMOS 32b are both connected to the inverted bit line BL. The source ends of the NMOSs 32a and 32b are short-circuited and connected to the drain end of the NMOS 34, and the NMOS3
The source end of 4 is connected to the ground line, and its gate end is connected to the control line SAN. Note that the NMOS 34 may be provided for each of the NMOSs 32a and 32b.

Next, regarding the operation when reading the data stored in the memory cell using the sense circuit 10,
Assuming that the high level is stored in the memory cell,
This will be described using the timing chart shown in FIG.

First, the control line SAN is set to the low level, and the data line BL and the inverted data line BL- are precharged to the same potential, for example, approximately the center potential of the power supply potential and the ground potential, to the intermediate potential. In addition, the control line EQ
Data output line OUT by setting ￣ to low level
And the inverted data output line OUT- are both precharged to the power supply potential, and the drain ends of the NMOSs 24a and 24b are both precharged to the power supply potential by a precharge means (not shown).

In this state, the current detection type sense amplifier 1
2, PMOS 20a, 20b, NMOS 22
a, 22b, NMOS 24a, 24b, NMOS 26,
And the PMOS 3 forming the input signal line pair amplifier circuit 14.
0a, 30b, NMOS 32a, 32b, NMOS
All 34 are off.

Then, the data signal (high level) and its inverted data signal (low level) are read from the memory cell to the data line BL and the inverted data line BL. At this time, the potential of the data line BL rises from the intermediate potential by a minute potential, and conversely, the potential of the inverted data line BL- drops by a minute potential from the intermediate potential. Therefore, a minute voltage difference is generated between the data line BL and the inverted data line BL.

Subsequently, when the control lines SAN and EQ are both set to the high level, the PMOSs 28a and 28b are turned off, so that the precharge to the data output line OUT and the inverted data output line OUT is stopped, and at the same time, By turning on the NMOS 26, N
A drain current corresponding to the potentials of the data line BL and the inverted data line BL_ flows through the MOSs 24a and 24b, respectively.
The charge at the drain end of is drained faster. And
The NMOS 24a is turned on when the potential difference between its gate end and source end exceeds a threshold value, and its drain end, that is, the inverted data output line OUT- is at low level.

When the inverted data output line OUT_ goes low, the PMOS 20b and the NMOS 22b turn on and off, respectively, and the data output line OUT goes high. Further, when the data output line OUT becomes high level, the PMOSs 20a and N
Since the MOS 22a is turned off and turned on respectively, the low level of the inverted data output line OUT-is determined. In this way, the data signal and the inverted data signal read from the memory cell to the data line BL and the inverted data line BL are amplified and latched by the current detection type sense amplifier 60, and the data output line OUT and the inverted data output, respectively. Output to line OUT.

On the other hand, in the input signal line pair amplifier circuit 14, as described above, when the control line SAN becomes high level, the NMOS 34 is turned on. In addition, when the data output line OUT and the inverted data output line OUT are set to the high level and the low level, respectively, the PMOS 30
a and 30b are turned on and off, respectively.
Therefore, the drain end of the PMOS 30a, that is, the bit line BL is charged up by the PMOS 30a and becomes high level. Further, since the NMOS 30b is also turned on, the drain end of the NMOS 30b, that is, the inverted bit line BL_ is discharged by the NMOS 30b to a low level, whereby the off state of the NMOS 32a is determined, and these data are input signal line pair. It is latched by the amplifier circuit 14.

As described above, according to the sense circuit 10 of the present invention, the bit line B is generated by the current amplification type sense amplifier 12.
The minute difference voltage signal output to the L and inverted bit line BL is sensed and amplified, and this is output to the data output line OU.
It is possible to perform a latch output to T and the inverted data output line OUT, and the potential of the data output line OUT and the inverted data output line OUT, that is, the bit line BL and the inverted bit by the input signal line pair amplifier circuit 14. The bit line BL and the inverted bit line BL_ can be amplified according to the potential of the minute difference voltage signal read to the line BL_.

Next, FIG. 3 shows a configuration circuit diagram of another embodiment of the input signal line pair amplifier circuit of the sense circuit of the present invention.

The input signal line pair amplifying circuit 36 is a PMO.
S30a, 30b, NMOS 32a, 32b, NM
It is composed of OSs 38a and 38b. In the input signal line pair amplifier circuit 36, the PMOSs 30a and 30b
Both source ends of are connected to the power supply line. Also, P
The gate ends of the MOS 30a and the NMOS 32a are both connected to the inverted data output line OUT_, and the drain ends thereof are both connected to the bit line BL. Similarly, PM
The gate ends of the OS 30b and the NMOS 32b are both connected to the data output line OUT, and the drain ends thereof are both connected to the inversion bit line BL. Also, NMOS
The drain ends of 38a and 38b are NMOS 32, respectively.
The source ends of a and 32b are connected, the gate ends thereof are connected to the control line LEN, and the source ends thereof are both connected to the ground line.

The control line LEN connected to the gate ends of the NMOSs 38a and 38b is the sense circuit 1 shown in FIG.
This is a signal in which the operation timing of the control line SAN at 0 is delayed. In this input signal line pair amplifier circuit 36,
The gate ends of the NMOSs 38a and 38b may be controlled by the control line SAN, or may be controlled by the control line LEN for the reason that timing adjustment is necessary or the like, and may be appropriately changed.

The NMOSs 38a and 38b controlled by the control line LEN are the sense circuits 10 shown in FIG.
The input signal line pair amplifier circuit 14 corresponds to the NMOS 34. Thus, the sense circuit 1 of the present invention
0, the NMOS 34 of the input signal line pair amplifier circuit 14
Are NMOSs 38a, 38 of the input signal line pair amplifier circuit 36.
b, the bit line BL side and the inverted bit line BL
One may be provided for each.

Next, regarding the operation at the time of reading the data stored in the memory cell by using the sense circuit 10 having the input signal line pair amplifying circuit 36, it is assumed that a high level is stored in the memory cell. This will be described using the timing chart shown in FIG.

As described above, the minute difference voltage signal output to the bit line BL and the inverted bit line BL is sensed and amplified by the current detection type sense amplifier 12 to output the data output line OUT and the inverted data output line, respectively. OUT
Latch output to. That is, the current detection type sense amplifier 1
The operation of 2 is exactly the same, and the high level and the low level are output to the data output line OUT and the inverted data output line OUT_, respectively.

On the other hand, in the input signal line pair amplifier circuit 14, when the control line LEN becomes high level, the NMOS 38
a and 38b are turned on. In addition, the data output line OU
When the T and inverted data output lines OUT_ are determined to be high level and low level, respectively, both the PMOS 30a and the NMOS 32b are turned on, and the PMOS 3
Both 0b and the NMOS 32a are turned off. Therefore, the drain end of the PMOS 30a, that is, the bit line BL is charged up by the PMOS 30a to a high level, and the drain end of the NMOS 30b,
That is, the inverted bit line BL-is discharged by the NMOS 30b and becomes low level, and these data are latched by the input signal line pair amplifier circuit 36.

Thus, the input signal line pair amplifier circuit 36 can also amplify the bit line BL and the inverted bit line BL_ in accordance with the potentials of the data output line OUT and the inverted data output line OUT_. it can. Therefore,
According to the sense circuit of the present invention, the data read from the memory cell can be rewritten in the same memory cell, so that the data stored in the memory cell is destroyed when the data is read from the memory cell, for example, in DRAM. It can also be used for memory.

Although the sense circuit of the present invention has been described based on the embodiment, the sense circuit of the present invention is not limited to the above-described embodiment.

For example, the sense amplifier used in the sense circuit of the present invention is not limited to the current detection type sense amplifier shown in the embodiment, but an input signal line from which a minute difference voltage signal is read out, for example, a bit line and If the sense amplifier has a configuration in which the inverted bit line and the output signal line for amplifying and outputting the inverted bit line, for example, the data output line and the inverted data output line are provided separately, what kind of sense amplifier is used? It may be. Further, the circuit configuration of the input signal line pair amplifier circuit used in the sense circuit of the present invention is not limited, and the signal line from which the minute difference voltage signal is read can be amplified by using the signal amplified by the sense amplifier. It goes without saying that any circuit configuration is possible if possible.

[0057]

As described in detail above, the sense circuit of the present invention includes a sense amplifier which senses and amplifies a minute difference voltage signal read to the input signal line pair and outputs it to the output signal line pair. An input signal line pair amplifier circuit for amplifying the input signal line pair according to the potential of the output signal line pair of the sense amplifier is provided. Therefore, according to the sense circuit of the present invention, the minute difference voltage signal can be sensed / amplified at high speed with low power consumption by the sense amplifier, and further, the input signal line pair amplifier circuit can further detect and amplify the minute difference voltage signal. Can be applied to any type of memory, and can be applied to any type of memory, such as DRAM, whose stored information is destroyed by reading data. is there.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a sense circuit of the present invention.

FIG. 2 is a timing diagram of an embodiment for explaining the operation of the sense circuit of the present invention shown in FIG.

FIG. 3 is a configuration circuit diagram of another embodiment of the input signal line pair amplifier circuit of the sense circuit of the present invention.

FIG. 4 is a timing diagram of an example for explaining the operation of the sense circuit of the present invention when the input signal line pair amplifier circuit shown in FIG. 3 is used.

FIG. 5 is a configuration circuit diagram of an example of a latch type sense amplifier.

FIG. 6 is a configuration circuit diagram of an example of a current mirror type sense amplifier.

FIG. 7 is a configuration circuit diagram of an example of a current detection type sense amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 sense circuit 12,60 current detection type sense amplifier 14,36 input signal line pair amplification circuit 16 current drive type latch circuit 18 current drive circuit 20a, 20b PMOS 22a, 22b, 24a, 24b, 26 NMOS 30a, 30b PMOS 32a, 32b, 34, 38a, 38b NMOS 40 Latch type sense amplifier 42a, 42b, 46 PMOS 44a, 44b, 48 NMOS 50 Current mirror type sense amplifier 52a, 52b PMOS 54a, 54b, 56 NMOS BL bit line BL | inverted bit line OUT Data output line OUT ￣ Inverted data output line SAN, SAP, LEN, EQ ￣ Control line

Claims (5)

[Claims] 1. A small difference voltage signal controlled by a first control line and read to an input signal line pair consisting of a bit line and an inverted bit line is sensed and amplified, and the minute differential voltage signal is output from the data output line and the inverted data output line, respectively. A sense amplifier for outputting to the output signal line pair, and an input signal line pair amplifier circuit which is controlled by a second control line and amplifies the input signal line pair according to the potential of the output signal line pair. Sense circuit. 2. The sense circuit of claim 1, wherein the first and second control lines are the same. 3. The input signal line pair amplifier circuit has source terminals both connected to a power supply line, gate terminals connected to the inverted data output line and the data output line, and drain terminals respectively connected to the inverted data output line and the data output line. Bit line and first and second P-type MOS connected to the inverted bit line
A transistor, a ground N-type MOS transistor whose source end is connected to the ground line and whose gate end is connected to the second control line, and both source ends thereof are the drain end of the ground N-type MOS transistor. A first and a second N-type MOS transistor whose gate ends are connected to the inversion bit line and the bit line, respectively, and whose drain ends are connected to the bit line and the inversion bit line, respectively. The sense circuit according to claim 1 or 2, further comprising: 4. The input signal line pair amplifier circuit has source terminals both connected to a power supply line, gate terminals respectively connected to the inverted data output line and the data output line, and drain terminals respectively connected to the inversion data output line and the data output line. Bit line and first and second P-type MOS connected to the inverted bit line
A transistor, a ground N-type MOS transistor whose source end is connected to the ground line and whose gate end is connected to the second control line, and both source ends thereof are the drain end of the ground N-type MOS transistor. First and second N-type MOS transistors each having a gate end connected to the inverted data output line and the data output line and a drain end connected to the bit line and the inverted bit line, respectively. The sense circuit according to claim 1, further comprising: 5. The sense circuit according to claim 3, wherein the grounding N-type MOS transistor is individually provided at source ends of the first and second N-type MOS transistors.