JPH0824395B2 - Addressing device - Google Patents

Description

Description: INDUSTRIAL APPLICABILITY The present invention is useful in programmable remote control transmitters for consumer electronic products such as video cassette recorders, cable converters, video disc players, televisions and the like. Regarding memory saving configuration.

BACKGROUND OF THE INVENTION As an infrared (IR) remote control device for consumer electronic products, any one of a number of electronic products manufactured by different manufacturers and each using different remote control signal code formats can be used. There is a tendency to use multi-brand universal remote control hand units to control. The universal remote control hand unit provides the convenience that the user only needs to use one remote control hand unit, and most, if not all, of the features of consumer electronic products. Can be controlled.

The number of different functions and different remote control command signal formats that a single universal remote control hand unit can handle depends largely on the amount of memory available for remote control code storage.

There are two basic types of universal remote control hand units. Systems based on random access memory (RAM) are often "learned"
It is called a remote control hand unit. With this type of remote control hand unit, it is necessary to "teach" the remote control hand unit the desired functionality of the user's original hand unit. This normally switches the "learning" remote control hand unit to "learning mode" so that the "learning" remote control hand unit can receive IR transmissions from the emulated hand unit. This is done by physically facing the two hand units. This learning process begins as an information storage process, where IR transmissions are recorded as they are received by the learning remote control unit. After this initial "raw" data storage, the raw data is analyzed and compressed, and then the final compressed form of this data is stored in RAM. When the universal remote control hand unit is used in remote control mode to send commands,
The stored compressed code is read from memory, decompressed (returning the compressed one) and the resulting signal transmitted.

A read only memory (ROM) based system is a set of devices, usually a television receiver (T).
V), video cassette recorder (VCR) and cable converters only. In this type of hand unit, all different code types must be pre-programmed for all functions of each controlled device. Also, the remote control code is typically compressed in some way to occupy as little memory space as possible.

Due to the limited memory space, the more efficient the compression method for each compression method, the more functions can be stored. Another way to save memory space is to reduce the number of program instructions required to address the memory by providing an efficient routine to address the memory.
The present invention is directed to this end, and in particular relates to saving memory space when so-called "indexed-addressing" is used.

In microprocessor software, the use of "matrixes" (i.e. groups of memory locations) is quite common and is commonly used for look-up tables and / or data tables. In fact, lookup and data tables are so commonplace that most microprocessors include an "index register" that can be used to indirectly access the data. For example, X = 8 and the pointer (POINTER) is data
If at the beginning of the table (in memory), LDA POINTER, X retrieves the 8th byte after POINTER in memory and stores it in the accumulator. Ie LDAPOINTER, X
Is a combination of POINTER values (16-bit address)
Is the instruction to read data by the microcomputer from the memory location addressed by the value stored in the X register. This is a very effective method but requires a large memory section to address the individual matrices.

It is an object of the invention to save the ROM memory size in a ROM-based remote control unit.

EFFECT OF THE INVENTION It is not necessary to store the code common to all subroutines individually in ROM.

SUMMARY OF THE INVENTION It is understood that a single subroutine is used to retrieve all the data stored in any of the matrices. To address the individual matrices, a single subroutine is modified by adding the desired matrix start positions. Data about the starting position is stored in the table.

EXAMPLE FIG. 1 shows a device suitable for use as a learning type remote control hand unit of the type described above. Controller 100 may be a microprocessor (as used herein, the terms microprocessor and microcomputer are synonymous).

The controller 100 receives from the clock oscillator 110 clock signals that set the timing of the various functions of the controller 100. Controller 100 addresses memory 120, which may or may not be internal to controller 100, according to programmed instructions. Memory 120 has a general purpose (or scratch pad) area 122 and a data area 124.
Is included. Also, the controller 100 uses the numeric keys 0-9,
Data entered by the user is received by a keyboard 130 which comprises a group of keys 132 including a channel up key, a channel down key, and a power on / off key. Keyboard 130 may also include a switch 134 to initiate a "learn mode" (discussed below). This switch is shown on keyboard 130 as key 134, but it could be a separate toggle switch located elsewhere on the remote control hand unit. In the embodiment of FIG. 1, key 134
Shall exhibit the "toggle" property. Ie, key 13
Pressing 4 once enters the learning mode, pressing key 134 twice returns the remote control hand unit to the normal remote control mode, where user commands are sent to the controllable device.

When in learning mode, the IR receiver 140 is the IR transmitted by the emulated remote control hand unit.
It receives the signals and provides digital data representing these IR signals to controller 100. Controller 100 is "raw"
General purpose memory 12 (ie uncompressed) data
Store in 2. The "raw" data is then compressed and stored for later retrieval. An example of a remote control device that compresses a code for storage is U.S. Pat. No. 4,623,8 issued to Welles II.
No. 87 is disclosed.

In normal remote control mode, when it is desired to send a remote control signal for a command, the controller 100 decompresses the stored code, and the resulting uncompressed code is burst and space for transmission. Send the proper sequence of to the output unit 160 to assemble. Clock oscillator 110 is an output unit
A clock signal is supplied to a frequency divider 150 which supplies a signal of a lower frequency to 160. This lower frequency signal forms the burst component of the data stream provided to IR diode 170 for transmission.

Alternatively, divider 150 may be omitted and burst pulses are generated by controller 100 by quickly "toggling" the output.

In ROM-based systems, compression is not done by the remote control hand unit,
Pre-made at the factory to generate compressed control code stored in ROM. In this case, IR receiver 140
And the "learn mode" key 134 can be omitted from the remote control hand unit.

The individual commands for each controlled device are stored in each memory location in memory. FIG. 2 shows a number of memory locations grouped into a table (ie, a one-dimensional matrix). Each group 215,225,235 in Figure 2 has 256
Although shown as having one storage location, each group can take any number of storage locations, up to a maximum of 256 (256 storage location limits are discussed below). I want you to understand. It is often convenient for a programmer to organize a group of storage locations containing relevant data into a multidimensional matrix.
FIG. 3 shows a two-dimensional matrix in which the memory locations are arranged in columns and rows (ie, a two-dimensional matrix).
FIG. 5 shows a three-dimensional matrix composed of memories called page memories because the memory organization looks like pages of a book.

Similar reference numbers in FIGS. 2 and 3 indicate elements having similar functions. Therefore, only FIG. 3 will be described in detail. As shown in FIG. 3, the individual columns of the matrix (315, 325, 335) are divided into individual subroutines (31
0,320,330). These subroutines use the index pointer scheme to address individual rows in columns. The pointer indicates the start address (AO, BO, CO) of the desired column. The index value is stored in a register existing in the microcomputer. This register is known as the X register. The value in the X register is added to the value in the pointer register,
It becomes the final address of the desired storage location. X register is 8
Since it is a bit length, values up to 255 can be stored. Therefore, the pointer register value is "offset" by up to 255 additional locations.
For a small matrix, a single 8-bit index register does not cause any problems, even if it consists of several dimensions.

For multi-dimensional matrix M (i, j, k, ...) i <2 ^** n _i , j <2 ^** n _j , k <2 ^** r _k , ... n _i + n _j + n _k + ... <= 8, (where the 2 ^** n _i notation is known in the field of computer programming to mean n _i raised to the power of 2.) M is the index register as It can be assigned by bit mapping.

n _i bits + n _j bits + n _k bits + ... As an example, in the above equation, “i” represents the number of individual columns of the matrix, “j” represents the number of individual rows of the matrix, and “k” represents (the Individual pages of columns and rows can be represented (as shown in FIG. 5).

Therefore, any multidimensional matrix of i × j × k × ... <= 256 bytes can be processed by considering it as a one-dimensional matrix and directly using the index register. Although not necessarily the most efficient method of processing this type of matrix, this method is well known and commonly used. For larger matrices, i.e. _ni + _nj + _nk + ...> 8, another addressing method must be used.

Some matrices, called irregular matrices, have a range of elements (eg, elements j ₀ -j ₄ , i _{1 at} i ₀₎ .
Element j ₀ -j ₁ in i, element j ₀ -j ₇ in i _2, etc.) are used. An example of such an irregular matrix is
It is shown in Figure 3a. Allocating memory for all unused bytes in such a matrix means that a large portion of memory space is wasted. A typical way to address an irregular matrix is to send the row index to a column-indexed subroutine that retrieves the data. This can be best illustrated by example. For example, memory location I2_D in Figure 3a.
ATA5 (memory element i = 2, j = 5, where M (i <4, j <
8)) to retrieve the data bytes stored in the following subroutine (Motorola microprocessor 6805)
Written in assembly language for) can be used. Those skilled in the art will appreciate that IO_DATA is a 16-bit pointer to the beginning of the data table. Alternatively, IO_DATA can be thought of as a label representing the 16-bit address of IO_DATA 0, the first location in the matrix of storage locations.

In the example above, the individual subroutines, IO_GET, I1
_GET and I2_GET are used to retrieve data from each matrix. For simplicity, a similar fourth
Subroutine I3_GET is not shown. These individual subroutines are designated by reference numerals 310a, 320a, 330a, 3a in FIG. 3a.
Each is shown at 40a. Each of these individual subroutines is stored in ROM and is 5 bytes long. The 16-bit address of the individual column being addressed (eg, HIGH ADORESS OF IO_DATA 0, LOW, as each subroutine is stored in ROM and cannot be modified.
Note that it must include ADDRESS OF IO_DATA 0).

The routine shown above enters GET_VALUE, which is part of the program that determines the numerical value of the I index (ie the pointer to the desired column) and calculates the jump address of the microcomputer to retrieve the desired data. The IO_GET subroutine starts at memory location IO_GET + 0. The I1_GET subroutine starts with IO_GET + 5.
Similarly, the I2_GET subroutine starts at IO_GET + 10. The index must be multiplied by 5, as shown in the GET_VALUE routine shown above, so that the correct subroutine is jumped to to retrieve the desired data. It should be noted that 3 out of 5 bytes (TAX, LDA, RTS) of each subroutine such as IO_GET, I1_GET and I2_GET are the same and are repeated in each subroutine. For such small matrices this method is not very efficient. However, for larger tables, this method has been used to avoid wasting a lot of memory. This method is I_IN
Limited to DEX <= 51 (5 * 51 is equal to 255, which is the largest value that can be stored in the 8-bit X register), otherwise the column jump cannot be done exactly.

This method uses a fairly large index to reference the matrix, but the code needed to do it grows very quickly over many rows. As mentioned earlier, this method only applies to matrices with 51 columns and less than 256 rows. The devices and methods described in this specification obviate such limitations.

Instead of using the indexed column subroutine to retrieve the desired row data, the apparatus according to the invention uses one general subroutine to retrieve the data from all columns.

Next, the present invention will be described with reference to FIG. As explained above, all subroutines with indexed columns have the same size and format.

When initialized in accordance with the present invention, this general purpose subroutine (FETCH) 450 is retrieved from ROM 400 and stored in RAM 410 as a single subroutine 420 per opcode by opcode and accessed in the following manner. To be done.

In RAM space this is defined as:

The bytes LDA_OPCODE and RTS_OPCODE in RAM are initialized to correct the operation code for the individual microprocessors before this routine is called and their values remain unchanged thereafter. That is, the memory location LDA_OPCODE is read by the controller from the 1-byte data stored in the memory location where the address is stored immediately after the instruction offset by the value stored in the X register when it is executed. The code byte to be sent is put.

When the FETCH routine is first read from ROM and stored in RAM, storage locations HIGH_INDX and LOW_INDX may contain meaningless data to be stored there. The data at storage locations HIGH_INDX and LOW_INDX indicates the beginning of each matrix (ie, group of storage locations) in which the desired data is stored. The correct data is written to these memory locations as follows.

The FETCH subroutine is a table (COLUMN_PTR) of contiguous stored addresses called column pointers.
Access 440 and store column pointers in storage locations HIGH_INDX and LOW_INDX.

IO_DATA, I1_DATA, etc. are 16-bit addresses,
It is stored as two 8-bit bytes with the high-order 8 bits of the first occurring address. Since each of these addresses is 2 bytes long, the IO_DATA address starts at memory location COLUMN_PTR + 0 and the I1_DATA address is C
It starts from OLUMN_PTR + 2 and the address of I2_DATA is COLUMN.
It starts from _PTR + 4. Therefore, in order to correctly access the correct address to retrieve the desired data, the index is multiplied by 2, as shown in the GET_VALUE routine just shown. This method allows you to call a matrix with up to 128 (0-127) columns and up to 256 (0-255) rows, which requires significantly less memory. The 128 column limit arises from 0-127 columns x 2 bytes (for each), the last count value of which is equal to 255, and this highest value can be stored in an 8-bit X register. This extended data access capability comes at the small cost of adding ROM-based code that initializes the "program" RAM with the proper code.

An additional byte in the GET_VALUE routine removes the INCX instruction and replaces the instruction immediately before STA LOW_INDX with LDA COLUMN_PTR +
Note that it is secured by changing to 1, X.

If desired, a matrix of size 256 columns by 256 rows can be addressed by modifying the program shown above as shown below.

In this example, the high and low bytes of the column pointer are stored in separate tables (HI_COL_PT), as shown in FIG.
R and L O_COL_PTR). Both tables are indexed by the same value stored in the X register. Therefore, it is not necessary to multiply the index value by 2 to "skip" the lower bytes as in the previous example. Since there is no need to multiply by 2, all 256 addressable memory locations can be used to store the starting location of the matrix.

Although the present invention has been described with reference to an embodiment in a remote control hand unit, the scope of the present invention is not limited thereto.

[Brief description of drawings]

FIG. 1 shows in block diagram form a remote control hand unit of the learning remote control type in which the present invention is embodied. FIG. 2 is a block diagram showing a known configuration of a memory location in a read only memory (ROM). FIG. 3 is a block diagram showing another configuration of the ROM shown in FIG. Figure 3a shows an example of an irregular matrix of memory locations in block diagram form. FIG. 4 is a block diagram showing an embodiment of the present invention. FIG. 5 shows a known arrangement for a "page" memory. FIG. 6 is a block diagram showing an embodiment of the present invention. 100 …… Control device, 120 …… Memory, 130 …… Keyboard, 4
00 …… Read-only memory (ROM), 410 …… RAM, 420…
… Subroutine, 440 …… Table of addresses, 4
50 ... General subroutine, 600 ... ROM, 610 ... RAM, 64
0,642 ... Table of addresses, 650 ... General subroutine.

Claims (1)

[Claims] 1. A ROM area including a program instruction stored as data, a plurality of storage locations configured as a plurality of groups, and data including addresses of respective start locations of the group, and a RAM area. Control means coupled to the ROM area and the RAM area, wherein the program command stored as data is
By reading from the ROM area and storing the program instruction in the RAM area, reading the address from the ROM area, and storing each start address of the group,
Remote control comprising: a controller that modifies the data stored in the RAM area to form an executable instruction and executes the instruction in the RAM area to access the storage location of the group. An addressing device that addresses the memory used in the unit.