JPH08242291A - Line testing device for frame relay - Google Patents

Abstract

PURPOSE: To prevent all frame relay logic channels from being disconnected even during the line testing. CONSTITUTION: A frame generation circuit 1 for test sends a test frame with the self-station identification number through a frame relay(FR) logic channel to the other station and stores it in a buffer memory circuit 2, then starts the time measurement of a timer circuit 3. On the other hand, a test frame extracting circuit 4 extracts the test frame with the self-station identification number from the frames sent from the other station through the FR logic channel, then passes it to a comparison circuit 5. The circuit 5 compares the accepted test frame with the test frame of the circuit 2. When the circuit 5 detects they are matched, the timer circuit 3 judges whether or not the measured time by the detection corresponds to the prescribed timer value, then discriminates that the line used in the test is normal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a frame relay (hereinafter,
(Hereinafter abbreviated as FR) to a line test device for performing a line turn-back test.

[0002]

2. Description of the Related Art Conventionally, a line test apparatus of this type sends a line loopback signal using a control channel of a physical layer, and an opposite exchange or a terminal which receives the line loopback line at the physical layer. After confirming that the transmitted carrier signal returns back, the line test device transmits a line return cancellation signal using the control channel of the physical layer. The opposite exchange or the terminal, which has received the transmitted cancellation signal, is performing the line test by canceling the loopback at the physical layer. This is described in the following document, for example.

Transport Systems Generic Requirements
TR-NWT-000499 Issue 4, November 1991 Page 10-28,10
-29.

[0004]

The above-mentioned conventional line test apparatus sends a line return signal using the control channel of the physical layer, and the opposite exchange or terminal that receives the line returns the line at the physical layer. After confirming that the transmitted carrier signal returns back, the line test device sends out a line return release signal using the control channel of the physical layer. The opposite exchange or terminal receiving the transmitted release signal was performing the line test by releasing the loopback at the physical layer, so all the FR logical channels are temporarily disconnected during the line test. There was a problem.

In view of the above problems, it is an object of the present invention to provide a line test apparatus in which all the FR logical channels are not disconnected even during a line test.

[0006]

In the FR line test apparatus of the present invention, an FR test frame to which a local station identification number is added is used.
A test frame generation circuit for transmitting to another station via a logical channel, a buffer memory circuit for accumulating the test frame transmitted by the test frame generating circuit, and a signal from another station via an FR logical channel. The test frame is extracted from the received frame, and if the extracted test frame has the other station identification number, the extracted test frame is returned to the corresponding other station as it is via the FR logical channel. When the test frame extraction circuit and the test frame extraction circuit extract a test frame to which another station identification number is not assigned, the test frame is received and the test stored in the buffer memory circuit is received. The test frame generation circuit and the comparison circuit for comparing the test frame with the test frame to determine whether they match. When the comparison circuit detects a match, the time measured before the match is detected is checked whether or not the timer corresponds to a predetermined timer value. And a timer circuit for judging.

[0007]

The test frame generation circuit transmits the test frame with its own station identification number to another station via the FR logical channel, stores the test frame in the buffer memory circuit, and stores the time in the timer circuit. Start the measurement. On the other hand, the test frame extraction circuit extracts a test frame to which the own station identification number is added, from the frames sent from another station via the FR logical channel. The comparison circuit compares the extracted test frame with the test frame stored in the buffer memory circuit to determine whether they match. When the comparison circuit detects a match,
The timer circuit determines whether or not the time measured until a match is detected corresponds to a predetermined timer value, and if so, it is determined that the line used for the test is normal.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a line relay line testing apparatus of the present invention. The test frame generation circuit 1 is a frame relay (hereinafter referred to as FR).
For testing the line, a test frame of a specific pattern, to which the identification number of the FR exchange of the own station (hereinafter referred to as the own FR exchange identification number) is given, is stored in the buffer memory circuit 2 and the other FR which is a communication partner The test frame transmission signal is transmitted to the timer circuit 3 while being transmitted to the exchange or the terminal. The timer circuit 3, which has received the test frame transmission signal, starts the timer.

On the other hand, the test frame extraction circuit 4 is
When the test frame folded back from the R exchange or terminal is extracted and the identification number of the other FR exchange or terminal is added to the extracted test frame, the test frame is directly sent to the other FR exchange or terminal. Send it back. Further, the frame extraction circuit 4 outputs the extracted test frame to the comparison circuit 5 if the extracted test frame is assigned with its own FR exchange identification number. Further, if the input frame is a frame for general FR, the frame extraction circuit 4 outputs it to a normal route. Upon receiving the test frame to which the own FR exchange identification number is assigned, the comparison circuit 5 compares the transmitted test frame accumulated in the buffer memory circuit 2 with the test frame extracted by the frame extraction circuit 4. To do. If the comparison by the comparison circuit 5 does not match, it is determined that there is an abnormality in the line used for the test, and if the comparison matches, the timer circuit 3 detects the match, At the time of transmitting the test frame to which the own FR exchange identification number is added, it is determined whether or not the activated timer value exceeds the preset timer threshold value. If the timer threshold value is exceeded, the timer circuit 3 determines that the line used for the test is abnormal, and if the timer threshold value is not exceeded, the line used for the test is normal. .

[0010]

As described above, according to the present invention, the test frame generation circuit transmits the test frame to which the own station identification number is added to another station via the FR logical channel, and the test frame is generated. Is stored in the buffer memory circuit, and the timer circuit starts the time measurement. On the other hand, the test frame extraction circuit extracts the test frame to which the own station identification number is added from the frames sent from another station via the FR logical channel. The comparison circuit compares the extracted test frame with the test frames stored in the buffer memory circuit to determine whether they match. When the comparison circuit detects a match, the timer circuit
It is determined whether or not the time measured until a match is detected corresponds to a predetermined timer value, and if so, it is determined that the line used for the test is normal. As a result, all the FR logical channels are temporarily disconnected, and the line loopback test is performed in the FR layer.
This has the effect that it can be performed in logical channel units.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame relay (FR) line test apparatus of the present invention.

[Explanation of symbols]

 1 test frame generation circuit 2 buffer memory circuit 3 timer circuit 4 test frame extraction circuit 5 comparison circuit

Claims (3)

[Claims] 1. A test frame generation circuit for transmitting a test frame with its own station identification number to another station via a frame relay logical channel, and a test frame transmitted by the test frame generation circuit. A test frame is extracted from the buffer memory circuit that stores it and the frame sent from another station via the frame relay logical channel.If the extracted test frame has an identification number of another station, it is extracted. When the extracted test frame is returned to the corresponding other station via the frame relay logical channel as it is, and the test frame extraction circuit extracts the test frame to which the other station identification number is not assigned Receives the test frame and compares it with the test frames stored in the buffer memory circuit. If a comparison circuit that determines whether or not they match, when the test frame generation circuit transmits the test frame to another station, time measurement is started, and if the comparison circuit detects a match, , A timer circuit that determines whether or not the time measured until a match is detected corresponds to a predetermined timer value. 2. The comparison circuit, when the compared test frames do not match, determines that the line used for the test is abnormal, and the timer circuit preliminarily sets the measured time. If the threshold is not exceeded,
If it is determined that the line used in the test as corresponding to the timer value was normal, and if the measured time exceeds the threshold value, the line used in the test as not corresponding to the timer value 2. The frame relay line test device according to claim 1, wherein it is determined that there is an abnormality. 3. The frame relay line test apparatus according to claim 1, wherein the own station is a frame relay exchange, and the other station is another frame relay exchange or a terminal.