JPH08242260A - Frequency offset cancel circuit - Google Patents

Abstract

PURPOSE: To prevent the error propagation to the frequency offset cancel accompanied by a discrimination error for the system equivalently performing the frequency offset cancel by the correction of phase shift quantity for a phase detection output. CONSTITUTION: A frequency conversion is performed for a reception signal by a mixer 2 by using the local signal of a local oscillator 3. The reception signal after the frequency conversion is detected 14. A>=θ detection 7 is enforced by using the θO stored as a phase detection output 9 and matching data 8 by the reception timing corresponding to the matching data 8. By determining Δγplural numbers of times and averaging Δθ, Δθ correction value is determined 9 and is stored 10. By adding the established Δθ correction value to the phase detection output 11, subsequently, a Δθ cancel or a frequency offset cancel is executed. A discrimination/decoding 5 is performed for the phase detection output after the correction, data is reproduced and data is outputted to an output terminal 6. Thus, frequency offset cancel capacity is improved. The integration by a digitizing and the miniaturization of a device can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset cancel circuit used in a radio receiver, more specifically,
The present invention relates to a configuration of an offset canceling unit of a wireless receiver that performs frequency conversion of angle-modulated digital data according to a deviation between a carrier frequency inside a receiver and a received frequency to identify and decode the data.

[0002]

2. Description of the Related Art In a radio receiver for selecting and receiving an angle modulated signal in a frequency band to be received from a plurality of carriers,
Usually, frequency conversion and frequency band limitation are performed multiple times. As shown in FIG. 2, this type of wireless receiver inputs a received signal from an input terminal 1 and uses a local signal of a local oscillator 3 to perform frequency conversion by a mixer 2. After the frequency-converted signal is detected by the phase detector 4, the discriminator / decoder 5 reproduces the data and outputs it to the output terminal 6. With respect to the received signal of the center frequency f1, the signal of the local frequency f0 having the relation of the expression (1) is input to the mixer 2 and frequency-converted into the signal of the frequency f2.

[0003]

[Equation 1]

In reality, a deviation (fixed or temporal) occurs in the reception frequency f1 and the local frequency f0.

Due to this deviation, the frequency f2 'of the received signal after frequency conversion is given by the equation (2) in which the frequency offset Δf is added to the frequency f2.

[0006]

[Equation 2]

Although depending on the detection and identification method, the frequency offset Δf affects the reception performance, and in the extreme case, reception becomes impossible. Therefore, a frequency offset cancel circuit excluding the frequency offset Δf is used. Many frequency offset cancel circuits have already been adopted.

A configuration example of a conventional receiver having an offset cancel circuit in a radio system using a four-phase phase shift keying (hereinafter referred to as QPSK) system is shown in FIG. 3, and a constellation at a discrimination point of phase detection output. Is shown in FIG. A phase shift Δθ corresponding to the frequency offset Δf is added to the originally intended phase detection output θ0, and the phase detection output θ (t) shown in Expression (3) is obtained.

[0009]

(Equation 3)

If θ0 can be correctly identified, Δθ can be obtained by subtracting the identification result from the detection output. In FIG.
The Δθ detection 7 is performed by obtaining the difference between the detection output and the closest identification point that should originally exist. After obtaining Δθ a plurality of times in order to suppress the fluctuation component due to noise or the like, the correction value determination unit 9 outputs Δθ.
Calculate the correction value. There is a radio receiver in which the frequency control unit 12 eliminates the frequency offset of the local oscillator 3 by obtaining Δf corresponding to the obtained Δθ correction value.

FIG. 5 shows a structural example of a conventional receiver having another offset cancel circuit. This receiver corrects the phase Δθ associated with the frequency offset Δf of the detection output. Similar to the method of FIG. 3, Δθ detection, averaging, and Δθ correction value determination are performed, and the Δθ correction value is stored in the storage means 1.
0 is stored, and the Δθ correction value is added to the detection output by the adder 11, and then the identification / decoding unit 5 reproduces the data. Since this receiver uses the detection output, it has a relatively low signal frequency, and can be implemented by digital signal processing by converting the frequency-converted received signal into a digital signal. Therefore, it can be incorporated in the detector, which is effective for downsizing the device. As a document describing this kind of technology,
There are published patent publications and Japanese Patent Laid-Open No. 5-191465.

An actual receiver contains a noise component.
Equation (4) shows the phase of the detection output to which the noise N is added.

[0013]

[Equation 4]

As is apparent from the equation (4), when the instantaneous output is used, a phase error due to the noise N occurs. Noise N (t)
If is a normal distribution, the average value is 0, and an accurate phase shift Δθ can be obtained by averaging a plurality of detection outputs.

[0015]

In the above description of the conventional radio receiver, it is assumed that θ0 can be correctly identified. Therefore, in the radio receiver shown in FIG.
f can correct the phase shift Δθ in the wireless receiver shown in FIG. However, when the noise N (t) becomes large, θ0 cannot always be accurately identified. The correction of the phase shift Δθ when the identification error in the detection output of the equation (4), that is, θ0 is erroneous will be examined below. Focusing on the first quadrant in FIG. 4, the phase shift Δ when the noise N having a normal distribution is added
The probability distribution of θ is shown in FIG. FIG. 6A shows the case where there is no frequency offset Δf, and there is a spread due to noise N centering around Δθ = 0. FIG. 6B shows the frequency offset Δf.
And has a spread due to the noise N around the stationary phase shift Δθ0 accompanying the frequency offset Δf. Here, it is assumed that there is no deviation in the distribution of the frequency offset Δf or the identification timing. Further, the spread due to the noise N is determined by the signal-to-noise ratio (hereinafter, referred to as C / N) of the reception signal before detection assuming that the influence of noise generated in the detection circuit is small.

The probability density function of Δθ shown in FIG. 6A is expressed by equation (5).

[0017]

(Equation 5)

Here, σ represents the standard deviation of Δθ due to the noise N. Further, the probability density function of Δθ shown in FIG. 6B is represented by the equation (6).

[0019]

(Equation 6)

Here, μ represents the average value of Δθ and corresponds to the phase shift Δθ0 corresponding to the frequency offset Δf.

Δθ is measured n times and the average thereof is obtained. If there is no identification error, the following equation is derived from equations (5) and (6).

[0022]

(Equation 7)

Here, σn is the standard deviation after averaging n times, and is given by equation (8).

[0024]

(Equation 8)

Further, μn is the average value of Δθ after averaging n times, and μn = 0 in the case of FIG. 6a and μn = in the case of FIG. 6b.
Δθ0. The average value μn can be obtained more accurately by increasing the number of samples n from the equations (7) and (8).

If there is no identification error, the phase shift Δθ0 corresponding to the frequency offset Δf can be obtained with the probability P shown above. However, in FIG. 4, when the quadrant is moved to another quadrant due to noise or Δθ when it should be in the first quadrant, the discrimination point of the quadrant present at the time of discrimination is erroneously determined. If the identification point is wrong, Δθ will be obtained with reference to it. In other words, the detection output in FIG.
If θ | exceeds π / 4, it corresponds to a region other than the quadrant and an identification error occurs. In this case, the measured value of Δθ is folded back and overlapped with a period of −π / 4 to π / 4. 7A and 7B show distributions of the measured values of Δθ in consideration of the identification error in the adjacent quadrants. FIG. 7A shows the case where there is no frequency offset Δf. It is symmetrical about Δθ = 0, and the average value μn = 0
Becomes

On the other hand, when there is the frequency offset Δf shown in FIG. 7B, the shape does not become symmetrical about Δθ = Δθ0. The average value μc of Δθ measurement in this case is given by the equation (9).

[0028]

[Equation 9]

Here, the integration interval is -π / 4 to π / 4, and μ0 = Δθ0.

Further, Φ (x) is an error function and is expressed by the equation (1
0).

[0031]

[Equation 10]

From equation (9), if there is an identification error, Δ
Since θ0 cannot be accurately obtained, the error in the second term on the right side always occurs.

After Δθ is measured n times, the Δθ is averaged to determine the Δθ correction value, and the Δθ after the Δθ cancellation shown in FIG. 5 is executed.
The probability density function of is calculated as follows.

[0034]

[Equation 11]

Here, σc is expressed by the following equation. In order to perform Δθ cancellation using a noisy measurement value, the standard deviation increases depending on the averaging parameter n.

[0036]

(Equation 12)

When the identification error rate after Δθ cancellation (that is, the symbol error rate: SER) is obtained using the equation (11), the following equation is obtained.

[0038]

(Equation 13)

Here,

[0040]

[Equation 14]

Σs is the standard deviation when Δθ is standardized by π / 4 with respect to the standard deviation σ of Δθ determined from C / N.

SER and bit error rate (BE) when a QPSK modulation signal including noise N is demodulated by differential detection
It is known that the relationship between R) and noise N is as follows.

[0043]

(Equation 15)

Here, σN represents the standardized standard deviation of the noise N. In QPSK, C / N and BE
It is known that the relation of R is the following formula when the differential detection is performed.

[0045]

[Equation 16]

Consider the BER when the differential detection output has a phase shift Δθ due to the frequency offset Δf.
FIG. 8 shows an example of the result of obtaining the BER after performing the Δθ cancellation of FIG. 5 with respect to the frequency offset Δf, using the average number of Δθ measurements as a parameter. The BER when there is no frequency offset is set, and the phase deviation corresponding to the noise N at that time is obtained from the equation (15) and set as the initial state. BER = 10E-2 when there is no frequency offset,
The conditions for 10E-3 and 10E-4 were obtained. Next, a frequency offset is given, and the BER at that time is obtained and shown by the broken line. Next, the BER after the Δθ cancellation was performed with the number of Δθ measurements n = 4 and ∞, and shown by the solid line.

From the equation (13) and the calculation example of FIG.
Σs of the phase deviation due to is large (that is, C /
It can be seen that the frequency offset cancellation capability decreases as N decreases. In other words, if the BER is high (that is, σs is large), the error between the Δθ measurement value and the Δθ correction value due to this becomes large from the equation (9), and as a result, it is impossible to perform sufficient frequency offset cancellation. . Further, from the equation (14) and the calculation example of FIG. 8, it can be seen that steady BER deterioration occurs in accordance with the Δθ measurement average number n as the error increases due to the frequency offset cancellation. It should be noted that even in the method shown in FIG. 3, it can be easily predicted that a similar phenomenon will occur because the Δf detection error associated with the identification error is fed back.

Therefore, a main object of the present invention is to realize a frequency offset cancel circuit for preventing the error transmission to the frequency offset cancel due to the above-mentioned identification error and performing the frequency offset cancel correctly.

Another object of the present invention is to achieve the above object and, at the same time, enable the offset canceling process after frequency conversion of the radio receiver to be carried out by the digital signal processing circuit.

[0050]

In order to achieve the above object, the offset cancel circuit of the present invention adopts a method for correcting the phase of the detection output as shown in FIG.
The detection unit is configured to perform on the definite data in the digital data. The defined data in the digital data include known data and data that may have an identification error, and data that has been identified correctly after the identification error has been detected and data having an identification error has been removed.

As the known data, a training signal added to transmission digital data for offset cancellation, and a plurality of frames in the case of transmitting a plurality of frames in a time division manner such as a time division multiple access (TDMA) system There is a case where a preamble signal for timing extraction or a part of a unique word for frame synchronization arranged at the head part is used.

[0052]

As an example of the case of using the data whose identification points are known, consider the case where the original identification point is in the first quadrant in FIG.
Since it is known in advance that the original identification point should be in the first quadrant even if it is in another quadrant due to noise or frequency offset, the correct phase shift amount Δθ can be obtained. Using FIG. 6, even if | Δθ |> π / 4, Δθ
Can be detected. As a result, the error component of the second term on the right side of Expression (9) can be eliminated, and correct Δθ can be detected. When the Δθ detection error disappears, Δθ0 is obtained by measuring Δθ n times and averaging. The Δθ probability distribution of the detection signal after Δθ correction (or Δf correction) is a normal distribution centered on Δθ = 0 and is represented by the following equation.

[0053]

[Equation 17]

Here, σc is the same as that expressed by the above equation (12).

When the discrimination error rate after Δθ cancellation (that is, the symbol error rate: SER) is calculated using the equation (17), the following equation is obtained.

[0056]

(Equation 18)

Here, σsc is the same as that expressed by the above equation (14).

Equation (18) does not include the phase shift Δθ associated with the frequency offset Δf. From this, it can be seen that by avoiding the identification error, it becomes independent of the value of Δf. It is obvious that there is a condition of | Δθ | <π. It can be seen from the equation (14) that the SER after the frequency offset cancellation depends on the number of measurements n of Δθ. At the same time, it is also apparent from the equation (14) that if the number of times of measurement n is extremely increased, it coincides with the SER when there is no frequency offset Δf. FIG. 9 shows a calculation example of the relationship between the Δθ measurement number n and the BER after canceling the frequency offset.

Even if there is an identification error, Δθ is detected, and only data obtained when there is no identification error during a plurality of Δθ measurements are used. That is, when the identification error is detected later, the Δθ measurement value for the data is discarded, and the Δθ measurement value is used only when the identification is correctly performed, the identification point is not known by adding the identification error detection means. Can be dealt with. The identification error detection means will be described in the embodiment, and the Δθ detection capability will be described here. Excluding the Δθ measurement value when an identification error occurs corresponds to using only the data that satisfies | Δθ | <π / 4 in FIG. As a result, the return of Δθ detection due to the identification error shown in FIG. 7 is eliminated. However, since the section average of −π / 4 to π / 4 is obtained, the average value of Δθ detection has a slight error from Δθ0, unlike the case where known data is used.
However, more accurate Δθ detection can be performed as compared with the conventional method shown in FIG.

[0060]

【Example】

<Embodiment 1> FIG. 1 is a functional block diagram of an embodiment of a radio receiver using a frequency offset cancel circuit according to the present invention. The received signal input to the input terminal 1 is angle-modulated digital data. The received signal is frequency-converted by the mixer 2 using the local signal of the local oscillator 3.
The received signal after frequency conversion is detected by the detector 4. Although the frequency offset cancellation is executed by adding the Δθ correction value by the adder (correction unit) 11, the Δθ correction value storage means 10 is initialized in the initial state. Phase detection output θ at the reception timing corresponding to the collation data in the storage means 8.
Then, the phase difference Δθ is detected by the detector 7 using θ0 stored as the collation data. The averaging / correction value determination unit 9 obtains Δθ a plurality of times and averages it to determine a Δθ correction value.
0 is recorded as a Δθ correction value. Δθ in the phase correction unit 11
By adding the correction value to the phase detection output, Δθ cancellation, that is, frequency offset cancellation is executed thereafter.

The identification / decoding section 5 identifies and decodes the phase-detected output after phase correction to reproduce digital data and outputs the digital data to the output terminal 6. The control unit 18 controls each of the above functional units, and performs writing and reading of the storage means 8 and 10, timing setting of the arithmetic units 7 and 9, and instruction of arithmetic operations. The detected output is A / D converted and configured by a digital circuit. Further, the detection period 7, the correction value determination unit 9, and the control unit 18 may be configured by a general-purpose signal processing circuit such as a microprocessor. The details of the Δθ cancel operation are as described above and have the characteristics shown in FIG.

The operation of the embodiment will be described below by taking a specific data format of digital data as an example. FIG.
0 indicates a data format using a training signal as a signal whose identification point is known. In the figure, PR is a preamble signal for timing extraction (hereinafter abbreviated as PR), UW is a unique word for frame synchronization (hereinafter U).
W is abbreviated), TS is a training signal (hereinafter abbreviated as TS), and Data is communication data. For example, T
When the DMA (time division multiple access) method is used, a plurality of frames having PR and UW at the head are transmitted in time division. The TS is prepared in advance and stored in both the transmitting and receiving radios.
In the above embodiment, the phase detection output corresponding to the TS is used as reference data to correct Δθ, and then the communication data Data is received.

FIG. 10A shows an example in which a TS is inserted in each frame of the TDMA system to cancel the frequency offset in each frame, that is, the phase difference Δθ is corrected.
The flowchart is shown in. When the head of each frame is received, the storage means 10 is initialized (11-1), and the collation data and the phase detection output are compared at the TS reception timing to compare the phase difference Δ.
θ is detected (11-2). After averaging the detected phase difference Δθ (11-3), the Δθ correction value is determined (1
1-4), Δθ is corrected at the time of Data reception (1
1-6). Therefore, at the time of receiving the data, the signal with the frequency offset canceled is added to the identification / decoding unit 5. Here, the TS insertion position may be placed in front of the PR or UW, but it must be taken into consideration that the correct position of the TS cannot be detected unless synchronization is established. For example, the synchronization condition in the previous frame is stored and the position of the TS in the frame is predicted.

FIG. 10B shows a method in which the initialization timing is changed and the Δθ correction value obtained last time is held until just before the TS is received. As a result, frequency offset cancellation can be performed for PR and UW, which is effective when the reception cycle is relatively short and the variation in frequency offset amount between frames is small. In FIGS. 10A and 10B, T
Since S is required for all frames, there is a drawback in that the execution transmission efficiency is reduced due to the overhead due to this. In order to improve the decrease of the effective transmission efficiency, FIG.
As described above, the TS is inserted every plural frames. Figure 10
(D) shows Δθ detected by performing Δθ detection over a plurality of frames.
This is an example of finely adjusting the correction value.

<Embodiment 2> FIG. 12 and FIG. 13 are a functional block diagram of a second embodiment of a radio receiver employing a frequency offset cancel circuit according to the present invention and a flow chart showing its operation, respectively. In the figure, the same functional parts as those in the embodiment of FIG. The control unit 18 is also omitted (the same applies to the following embodiments). In this embodiment, as shown in FIG. 10D, Δθ detection is performed over a plurality of frames to finely adjust the Δθ correction value.

Initialization is performed at the start of the frequency offset cancel operation (13-2), and the contents of the Δθ correction value storage means 10 are cleared. Similar to the embodiment described with reference to FIG. 10A, the Δθ detection unit (13-4), the averaging (13-5) and the Δθ correction value determination (13-6) are performed at the time of TS reception. In the first frame, the Δθ correction value in the storage means 10 has been cleared (13-2), so that the addition section 13 does not actually perform addition. The addition result is stored in the storage unit 10 as a Δθ correction value, and Δθ correction, that is, frequency offset cancellation is performed on the Data of the first frame in FIG. 10D (13-9). Unless the frame is initialized again in the next and subsequent frames, the storage device 1 is received when the TS is received.
Δθ correction according to the stored contents of 0 is already performed. Therefore, in the Δθ detection by the Δθ detection unit 7, the difference after the Δθ correction is detected. Using this result, the Δθ correction value determination unit 9 performs averaging, and the Δθ correction value is added to the storage unit 10 by the addition unit 13 to finely adjust the Δθ correction value for each frame (13-
7) is performed. This corresponds to increasing the value of n in equations (12) and (14), that is, the averaging parameter, and more precise frequency offset cancellation is performed.
In the above embodiment, T taking into consideration the time change of the frequency offset amount and the tracking time of the offset cancellation, etc.
It is necessary to determine the insertion period of S, the signal length of TS, and the initialization period.

<Embodiment 3> FIG. 14 is a functional block diagram of a third embodiment of a radio receiver using an offset cancel circuit according to the present invention. In the present embodiment, FIG.
The operation is almost equivalent to that of (b) and (c). Unlike the embodiment shown in FIG. 1, it has a feed-forward type configuration.
In the first frame, the Δθ correction value in the storage means 10 is cleared. After determining the Δθ correction value using TS, the Δθ correction value is stored and the Δθ correction is started. This is repeated from the next frame onward, and the stored content of the Δθ correction value is updated every time the Δθ correction value is determined by the TS. As a result, after the second frame, by holding the Δθ correction value in the previous frame, PR,
Δθ correction can also be performed on UW and TS.

An example of utilizing the existing frame structure without using the TS to prevent the reduction of the effective transmission efficiency due to the frequency offset cancellation will be shown below. FIG. 15 shows a data format of an embodiment using the preamble signal PR. 15A is the frequency offset cancel circuit of FIG. 1, and the embodiment shown in FIG. 15B can be executed by the frequency offset cancel circuit of FIG. 12, respectively. The basic operation is the same as that of the above-described embodiment using TS, and by using PR as the training signal, the additional signal TS for the purpose of frequency offset cancellation becomes unnecessary. Δθ after timing extraction in the first half of PR
The frequency offset cancellation is performed by evaluating and correcting. In a normal system, PR is a fixed data pattern and can be easily used as a training signal. As a condition, it is necessary to have a PR signal length that has a margin to evaluate Δθ after timing extraction. When the PR signal length is relatively short, Δ over a plurality of frames shown in FIG.
This can be dealt with by evaluating and correcting θ. This utilizes the improvement in accuracy by increasing the value of n in Expressions (12) and (14), that is, the averaging parameter, by evaluating Δθ over a plurality of frames as described above.

The operation almost equivalent to that of the embodiment shown in FIG. 15A can be executed by the feedforward type offset cancel circuit of FIG. Initialization is performed only at the start, and when the PR of the next frame is received, Δθ detection is performed and Δθ correction determined in the previous frame is performed.

FIG. 16 shows an example of the data format of the embodiment using UW. UW predetermined by the system
The frame synchronization is performed based on the timing when all the data are matched with each other. Note that there are cases where a plurality of bit errors are allowed in the UW, and it depends on the system specifications.

<Fourth Embodiment> FIGS. 17 and 18 are a functional block diagram of a fourth embodiment of a radio receiver using a frequency offset cancel circuit according to the present invention and a flowchart showing its operation, respectively. This embodiment uses the data format shown in FIG. Initialization (18-1)
Thereafter, a margin is given to the timing when the UW is expected to be received, and the phase detection output is stored in the storage unit 14 over a plurality of symbols (18-2). At this time point, Δθ has not been corrected. Frame synchronization is established when the UW is captured. The UW start point in the stored phase detection output is found by establishing frame synchronization (18-
3). Therefore, the phase detection output and U stored in the storage unit 14
From the identification points corresponding to all or part of W, the detection unit 7 detects Δθ over a plurality of symbols (18-4), and corrects averaging (18-5) and Δθ correction value determination (18-6). The value determining unit 9 performs this. This is stored in the storage means 10 (18-
8), the correction unit 11 performs Δθ correction (18-9), that is, frequency offset cancellation, on the received signal after the UW of the slot. Note that communication data is often received immediately after UW, and it is realistic to use part of UW in consideration of the processing time required to determine the Δθ correction value.
FIG. 16A shows a method of performing the above processing for each frame, and FIG. 16B shows a method of repeating fine adjustment over a plurality of frames. In the case of FIG. 16B, the steps of determining whether to update in each frame (18-10), determining whether to initialize (18-11), and fine adjustment by the adder 13 (18-7). Is added. In any case, when the UW signal cannot be confirmed and the frame synchronization cannot be established, it is necessary to cancel Δθ detection (18-4).

<Embodiment 5> FIG. 19 shows a fifth embodiment of the radio receiver using the frequency offset cancel circuit according to the present invention.
The functional block diagram of the Example of FIG. In the present embodiment, in a system with a fixed frame structure, the position of the UW of the next frame can be estimated once frame synchronization is established, the UW reception timing of the next frame is predicted after the frame synchronization, and Δθ detection is performed at the predicted timing. Then, the average value and the Δθ correction value are determined. If used as it is, it is obvious that the calculated Δθ correction value is meaningless when the position of the received data and the position of the collation data are misaligned if the predicted timing is incorrect. When the frame synchronization can be maintained in the frame, it is confirmed whether or not the UW is received at the expected timing, and the determination unit 15 for determining whether or not the obtained Δθ correction value can be used is a Δθ correction value determination unit 9 Provide on the output side of. Then, Δθ correction and fine adjustment are executed only when the UW is received at the predicted timing.

<Embodiment 6> FIG. 20 shows a sixth radio receiver using the frequency offset cancel circuit according to the present invention.
The functional block diagram of the Example of FIG. This embodiment is another embodiment using the UW, and controls the selector 16 to perform the same operation as the circuit of FIG. 17 before the frame synchronization and the same operation as the circuit of FIG. 19 after the frame synchronization.

<Embodiment 7> FIG. 21 shows a seventh embodiment of a radio receiver using the frequency offset cancel circuit according to the present invention.
The functional block diagram of the Example of FIG. In this embodiment, the phase detection output using UW is temporarily stored, and the Δθ correction value is updated for each frame in the feedforward type configuration.
In addition, PR and UW frequency offset cancellation can be executed. The Δθ correction value detected in the previous frame is held until immediately before the determination of the Δθ correction value in the frame.

<Embodiment 8> FIG. 22 shows the eighth embodiment of the radio receiver using the frequency offset cancel circuit according to the present invention.
The functional block diagram of the Example of FIG. The present embodiment is another embodiment for predicting the UW reception timing using UW, in which a Δθ correction value is updated for each frame in a feedforward type configuration, and PR and UW frequency offset cancellation is performed. The Δθ correction value detected in the previous frame is held until immediately before the determination of the Δθ correction value in the frame. 21, 2
2. In both of the embodiments, initialization is basically performed at the start of frequency offset cancellation.

<Embodiment 9> FIGS. 23, 24 and 25 are a functional block diagram of a ninth embodiment of a radio receiver using a frequency offset cancel circuit according to the present invention, a data format diagram used therefor, and The flowchart figure is shown. In this embodiment, an identification error of communication data Data is detected to determine whether or not Δθ correction is performed, and frequency offset cancellation is performed. In the data format diagram of FIG. 24, an error detection code (ED) is added to the communication data Data. Dat in frame
If a is correct, it is confirmed by ED. In FIG. 23, the determination unit 15 is provided on the output side of the Δθ correction value determination unit 9, and the output of the Δθ correction value determination unit 9 using Data is selected only when there is no reception error, that is, when there is no identification error. That is, it is determined 15 whether to use the calculated Δθ correction value depending on whether or not there is a Data error in the frame. The above P
Dat in frame compared to using R or UW
Since the data amount of a is generally large, it is possible to perform evaluation on many samples in a short time, and as shown in FIG. 9, it is possible to shorten the convergence time regarding the Δθ correction value by a large number of data.

<Embodiment 10> FIG. 26 shows a functional block diagram of a tenth embodiment of a radio receiver using a frequency offset cancel circuit according to the present invention. This embodiment is also Da
It uses ta and is configured as a feedforward type. This embodiment is shown in FIG. 21 when there is no identification error.
In this circuit, the Δθ correction value is updated instead of being finely adjusted. When an identification error occurs in the frame, the Δθ correction value of the previous frame is held and stored as it is.

An embodiment obtained by combining the embodiments described above will be described below. From the viewpoint of effective transmission rate, it is desirable to reduce additional signals such as PR, UW, and TS. In an actual system, a method is often adopted in which a large amount of additional data is given to the initial synchronization, and in the steady state after the synchronization, the data format is changed to the minimum additional data necessary for maintaining the synchronization. FIG. 27 shows an example of the data format relating to the embodiment when the frame structure changes with time. FIG.
In the data format of, the example in the case of changing the PR signal before and after the synchronization is shown. FIG. 27A shows an example in which PR and UW are used together for frequency offset cancellation. The basic functional block of the receiver that executes this is shown in FIG. 19 or FIG. If the PR is long at the time of timing extraction, the PR is used to obtain a Δθ correction value and the Δθ correction is started. Within the same frame, UW is used to finely adjust the Δθ correction value. As a result, the accuracy of Δθ correction, that is, the frequency offset cancellation can be improved in a short time. When the timing extraction is established, the PR length required to hold the timing is shortened and Data is increased. When this state is entered, fine adjustment of the Δθ correction value is repeated using only UW. The basic functional block diagram of the receiver that executes this is shown in FIG.
It is the same as that of 7, 19, 20. This can be achieved by switching the collation data in the storage means 8 and controlling the determination unit 15 and the selector 16 according to the situation of using PR or UW.

<Embodiment 11> FIG. 28 is a functional block diagram of an eleventh embodiment of a radio receiver using a frequency offset cancel circuit according to the present invention. This embodiment uses the data format using both PR and Data shown in FIG. 27B. In the initial state, the selector 17 is controlled to first use the PR to obtain the Δθ correction value and perform the Δθ correction. In the same frame, Data is used to finely adjust the Δθ correction value. That is, when the timing extraction is established and the steady state is entered, the selector 17 is controlled to repeat the fine adjustment of the Δθ correction value using Data.

<Embodiment 12> FIGS. 29 and 30 are a data format diagram and a functional block diagram of a radio receiver used in a twelfth embodiment of a radio receiver using a frequency offset cancel circuit according to the present invention. Show.
In this embodiment, the frequency offset cancel circuit of the present invention and the feedforward type frequency offset cancel circuit shown in FIG. 5 are used together. It has been described above that when a discrimination error occurs, a steady error occurs in the Δθ correction value in the conventional example. However, it has already been mentioned that the steady-state error is small if the frequency of the identification error is low. By using the embodiments described so far, the identification error relating to the phase detection signal after executing the Δθ correction can be reduced, so that the conventional feedforward method can be applied to the phase detection signal after the Δθ correction. In each of the above-described embodiments, the Δθ correction value obtained from the phase detection signal at the beginning of each frame or the Δθ correction value obtained in the previous frames is used. Therefore, if the amount of frequency offset variation in a frame is large, it may not be possible to follow up. It is possible to cope with the frequency offset variation by performing the fine adjustment of the Δθ correction with a relatively short number of data by using the feedforward method shown as the conventional example during the reception of the data in the frame.

Although the present embodiment of the present invention has been described above, the present invention is not limited to the above embodiment. Further, it is obvious that there may be a plurality of combinations other than those shown individually, and the characteristics of each basic configuration example are as described above, and therefore description thereof will be omitted.

[0082]

According to the present invention, when the phase shift amount of the phase detection output due to the frequency offset is evaluated in consideration of the identification error, the frequency offset canceling ability can be enhanced. In the present invention, frequency offset cancellation is equivalently performed by correcting the amount of phase shift with respect to the phase detection output. Since the signal frequency of the target phase detection output is a relatively low frequency unlike the radio frequency band, it is suitable for integration by digitization and has the effect of downsizing the device.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a first embodiment of a wireless receiver using a frequency offset cancel circuit according to the present invention.

FIG. 2 is a functional block diagram of a conventional wireless receiver.

FIG. 3 is a functional block diagram of a radio receiver having a conventional frequency offset cancel circuit.

FIG. 4 QPSK phase detection output constellation diagram

FIG. 5 is a functional block diagram of a radio receiver having a conventional frequency offset cancel circuit.

FIG. 6 is a probability density distribution diagram of the phase difference Δθ.

FIG. 7: Probability density distribution diagram of Δθ measurement values when an identification error occurs

FIG. 8 is a frequency offset vs. BER characteristic diagram for explaining the problems of the prior art.

FIG. 9 is a Δθ measurement number vs. BER characteristic diagram according to the present invention.

FIG. 10 is a data format diagram using a training signal (TS) used in an embodiment of the frequency offset cancel circuit of the present invention.

FIG. 11 is a flowchart showing the operation of the first embodiment of the wireless receiver having the frequency offset cancel circuit according to the present invention.

FIG. 12 is a functional block diagram of a second embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 13 is a flowchart showing the operation of the second embodiment of the wireless receiver having the frequency offset cancel circuit according to the present invention.

FIG. 14 is a functional block diagram of a third embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 15 is a data format diagram using a preamble (PR) used in an embodiment having a frequency offset cancel circuit of the present invention.

FIG. 16 is a data format diagram of an embodiment having a frequency offset cancel circuit using a unique word (UW).

FIG. 17 is a functional block diagram of a wireless receiver having a frequency offset cancel circuit according to a fourth embodiment of the present invention.

FIG. 18 is a flowchart showing the operation of the fourth embodiment of the wireless receiver having the frequency offset cancel circuit according to the present invention.

FIG. 19 is a functional block diagram of a fifth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 20 is a functional block diagram of a sixth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 21 is a functional block diagram of a seventh embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 22 is a functional block diagram of an eighth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 23 is a functional block diagram of a wireless receiver having a frequency offset cancel circuit according to a ninth embodiment of the present invention.

FIG. 24 is a data format diagram used in a ninth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 25 is a flowchart of a ninth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 26 is a functional block diagram of a tenth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 27 is a data format relating to an embodiment in which the frame structure changes with time.

FIG. 28 is a functional block diagram of an eleventh embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

FIG. 29 is a data format diagram used in a twelfth embodiment of a radio receiver having a frequency offset cancel circuit according to the present invention.

FIG. 30 is a functional block diagram of a twelfth embodiment of a wireless receiver having a frequency offset cancel circuit according to the present invention.

[Explanation of symbols]

 1: Input Terminal 2: Mixer 3: Local Oscillator 4: Phase Detector 5: Identification / Decoder 6: Output Terminals 7, 7a, 7b: Δθ (Phase Shift Amount) Detector 8: Collation Data Storage Means 9, 9a, 9b: averaging / Δθ correction value determination unit 10, 10a, 10b: Δθ correction value storage unit 11, 11a, 11b: addition (Δθ correction) unit 12: frequency control unit 13: addition (Δθ correction value fine adjustment) unit 14: θ (phase detection output) storage means 15: determination 16, 17: selector 18: control unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Shinda 2-1-1 Shinmeidai, Hamura-shi, Tokyo Kokusai Electric Co., Ltd. Hamura factory (72) Inventor Yoshinori Nagoya 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Incorporated company Hitachi, Ltd., Information and Communication Division (72) Inventor, Kuniaki Akatsuka, 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Incorporated, Hitachi, Ltd., Information and Communications Division (72) Inventor, Katsunori Hamada 2-10 Toranomon, Minato-ku, Tokyo No. 1 NTT Mobile Communications Network Co., Ltd.

Claims (21)

[Claims] 1. A radio receiver having a detector for phase-detecting a signal obtained by angle-modulating digital data, and an identifier / decoder for identifying the signal excluding the frequency offset of the output of the detector and decoding the digital data. A frequency offset cancel circuit for holding phase information for predetermined specific data in the digital data as reference data in advance, a position of the output of the detector and the reference data. A phase difference detection unit that detects a phase difference, a correction value determination unit that averages the phase difference over a plurality of data to determine a phase correction value, a second storage unit that stores the phase correction value, and the second storage unit. 2. A frequency offset cancel circuit characterized by having a phase correction unit for correcting the phase of the output of the detector using the phase correction value stored in the second storage means. . 2. The frequency offset cancel circuit according to claim 1, wherein the specified specific data in the digital data is a training signal added for offset cancellation. Cancel circuit. 3. The frequency offset cancel circuit according to claim 2, wherein the digital data is a signal obtained by temporally dividing the digital data into a plurality of frames, and the digital data is stored in the second storage means at each head of each received frame. The stored contents are initialized to zero, the phase correction value is determined from the phase detection output corresponding to the training signal, and the phase correction value is stored in the second storage means. A frequency offset cancel circuit, comprising: the second storage means, the correction value determination section, and a control section for driving the phase correction section so as to perform phase correction on the received phase detection output. 4. The frequency offset cancel circuit according to claim 2, wherein the digital data is a signal temporally divided into a plurality of frames, and is stored in the second storage means immediately before a training signal of a received frame. The contents are initialized to zero, the phase correction value is determined from the phase detection output corresponding to the training signal and stored in the second storage means, and the phase correction unit receives the training signal after the training signal in the frame. The stored contents of the second storage means are maintained until the next frame, and the stored contents of the second storage means are initialized to zero immediately before the training signal in the next frame. Up to the second storage means, the correction value determination section, and the top correction section for executing the phase correction section for the received phase detection output. Frequency offset cancellation circuit, characterized in that a control unit for driving the phase correction unit. 5. The frequency offset cancel circuit according to claim 2, wherein the digital data is a signal temporally divided into a plurality of frames, and the contents stored in the second storage means are stored at a preset cycle. Initialized to zero,
The phase correction value is determined from the phase detection output corresponding to the training signal in the frame in which the storage content of the second storage means is initialized to zero, and the phase correction value is stored in the second storage means and stored in the frame. The second storage unit, the correction value determination unit, and the correction value determination unit are configured to perform the phase correction on the received phase detection output until after the storage content of the second storage unit is initialized to zero next after the training signal. A frequency offset cancel circuit comprising a control unit for driving the phase correction unit. 6. The frequency offset cancel circuit according to claim 2, wherein the digital data is a signal temporally divided into a plurality of frames, and the stored content of the second storage means is zero at a preset cycle. The phase correction value is determined from the phase detection output corresponding to the training signal in the frame in which the storage content of the second storage means is initialized to zero and stored in the second storage means. Phase correction is performed on the phase detection output received after the training signal in the frame and the storage content of the second storage means is maintained until the next frame, and the storage content of the second storage means after the next frame. The phase correction value is determined from the phase detection output corresponding to the training signal in the frame for the phase detection output after performing the phase correction by Then, the frequency offset cancel circuit is provided with the control unit for driving the second storage unit, the correction value determination unit, and the phase correction unit so as to finely adjust the stored contents of the second storage unit. . 7. The frequency offset cancel circuit according to claim 1, wherein the determined specific data in the digital data is at least a part of a timing extraction preamble signal. . 8. The frequency offset cancel circuit according to claim 7, wherein the digital data is a signal obtained by temporally dividing a plurality of frames having the preamble signal at a head portion thereof, and each head of the plurality of frames. Section initializes the storage content of the second storage means to zero, determines the phase correction value from the phase detection output corresponding to the preamble signal, stores it in the second storage means, and stores it in the frame. A frequency offset cancel circuit comprising: the second storage means, the correction value determination section, and a control section for driving the phase correction section so as to perform phase correction on the phase detection output received after the preamble signal. . 9. The frequency offset cancel circuit according to claim 7, wherein the digital data is a signal obtained by temporally dividing a plurality of frames having the preamble signal at the head portion, and the digital data is the first frame at a preset cycle. The storage content of the second storage means is initialized to zero, and the phase correction value is determined from the phase detection output corresponding to the preamble signal in the frame in which the storage content of the second storage means is initialized to zero. Phase correction is performed on the received phase detection output after the preamble signal is stored in the frame until the content stored in the second storage means is initialized to zero next time. Second above
And a control unit for driving the correction value determination unit and the phase correction unit. 10. The frequency offset cancel circuit according to claim 7, wherein the digital data is a signal obtained by temporally dividing a plurality of frames having the preamble signal at a head portion thereof, and the digital data is the first frame at a preset cycle. The storage content of the second storage means is initialized to zero, and the phase correction value is determined from the phase detection output corresponding to the preamble signal in the frame in which the storage content of the second storage means is initialized to zero. Phase correction is performed on the phase detection output stored in the second storage means and received after the preamble signal in the frame, and the storage content of the second storage means is maintained until the next frame. The preamble signal in the frame is converted to the phase detection output after performing the phase correction based on the stored contents of the second storage means. A control unit that drives the second storage unit, the correction value determination unit, and the phase correction unit so as to finely adjust the stored contents of the second storage unit by determining the phase correction value from the corresponding phase detection output. A frequency offset cancel circuit provided. 11. A radio receiver having a detector for phase-detecting a signal obtained by angle-modulating digital data, and an identifier / decoder for identifying the signal excluding the frequency offset of the output of the detector and decoding the digital data. A frequency offset cancel circuit, wherein the digital data has a frame synchronization unique word signal, and a phase detection output corresponding to at least a part of the unique word signal is stored as reference data; Third storage means for giving a margin before and after the unique word signal timing, storing the phase detection output obtained from the received signal, and designating a read position in accordance with the unique word signal timing found by establishing frame synchronization by the unique word. , The phase detection output stored in the third storage means and the collation data A phase difference detection unit that detects the phase difference, a correction value determination unit that averages the phase difference over a plurality of data to determine a phase correction value, and a second storage unit that stores the phase correction value, A frequency offset cancel circuit, comprising: a phase correction unit for correcting the phase of the output of the detector using the phase correction value stored in the second storage means. 12. The frequency offset cancel circuit according to claim 11, wherein the content stored in the second storage means is initialized to zero at each head of the received frame, and the phase detection output corresponding to the unique word signal is output. The second storage means and the correction are performed so that the phase correction value is determined and stored in the second storage means, and the phase detection output received after the unique word signal in the frame is corrected. A frequency offset cancel circuit comprising a value determining section and a control section for driving the phase correcting section. 13. A radio receiver having a detector for phase-detecting a signal obtained by angle-modulating digital data, and an identifier / decoder for identifying the signal excluding the frequency offset of the output of the detector and decoding the digital data. Frequency offset cancellation circuit, wherein the digital data is a signal temporally divided into a plurality of frames having a unique word signal for frame synchronization, and the phase detection output corresponding to at least a part of the unique word signal is collated. First storage means for storing as data and a timing at which the unique word signal is received with respect to a frame after frame synchronization is established, and a position of the phase detection output of the frame and the collation data is predicted at the predicted timing. Phase difference detection means for detecting the phase difference, and the phase difference is calculated over a plurality of data and averaged. And a correction value determination unit that determines a phase correction value based on the average value, and determines whether to use the phase correction value depending on whether the unique word signal is received at the timing predicted from the frame synchronization establishment timing in the slot. Determination unit, a second storage unit that stores the correction value according to the determination result of the determination unit, and a phase that executes the phase correction of the phase detection output using the phase correction value of the second storage unit. A frequency offset cancel circuit having a correction unit. 14. The frequency offset cancel circuit according to claim 11 or 13, wherein the stored content of the second storage means is initialized to zero at a preset cycle, and the stored content of the second storage means is set to zero. In the frame after the frame synchronization is established after initialization, the phase correction value is determined and stored in the second storage means, and the phase correction is performed on the phase detection output received after the unique word signal in the frame. And the second storage unit holds the contents stored in the second storage unit until the phase correction value is redetermined in the subsequent frame or the second storage unit is initialized. A frequency offset cancel circuit comprising: a storage unit, a control unit that drives the correction value determination unit, and the phase correction unit. 15. The frequency offset cancel circuit according to claim 14, wherein the correction section performs the phase correction on the phase detection output including the unique word signal in the frame after the storage content of the second storage means is determined. The correction value determination unit executes the phase correction value determination using the unique word signal after the phase correction, and finely adjusts the storage content of the second storage unit according to the phase correction value obtained in the frame. A frequency offset cancel circuit characterized by: 16. A radio receiver having a detector for phase-detecting a signal obtained by angle-modulating digital data, and an identifier / decoder for identifying the signal excluding the frequency offset of the output of the detector and decoding the digital data. A frequency offset cancel circuit of, wherein the digital data is a signal obtained by temporally dividing the data into a plurality of frames, and a signal in which an error detection code is added to the communication data in each frame, and at least a part of the communication data Assuming that the phase detection output corresponding to was correctly received, the phase difference from the normal identification point is detected by the detection unit, and the phase difference is calculated over a plurality of data and averaged. A correction value determination unit that determines the phase correction value based on the value and the above-mentioned complementary when it is confirmed from the error detection result in the relevant slot that there is no identification error. A determination unit that determines the use of the value, a second storage unit that stores the phase correction value according to the determination result by the determination unit, and a phase correction value that is stored in the second storage unit in the next frame. A frequency offset cancel circuit having a phase correction unit for performing phase correction of the output of the above-mentioned detector. 17. The frequency offset cancel circuit according to claim 16, wherein the phase correction for the phase detection output is executed in a frame after the storage content of the second storage means is fixed, and the communication data after the phase correction is executed. Is executed to determine the phase correction value, and the stored content of the second storage means is finely adjusted by the phase correction value obtained in the frame.
A frequency offset cancel circuit, comprising: a control unit that drives the second storage unit, the phase correction unit, and the correction value determination unit so as to determine the phase correction value in the next frame. 18. A radio receiver having a detector for phase-detecting a signal obtained by angle-modulating digital data, and an identifier / decoder for identifying the signal excluding the frequency offset of the output of the detector and decoding the digital data. 9. The frequency offset cancel circuit according to claim 7, wherein the digital data is a signal obtained by temporally dividing the digital data into a plurality of frames, and each frame has a preamble signal for timing extraction and a unique word signal for frame synchronization. A frequency offset cancel circuit comprising the frequency offset cancel circuit according to claim 11 and the frequency offset cancel circuit according to claim 11. 19. The frequency offset cancel circuit according to claim 18, wherein the first collation data using the preamble signal and the second collation data using the unique word signal are stored in the first storage means, Selection means for selecting collation data depending on whether to use the preamble signal or the unique word signal, and means for detecting a phase difference between the phase detection output obtained from the received signal and the first or second collation data. And a correction value determination unit that determines a phase correction value based on the average value by performing averaging over a plurality of data in accordance with the number of matching data by the preamble signal and the unique word signal. Frequency offset cancel circuit. 20. The frequency offset cancel circuit according to claim 2, claim 7, claim 11 or claim 16, assuming that the phase detection output after phase correction can be correctly received. Another detecting means for detecting a phase difference from the point, a second correction value determining section for determining the phase difference over a plurality of data, performing averaging, and determining a phase correction value based on the average value, A fifth storage unit that stores the phase correction value according to the determination result by the second correction value determination unit, and the phase using the phase correction value stored in the fifth storage unit in the frame. A frequency offset cancel circuit, comprising: a second phase correction unit that executes phase correction again on the corrected phase detection output. 21. A detector for phase-detecting a signal obtained by angle-modulating digital data, a frequency offset cancel circuit for correcting the phase of an output of the detector, and a frequency offset canceller. A radio receiver having an identification / decoder for identifying the removed signal and decoding the digital data.