JPH0823855B2 - Bus switching device for multi-processor system - Google Patents

Description

The present invention relates to a bus switching device in a multiprocessor (computer) system.

[Conventional technology]

Conventionally, as described in Japanese Patent Application Laid-Open No. 58-8075, a bus switching device is used when an input / output operation such as data transfer started by an input / output request from a processing device (hereinafter abbreviated as CPU) is completed. Immediately, it was restarting the scan for activation requests from other CPUs. However, recent I / O devices (hereinafter abbreviated as I / O)
Is intelligent, its operation is complicated, and the amount of information to be reported at the time of abnormal termination is enormous.Therefore, in order to shorten the operation time of one time and improve the bus usage efficiency, At the end of the operation, only the presence / absence of an error is reported, and the detailed information is taken in by another input / output operation.

[Problems to be solved by the invention]

The above-mentioned prior art has not considered the case where the detailed information is transferred to the CPU by another input / output operation after the operation is completed. That is, even if it is found that detailed information is required as a result of performing input / output operation with an I / O having one CPU (called CPUA), this CPUA will fetch the detailed information next time. The bus switching device may scan for I / O requests from other CPUs until the I / O requests of other CPUs are issued, resulting in I / O operations from other CPUs (called CPUB). . As a result, there is a problem that the detailed information of the input / output operation by CPUA is overwritten by the result of the input / output operation by CPUB before being transferred to CPUA.

An object of the present invention is to provide a bus switching device suitable for controlling shared I / O in a multiprocessor system.

[Means for solving problems]

The purpose is to connect the common input / output device by sequentially switching the input / output bus connected to each processor when there is no input / output request from any of the plurality of processors and the common input / output device is not busy. When there is an I / O request from any of the processors or the common I / O device is busy, a bus switching unit that prohibits switching of the I / O bus connected to the common I / O device is provided, and it is started by the I / O request. When the input / output operation ends in error, the input / output operation is reported only if there is an error, and the detailed information of the error is transferred after waiting for the next input / output request. Which stores a pattern indicating the above in advance, termination information reported to the connected processor by the common input / output device at the time of termination of the connection, and the memory A one-shot circuit that triggers when an error is detected by checking the contents and a period during which the error is detected and the one-shot circuit is outputting and prohibits switching of the input / output bus This is achieved by providing means for continuously accepting input / output requests.

[Action]

The bus switching unit of the bus switching device keeps the bus connected when other I / O operations are complete when detailed I / O information is available.
I / O request scan processing is not performed. Therefore,
The detailed information is not destroyed by performing I / O and I / O operations from other CPUs. If there is no detailed information, the bus is immediately disconnected and the processing of the I / O request scan of another CPU is started. As a result, the bus occupation time can be shortened so that the I / O requests of other CPUs are not additionally provided.

〔Example〕

A bus switching device according to the present invention will be described below by taking a file system as an example. FIG. 4 shows a system configuration as an example. In this example, as shown in the figure, two processing devices (processors, computers) 101, 102 can access the disk 107 as a file device in a time division manner, that is, a multi-processor. It is an access control system. Specifically, bus switching is performed by the bus switching device 105. Although the computer system in this example is a file system, it is needless to say that it is generally not limited to this.

In this system configuration, the controller 106 controls the operations for writing and reading data on the disk 107. In this controller, when this operation is executed, when an error occurs, the processing device is notified by status information, the detailed information is stored inside, and a command for reading the detailed information (hereinafter referred to as a sense command) is activated. The detailed information is transferred to the processing device. However, when another read / write command is accepted before the sense command is activated, the detailed information of the previous time is erased, and the detailed information of the newly accepted command remains.

Further, the host adapters 103 and 104 are respectively the processing unit 10
1 and 102 are provided correspondingly to transfer command information, data and status information between the processing devices 101 and 102 and the controller 106. Furthermore, the bus switching unit 105 is
One of the host adapters 103 and 104 connected to 08 and 109 is selected and connected to the bus 110.

An embodiment of the present invention will be described below. The present invention is related to the host adapters 103, 104, buses 108, 109 in FIG.
The operation is within the range of 110, the controller 106, and the bus switching device 105, and the operation will be described in the following range.

FIG. 1 shows a block diagram of the bus switching unit 105 of FIG.
The buses 108, 109, and 110 are the same bus interface in this example.

First, the input / output operation in this embodiment will be described with reference to FIG. FIG. 5 shows the input / output operation procedure flow in this embodiment.

The host adapter 103 (or 104) is the processing device 101 (or 1
When the data transfer request from 02) is accepted, the input / output device selection signal (this is a start signal. This signal is hereinafter referred to as SEL) is turned on in step 70. Next, at step 71, an in-operation signal (hereinafter referred to as BSY) which becomes a response signal from the controller 106.
Check) whether or not (standing) is standing. If BSY
If it detects that the SEL is turned off in step 72, the command specified by the input / output operation is sent in step 73, the data is transferred to the controller 106 in step 74, and the status which is the command end information is sent in step 75. To receive. When it ends, the BSY from the controller 106 is detected to be turned off at step 76, and finally the status is checked at step 77, and the input / output operation of this command is ended. If the status check result is normal at step 78, the command processing is terminated. However, when an error occurs, the controller stores the detailed information thereof, so the sense command is executed and read out in accordance with the procedure of steps 79 to 85 as in the previous case. Then, at 86, error processing is performed according to the error information of the data, and a series of operations is ended. The above is the host adapter 10 in this embodiment.
3 and 104 are common operations.

FIG. 1 shows the internal configuration of the bus switching unit 105 which is an embodiment of the present invention. The function of this switching unit component will be described below with reference to FIG. Host adapter 103, 104, controller 106
The connection buses 108, 109, 110 and the bus switching unit 105 are connected by tri-state drivers / receivers 30, 31, 32. Switching of which host adapter bus to connect the bus 110 on the controller 106 side is performed by controlling the enable terminal “E” of the driver / receivers 30 and 31. The output of the decoder 33 is connected to this terminal, and the decoder 33 decodes the count value of the counter 34. Therefore, the bus switching unit performs switching by the count-up of the counter 34 so that the bus 110 is sequentially connected to the buses 108 and 109. If there is no command start from the host adapter, Both are high, and the bus connection is periodically switched by the output signal of the oscillator 36 input to the counter 34 via the AND gate 35.

The start signal SEL10 is turned on from the host adapter 103, and the bus
Once the 108 is connected, the driver / receiver 30 will
Turn on EL1. SEL1 is sent to the controller 106 via the driver / receiver 32 and is also input to the NOR gate 37. It is the output of NOR gate 37 Is connected to the input of the AND gate 35, this signal suppresses the CLK input of the counter 36. As a result, the count up of the counter 34 stops. Therefore controller 10
The bus 110 of 6 remains connected to the bus 108 of the host adapter 103. From the controller 106 that received SEL1,
The response signal BSY2 is turned on via the driver / receiver 32. This signal sends a response to the host adapter 103 via the driver / receiver 30 and is input to the NOR gate 37. Therefore, after this, the host adapter 103 that received the response
Turns off SEL10, and even if SEL1 turns off, until BSY2 turns off,
Ie until the command is finished Does not turn off, the bus continues to be connected. The functions up to this point are known.

Information is exchanged between the host adapter and the controller by placing information on the DATA bus 6 by a handshake which returns a response ACK5 from the host adapter 103 or 104 in response to the transfer request REQ4 from the controller 106.
Also, the information to be transferred is the command to the controller, READ /
The WRIT data and the status from the controller are distinguished by two signals TYPE3.

TYPE3 and DATA bus 6 are connected to the address input of ROM38. ROM38 is a TYP as shown in FIG.
E3 is the status transfer pattern (11) ₂ and DATA bus 6 is the error end status pattern (00000010) ₂ or (001
00010) Only when it becomes ₂ , the "D0" terminal in the data output terminal is burnt out so that it becomes "1". This output enters the D input of flip-flop 40. REQ4 and ACK5 are input to the NAND gate 39, and the output is connected to the one-shot 41 and the flip-flop 40, and the one-shot 41 operates at the falling edge of the output pulse and the flip-flop 40 operates at the rising edge. Q Output of One Shot 41 ▲ ▼ 9
Is connected to the clear input of flip-flop 40. In the one-shot 41, the NAND gate 42 turns on SEL1 from the host adapter 103 or 104, and the controller 106 turns on B
It is cleared when the response of SY2 returns, that is, when a new I / O operation starts. On the other hand, since the controller 106 transfers status, REQ4 is turned ON, and when the host adapter 103 responds with ACK5, ▲ ▼ 9 is turned OFF, clearing of the flip-flop 40 is released, and the error completion status pattern is generated at the timing when the controller 106 turns OFF REQ4. Then flip-flop 40 is set. Output of flip-flop 40, Similarly to AND gate 35, it has the function of stopping the switching of buses. It is also connected to the one-shot 41 so that the one-shot 41 is not retriggered while this signal is being output. That is, the command ends, If there is an error in the status before turning off Since the switch turns on, the bus switching is not restarted. The bus switching is restarted when the same host adapter is restarted and the one-shot 41 and flip-flop 40 are cleared. Is turned off, the command is Is turned off, or a certain period of time determined by the time constant of the one-shot 41 has passed, and the output of the one-shot 41 is ▲ ▼
9 is turned on and the flip-flop 40 is cleared, When is turned off.

A series of operations of input / output commands using the bus switching unit will be described below along the time chart of FIG. 2 by taking a normal operation as an example. First, SEL10 from host adapter 103
When (SELA) is turned ON, the host adapter 103 is turned ON by the bus switching unit 105 via the driver / receiver 30 if connected to the bus 110 on the controller 106 side. SEL1 is output to the controller 106 via the driver / receiver 32, and Is turned on, the bus switching for a fixed period stops, and the host adapter
The bus connection between 103 and controller 106 is maintained. When the response signal BSY2 is returned from the controller 106, the host adapter 103
Turns off SEL10 and starts command operation. First, since the controller 106 receives a command to be executed, it transfers a command of TYPE3 and turns on REQ4. Host adapter 103 is D
Put command information on the ATA bus 6 and turn on ACK5. The controller 106 reads the information and turns off REQ4 to notify that it has been read.
Turn off CK5. By repeating this operation by the amount of information, the content of the command is sent to the controller 106. For example, taking the command to read data from the disk as an example,
The controller 106 changes TYPE3 to data READ, puts the read data on the DATA bus 6 by the handshake of REQ4 and ACK5 as in the above command transfer, and the host adapter 103
Transferred to. The controller 106 repeats the above operation for the number of data items designated by the command information. When all the data transfer is completed and the command operation is normally completed, the controller 106 changes the TYPE3 to the status transfer, and similarly transfers the status on the REQ4, ACK5 and DATA buses 6. At this time, the status pattern ends normally, so ROM38
The data output by is 0, so the flip-flop 40 is not set, Remains off. With this, the controller 106 completes all the processing and BSY2 is turned off. Is turned off and the bus switching is restarted by the output signal of the oscillator 36. When the command activation signal SEL11 from the host adapter 104 is ON during the execution of the command of the host adapter 103, the bus has been disconnected, and therefore the response waiting state shown in FIG. 2 is entered. When the bus switching is restarted and the bus of the host adapter 104 and the controller 106 is connected, SEL1 is immediately received by the controller 106 and the same operation as the host adapter 103 is performed.

Next, an abnormal operation will be described as an example along the time chart of FIG. First, command activation, command transfer, and data transfer are performed between the host adapter 103 and the controller 106 in the same manner as in FIG. 2, and when the controller 106 detects an error, the information is stored, and an error end is performed in the same procedure as in FIG. Status pattern of the host adapter 103
Transferred to. At this time, the data "D0" output from ROM38 becomes "1", ACK5 turns ON, and REQ4 turns OFF, flip-flop 40 is set, Turns on. Therefore, when this command ends, Even if is turned off, the bus does not switch. Therefore, host adapter 1
Even if SEL11 (SELB) is turned ON, 04 is not accepted and the response waiting state continues. Next host adapter A103
When the sense command is activated and SEL1 is turned ON and BSY is turned ON from the controller 106, ▲ ▼ 9 is turned ON and the flip-flop 40 is cleared, Is turned off. But at this time, Since it is ON, the bus does not switch and the sense command
It is executed in the same procedure as the read command from the disk, and detailed error information is sent to the host adapter 103.
After that, when the sense command ends, bus switching resumes,
The SELB 11 in which the host adapter 104 is ON is accepted and the command is executed. If the host adapter 103 for a certain period
If the sense command is not activated, the output of the one-shot 41 is changed depending on the time constant as shown by the dotted line.
▼ 9 is turned on and the flip-flop 40 is cleared, Turns off, and bus switching resumes.

According to this embodiment, even if the input / output operation from the host adapter 103 ends in error, the bus switching unit 105 detects this and the input / output bus remains connected to the host adapter 103. There is an effect that the input / output operation is not performed and the host adapter 103 can surely capture the error detailed information of the input / output operation performed by itself. Also, to keep the bus connected,
Only when there is detailed error information, only when there is an error during the previous I / O operation, and when it ends normally, the start scan of the I / O operation is restarted immediately, so the bus is occupied unnecessarily long. The effect is that you do not have to. Further, since the bus remains connected for a certain period of time, there is an effect that the bus does not remain occupied even if the processing device side has a failure during the bus connection and the next activation does not occur. .

The present invention can be positively used for SCSI (abbreviation of small computer system interface).

〔The invention's effect〕

According to the present invention, after the input / output operation of the I / O is executed by the input / output request of the CPU, the bus is immediately disconnected to enable the input / output operation of the I / O from another CPU if there is no detailed information by the operation. If you have the information, leave the bus connected and
Since I / O is not made to perform I / O operations by the CPU, it has the effect of not waiting for I / O requests from other CPUs more than necessary when there is no detailed information.
There is an effect that detailed information is not destroyed by the input / output operation of U.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a bus switching unit according to an embodiment of the present invention, FIG. 2 is a time chart of a series of normal termination commands using the bus switching unit according to the embodiment, and FIG. 3 is an abnormal termination command. FIG. 4 is a system configuration diagram of an example of a computer system according to the present invention, FIG. 5 is an input / output operation procedure flow chart of one embodiment, and FIG.
FIG. 6D is a diagram showing a data pattern of the status check ROM in the bus switching unit according to the embodiment of the present invention. 105 …… Bus switching section, 38 …… ROM, 39,42 …… NAND gate, 41 …… One-shot, 35 …… AND gate, 40 …… Flip flip.

Claims (1)

[Claims] 1. When there is no input / output request from any of the plurality of processors and the common input / output device is not busy, the input / output bus connected to each processor is sequentially switched to connect to the common input / output device. , A bus switching unit that prohibits switching of the I / O bus connected to the common I / O device when there is an I / O request from any processor or when the common I / O device is in a busy state is started by the I / O request. When an input / output operation is terminated due to an error, the input / output operation is terminated by reporting whether or not there is an error, and detailed information about the error is transferred after waiting for the next input / output request. A memory in which a pattern indicating existence is stored in advance, termination information reported by the common input / output device to the connected processor at the time of termination of the connection, and the memory A one-shot circuit that triggers when an error is detected by checking the contents and a period during which the error is detected and the one-shot circuit is outputting and prohibits switching of the input / output bus A bus switching device for a multiprocessor system, comprising: means for continuously receiving input / output requests.