JPH08236665A - Resin sealed semiconductor device and manufacture thereof - Google Patents
Resin sealed semiconductor device and manufacture thereofInfo
- Publication number
- JPH08236665A JPH08236665A JP3951495A JP3951495A JPH08236665A JP H08236665 A JPH08236665 A JP H08236665A JP 3951495 A JP3951495 A JP 3951495A JP 3951495 A JP3951495 A JP 3951495A JP H08236665 A JPH08236665 A JP H08236665A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- hole
- resin
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、放熱特性を改善した樹
脂封止型半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having improved heat dissipation characteristics and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、樹脂基板の上面側に設けたＩＣチ
ップの接続電極と、下面側に設けた外部接続用のパッド
電極とをスル−ホ−ルを介して接続し、前記パッド電極
には半田パンプを設けると共に前記樹脂基板の上面を樹
脂封止してなる樹脂封止型半導体装置が開発され、これ
らの半導体装置はプラスチック・ボ−ルグリッドアレイ
（以後ＰＢＧＡと略記する）の名称にて商品化されてい
る。然るに、上記ＰＢＧＡは従来のセラミックＢＧＡに
比較して低価格にて製造出来るというメリットがある反
面、放熱特性が悪い為、端子数が少なく放熱特性が問題
にならない小型のＰＢＧＡにその用途が限定されるとい
う欠点があった。2. Description of the Related Art In recent years, a connecting electrode of an IC chip provided on the upper surface side of a resin substrate and a pad electrode for external connection provided on the lower surface side are connected via a through hole, and the pad electrode is connected to the pad electrode. Has developed a resin-sealed semiconductor device in which a solder bump is provided and the upper surface of the resin substrate is resin-sealed. These semiconductor devices are named plastic ball grid arrays (hereinafter abbreviated as PBGA). Have been commercialized. However, while the PBGA has the merit that it can be manufactured at a lower price than the conventional ceramic BGA, it has poor heat dissipation characteristics, so its application is limited to a small PBGA with a small number of terminals and heat dissipation characteristics are not a problem. There was a drawback that
【０００３】上記の欠点を解決する方法としては従来よ
り各種の提案があるが、特に回路基板の下面側に放熱す
る方式としては米国特許５、２８５、３５２号に開示が
ありその構成を図３により説明する。Various proposals have been made in the past as a method for solving the above-mentioned drawbacks. In particular, a method for radiating heat to the lower surface of a circuit board is disclosed in US Pat. No. 5,285,352, and its configuration is shown in FIG. Will be described.
【０００４】図３は回路基板の下面側に放熱機構を設け
たＰＢＧＡの断面図で、１は樹脂基板であり該樹脂基板
１の上面には接続電極２が、又下面側には外部接続用の
パッド電極３が形成され、前記樹脂基板１の上面側の接
続電極２と下面側のパッド電極３とはスル−ホ−ル４を
介して接続されている。更に樹脂基板１のＩＣチップ搭
載部には貫通穴５が形成され、該貫通穴５には熱伝導の
良い金属よりなる放熱ブロック６が埋設される事により
回路基板７が構成されている。FIG. 3 is a cross-sectional view of a PBGA in which a heat dissipation mechanism is provided on the lower surface side of a circuit board. Reference numeral 1 is a resin substrate, on the upper surface of which a connecting electrode 2 is provided, and on the lower surface side, for external connection. Pad electrode 3 is formed, and the connection electrode 2 on the upper surface side of the resin substrate 1 and the pad electrode 3 on the lower surface side are connected via a through hole 4. Further, a through hole 5 is formed in the IC chip mounting portion of the resin substrate 1, and a heat radiating block 6 made of a metal having good thermal conductivity is embedded in the through hole 5 to form a circuit board 7.
【０００５】そして前記回路基板１の上面側のＩＣチッ
プ搭載部にはＩＣチップ９が熱伝導の良い接着材１０に
より固着されると共に前記ＩＣチップ９の各電極はボン
ディング・ワイヤ−１１によって前記接続電極２に接続
されている。更に回路基板７の上面側を封止樹脂１２に
より封止した後、回路基板７の下面側のパッド電極３と
前記放熱ブロック６の下面とに半田バンプ１３を形成す
る事によりＰＢＧＡ１５が完成する。An IC chip 9 is fixed to an IC chip mounting portion on the upper surface side of the circuit board 1 by an adhesive 10 having good heat conductivity, and each electrode of the IC chip 9 is connected by a bonding wire-11. It is connected to the electrode 2. Further, after sealing the upper surface side of the circuit board 7 with the sealing resin 12, the PBGA 15 is completed by forming the solder bumps 13 on the pad electrodes 3 on the lower surface side of the circuit board 7 and on the lower surface of the heat dissipation block 6.
【０００６】上記構成を有するＰＢＧＡ１５は、図示し
ないマザ−ボ−ドに前記半田ボ−ル１３を溶融して実装
される事により、前記ＩＣチップ９に発生した発熱は熱
伝導の良い接着剤１０、放熱ブロック６、半田ボ−ル１
３を介してマザ−ボ−ド側に放出される。The PBGA 15 having the above-mentioned structure is mounted by melting the solder ball 13 on a mother board (not shown), so that the heat generated in the IC chip 9 has good thermal conductivity. , Heat dissipation block 6, solder ball 1
It is discharged to the mother board side via the No. 3.
【０００７】[0007]
【発明が解決しようとする課題】前記ＰＢＧＡ１５の構
成はＩＣチップの発熱を回路基板側に放出できる、とい
う点に於いて優れているが構成的には樹脂基板１の貫通
穴５に放熱ブロック６を整合して位置決めする方式であ
る為、樹脂基板１の厚さのバラツキや貫通穴５の加工制
度のバラツキの影響を受けやすく回路基板７の上面側及
び下面側の位置制度が安定せず、ＩＣチップ９の接着位
置や半田バンプ１３の形成高さが安定しないという問題
がある。The structure of the PBGA 15 is excellent in that the heat generated by the IC chip can be radiated to the circuit board side, but the heat dissipation block 6 is formed in the through hole 5 of the resin substrate 1 structurally. Since it is a method of aligning and aligning, the position accuracy of the upper surface side and the lower surface side of the circuit board 7 is not stable because it is easily affected by the variation in the thickness of the resin substrate 1 and the variation in the processing accuracy of the through hole 5. There is a problem that the bonding position of the IC chip 9 and the formation height of the solder bump 13 are not stable.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
の本発明の要旨は下記の通りである。両面銅張りした樹
脂基板の上面側に設けたＩＣチップの接続電極と、下面
側に設けた外部接続用のパッド電極とをスル−ホ−ルを
介して接続し、前記パッド電極には半田パンプを設ける
と共に前記樹脂基板の上面を樹脂封止してなる半導体装
置に於いて、前記樹脂基板のＩＣチップ搭載部に貫通穴
を設けると共に、該貫通穴内に前記ＩＣチップを配設
し、該ＩＣチップの下面に放熱用の半田バンプを設けた
事を特徴とする。The summary of the present invention for achieving the above object is as follows. An IC chip connection electrode provided on the upper surface side of a resin board with copper on both sides and a pad electrode for external connection provided on the lower surface side are connected via a through hole, and a solder bump is connected to the pad electrode. And a through hole is provided in an IC chip mounting portion of the resin substrate, and the IC chip is disposed in the through hole. A feature is that a solder bump for heat dissipation is provided on the lower surface of the chip.
【０００９】又、両面銅張りした樹脂基板の上面側に設
けたＩＣチップの接続電極と、下面側に設けた外部接続
用のパッド電極とをスル−ホ−ルを介して接続すると共
にＩＣチップ搭載部に貫通穴を設けた回路基板とＩＣチ
ップとを、前記回路基板の貫通穴内にＩＣチップを位置
決めした状態にて治具板に仮固定する工程と、前記ＩＣ
チップの電極と回路基板の接続電極とを接続する工程
と、前記回路基板の上面側を樹脂封止する工程と、前記
治具板を剥離する工程と、前記回路基板下面のパッド電
極と前記ＩＣチップの下面とに半田バンプを形成する工
程とを有する事を特徴とする。Further, the connection electrodes of the IC chip provided on the upper surface side of the resin substrate with copper-clad double-sided and the pad electrodes for external connection provided on the lower surface side are connected through the through hole, and the IC chip is also provided. A step of temporarily fixing the circuit board having a through hole in the mounting portion and the IC chip to a jig plate with the IC chip positioned in the through hole of the circuit board;
The step of connecting the chip electrode and the connection electrode of the circuit board, the step of resin-sealing the upper surface side of the circuit board, the step of peeling the jig plate, the pad electrode on the lower surface of the circuit board, and the IC And a step of forming solder bumps on the lower surface of the chip.
【００１０】[0010]
【実施例】図１は本発明の樹脂封止型半導体装置の実施
例であるＰＢＧＡの断面図であり図３に示すＰＢＧＡと
同一部材には同一番号を付し説明を省略する。図１に示
すＰＢＧＡ１５０に於いて図３にしめすＰＢＧＡ１５と
の違いは樹脂基板１の貫通穴５０をＩＣチップ９の径よ
りも大きく形成し、その貫通穴５０の中にＩＣチップ９
を直接配置すると共に、該ＩＣチップ９の裏面に放熱用
の半田バンプ１３を直接形成したことである。尚２０は
ＩＣチップ９の裏面と半田バンプ１３との密着力を改善
する為に塗布された銀ペ−スト層、２１は半田バンプ１
３の形成と回路基板７の防湿処理を兼ねたレジスト・フ
ィルムである。1 is a sectional view of a PBGA which is an embodiment of a resin-sealed semiconductor device of the present invention. The same members as those of the PBGA shown in FIG. The difference between the PBGA 150 shown in FIG. 1 and the PBGA 15 shown in FIG. 3 is that the through hole 50 of the resin substrate 1 is formed larger than the diameter of the IC chip 9 and the IC chip 9 is inserted in the through hole 50.
And the solder bumps 13 for heat dissipation are directly formed on the back surface of the IC chip 9. Reference numeral 20 is a silver paste layer applied to improve the adhesion between the back surface of the IC chip 9 and the solder bump 13, and 21 is the solder bump 1.
3 is a resist film that has both the formation of 3 and the moisture-proof treatment of the circuit board 7.
【００１１】次に図１に示すＰＢＧＡ５０の製造方法を
説明する。図２は図１に示すＰＢＧＡ５０の製造工程を
示す工程図であり、図１（ａ）は前記回路基板７の貫通
穴５０内に前記ＩＣチップ９を位置決めした状態にて、
前記回路基板７とＩＣチップ９とを熱可塑性のフィルム
状接着材４１により金属性の治具板４０に仮接着した状
態を示す仮接着工程であり、この状態では回路基板７の
下面側のパッド電極３はフィルム状接着材４１のなかに
食い込んだ状態となっている。Next, a method of manufacturing the PBGA 50 shown in FIG. 1 will be described. FIG. 2 is a process diagram showing a manufacturing process of the PBGA 50 shown in FIG. 1. FIG. 1A shows a state in which the IC chip 9 is positioned in the through hole 50 of the circuit board 7.
This is a temporary bonding step showing a state where the circuit board 7 and the IC chip 9 are temporarily bonded to the metallic jig plate 40 by the thermoplastic film adhesive material 41. In this state, the pads on the lower surface side of the circuit board 7 are provided. The electrode 3 is in a state of digging into the film adhesive material 41.
【００１２】図１（ｂ）はワイヤ−ボンデング工程とモ
−ルド工程とを示すものであり、前記ＩＣチップ９の電
極をボンデング・ワイヤ−１１により前記接続電極２に
接続した後、前記治具板４０ごと金型内にセットして射
出成形により封止樹脂１２を形成する。FIG. 1B shows a wire bonding step and a molding step. After the electrodes of the IC chip 9 are connected to the connection electrodes 2 by the bonding wires 11, the jig is used. The plate 40 is set in a mold together with the plate 40, and the sealing resin 12 is formed by injection molding.
【００１３】図１（ｃ）は治具板剥離工程と、ＩＣチッ
プ裏面処理工程とを示すものであり加熱処理によって熱
可塑性のフィルム状接着材４１を軟化させた状態にて前
記治具板４０を剥離し、しかる後ＩＣチップ９の裏面に
半田バンプとの密着力を良くする為の銀ペ−スト層２０
を塗布する。尚、前記ＩＣチップ９の裏面が金メッキ処
理されている場合は、金メッキ層が半田バンプとの密着
力が良い為、前記銀ペ−スト層２０の塗布工程を省略す
る事ができる。FIG. 1C shows a jig plate peeling step and an IC chip back surface treating step. The jig plate 40 is made in a state where the thermoplastic film adhesive 41 is softened by heat treatment. And then the silver paste layer 20 for improving the adhesion to the solder bumps on the back surface of the IC chip 9.
Apply. When the back surface of the IC chip 9 is gold-plated, the gold plating layer has good adhesion to the solder bumps, so that the step of applying the silver paste layer 20 can be omitted.
【００１４】更に前記図１に示す如く、回路基板７の下
面側に各パッド電極３及びＩＣチップ９の半田バンプ形
成部に円形の窓穴を有する耐熱性のレジスト・フィルム
２１を張り、該レジスト・フィルム２１の各窓穴に半田
ボ−ルを供給した後、加熱処理を行って半田バンプ１３
を形成する事によりＰＢＧＡ１５０が完成する。Further, as shown in FIG. 1, a heat-resistant resist film 21 having circular window holes is formed on the lower surface side of the circuit board 7 at the solder bump forming portion of each pad electrode 3 and the IC chip 9, and the resist is formed. After the solder balls are supplied to the window holes of the film 21, heat treatment is applied to the solder bumps 13
The PBGA 150 is completed by forming the.
【００１５】図４は本発明の他の実施例を示すＰＢＧＡ
の断面図であり、図１に示すＰＢＧＡと異なるのは、前
記封止樹脂１２に上放熱板６０をインサ−トモ−ルドし
た構成である。この構成によってＩＣチップ９より発生
した発熱は下面側の放熱用半田バンプ１３と上放熱板６
０との上下両方向に発散される為、更に放熱特性は改善
される。FIG. 4 is a PBGA showing another embodiment of the present invention.
2 is different from the PBGA shown in FIG. 1 in that the sealing resin 12 is provided with an upper heat dissipation plate 60 in an insert mold. With this configuration, the heat generated from the IC chip 9 is applied to the heat dissipation solder bumps 13 on the lower surface side and the upper heat dissipation plate 6.
Since it diverges in both the upper and lower directions with respect to 0, the heat dissipation characteristics are further improved.
【００１６】尚、前記各実施例ではモ−ルド工程として
射出成形による樹脂封止を示したが本願はこれに限定さ
れる物ではなく、例えば熱可塑性樹脂によるポッティン
グ等の技術によって封止樹脂を形成する事も本願の範囲
に含まれるものである。In each of the above-mentioned embodiments, resin molding by injection molding is shown as the molding process, but the present invention is not limited to this. For example, the sealing resin may be molded by a technique such as potting with a thermoplastic resin. Forming is also included in the scope of the present application.
【００１７】[0017]
【発明の効果】上記のごとく本発明によれば、ＩＣチッ
プが発生する発熱を回路基板の下面側より放出する方式
に於いて、従来の様な放熱ブロックを設けずに、ＩＣチ
ップの裏面より直接放熱する構成となっている為極めて
優れた放熱効果を奏すると共に放熱ブロックの廃止によ
るコストダウンができる。又、回路基板とＩＣチップと
の位置決めは治具板を用いて両者の底面位置をそろえる
事が出来る為、各位置精度を高めると共にその製造工程
を簡素化する事ができる。更に、ＩＣチップを回路基板
の貫通穴に完全に埋設する構造である為、その分だけＰ
ＢＧＡの薄型化が可能となる。As described above, according to the present invention, in the system in which the heat generated by the IC chip is radiated from the lower surface side of the circuit board, the heat radiation block as in the prior art is not provided and the heat is generated from the back surface of the IC chip. Since it is configured to radiate heat directly, it has an extremely excellent heat radiating effect, and the cost can be reduced by eliminating the heat radiating block. Moreover, since the bottom surface positions of the circuit board and the IC chip can be aligned by using a jig plate, the accuracy of each position can be improved and the manufacturing process thereof can be simplified. Further, since the IC chip is completely buried in the through hole of the circuit board, the P
It is possible to make the BGA thinner.
【図１】本発明の樹脂封止型半導体装置を示す断面図で
ある。FIG. 1 is a cross-sectional view showing a resin-encapsulated semiconductor device of the present invention.
【図２】本発明の樹脂封止型半導体装置の製造工程を示
す工程図である。FIG. 2 is a process drawing showing a manufacturing process of a resin-sealed semiconductor device of the present invention.
【図３】従来の樹脂封止型半導体装置を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional resin-sealed semiconductor device.
【図４】本発明の樹脂封止型半導体装置の他の実施例を
示す断面図である。FIG. 4 is a sectional view showing another embodiment of the resin-encapsulated semiconductor device of the present invention.
１ 樹脂基板 ３ パッド電極 ５、５０ 貫通穴 ７ 回路基板 ９ ＩＣチップ １２ 封止樹脂 １３ 半田バンプ １５、１５０ 樹脂封止型半導体装置 1 Resin Substrate 3 Pad Electrodes 5 and 50 Through Holes 7 Circuit Board 9 IC Chip 12 Sealing Resin 13 Solder Bumps 15 and 150 Resin Sealing Type Semiconductor Device
Claims (2)
たＩＣチップの接続電極と、下面側に設けた外部接続用
のパッド電極とをスル−ホ−ルを介して接続し、前記パ
ッド電極には半田パンプを設けると共に前記樹脂基板の
上面を樹脂封止してなる半導体装置に於いて、前記樹脂
基板のＩＣチップ搭載部に貫通穴を設けると共に、該貫
通穴内に前記ＩＣチップを配設し、該ＩＣチップの下面
に放熱用の半田バンプを設けた事を特徴とする樹脂封止
型半導体装置。1. A pad for connecting an IC chip provided on the upper surface side of a double-sided copper-clad resin substrate and a pad electrode for external connection provided on the lower surface side are connected through a through hole to form the pad. In a semiconductor device in which a solder bump is provided on an electrode and the upper surface of the resin substrate is resin-sealed, a through hole is provided in an IC chip mounting portion of the resin substrate and the IC chip is arranged in the through hole. And a solder bump for heat dissipation is provided on the lower surface of the IC chip.
たＩＣチップの接続電極と、下面側に設けた外部接続用
のパッド電極とをスル−ホ−ルを介して接続すると共に
ＩＣチップ搭載部に貫通穴を設けた回路基板とＩＣチッ
プとを、前記回路基板の貫通穴内にＩＣチップを位置決
めした状態にて治具板に仮固定する工程と、前記ＩＣチ
ップの電極と回路基板の接続電極とを接続する工程と、
前記回路基板の上面側を樹脂封止する工程と、前記治具
板を剥離する工程と、前記回路基板下面のパッド電極と
前記ＩＣチップの下面とに半田バンプを形成する工程と
を有する事を特徴とする樹脂封止型半導体装置の製造方
法。2. An IC chip connecting electrode provided on the upper surface side of a double-sided copper-clad resin substrate and a pad electrode for external connection provided on the lower surface side are connected together through a through hole. A step of temporarily fixing the circuit board and the IC chip having through holes in the mounting portion to the jig plate in a state where the IC chip is positioned in the through hole of the circuit board; and the electrodes of the IC chip and the circuit board. Connecting the connection electrode,
A step of sealing the upper surface side of the circuit board with resin, a step of peeling the jig plate, and a step of forming solder bumps on the pad electrodes on the lower surface of the circuit board and the lower surface of the IC chip. A method of manufacturing a resin-encapsulated semiconductor device, which is characterized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3951495A JP3655338B2 (en) | 1995-02-28 | 1995-02-28 | Resin-sealed semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3951495A JP3655338B2 (en) | 1995-02-28 | 1995-02-28 | Resin-sealed semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08236665A true JPH08236665A (en) | 1996-09-13 |
| JP3655338B2 JP3655338B2 (en) | 2005-06-02 |
Family
ID=12555160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3951495A Expired - Lifetime JP3655338B2 (en) | 1995-02-28 | 1995-02-28 | Resin-sealed semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3655338B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010018381A (en) * | 1999-08-19 | 2001-03-05 | 마이클 디. 오브라이언 | Circuit board using conductive ink and semiconductor package using the same |
| US6377465B1 (en) * | 1999-01-14 | 2002-04-23 | Nec Corporation | Printing wiring board |
| JP2003078108A (en) * | 2001-08-31 | 2003-03-14 | Hitachi Chem Co Ltd | Semiconductor package board, semiconductor package using the same and its laminate, and method of manufacturing them |
| KR100400826B1 (en) * | 1999-08-24 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package |
| US6791195B2 (en) | 2000-04-24 | 2004-09-14 | Nec Electronics Corporation | Semiconductor device and manufacturing method of the same |
| KR100878169B1 (en) * | 2005-06-10 | 2009-01-12 | 샤프 가부시키가이샤 | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device |
| JP2010272734A (en) * | 2009-05-22 | 2010-12-02 | Elpida Memory Inc | Semiconductor device and manufacturing method thereof |
-
1995
- 1995-02-28 JP JP3951495A patent/JP3655338B2/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6377465B1 (en) * | 1999-01-14 | 2002-04-23 | Nec Corporation | Printing wiring board |
| KR20010018381A (en) * | 1999-08-19 | 2001-03-05 | 마이클 디. 오브라이언 | Circuit board using conductive ink and semiconductor package using the same |
| KR100400826B1 (en) * | 1999-08-24 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package |
| US6791195B2 (en) | 2000-04-24 | 2004-09-14 | Nec Electronics Corporation | Semiconductor device and manufacturing method of the same |
| JP2003078108A (en) * | 2001-08-31 | 2003-03-14 | Hitachi Chem Co Ltd | Semiconductor package board, semiconductor package using the same and its laminate, and method of manufacturing them |
| KR100878169B1 (en) * | 2005-06-10 | 2009-01-12 | 샤프 가부시키가이샤 | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device |
| US7723839B2 (en) | 2005-06-10 | 2010-05-25 | Sharp Kabushiki Kaisha | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device |
| JP2010272734A (en) * | 2009-05-22 | 2010-12-02 | Elpida Memory Inc | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3655338B2 (en) | 2005-06-02 |
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