JPH08235102A - Dma controller with mechanism for designation of substitute device stream and memory space in dma transfer period - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system and method for designating a substitute data stream and memory address space during a DMA transferring period. SOLUTION: The key field of a channel command is constituted so that the use of a substitute data port instead of a standard data stream can be designated. The data port can be formed in an unaddressed substitute data stream, such as the control/status steam, etc., or in another addressable space, such as the system memory, input-output address space, channel register space, etc. When a second addressable space is designated, another channel register is used for storing secondary addresses.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention generally relates to direct memory access-DM.
A) The present invention relates to a controller, and more specifically to a DMA controller having a mechanism for designating an alternative device stream and a memory space during a DMA transfer period.

The description of the present specification is based on the priority of the present application, US Patent Application No. 08 / 340,249 (1).
(November 16, 1994), and the description of the specification of the US patent application constitutes a part of the present specification by referring to the number of the US patent application. I shall.

[0003]

2. Description of the Related Art DMA is a personal computer,
It is a common method for input / output (I / O) on minicomputers and mainframe computers.
This allows data to be transferred in large blocks without processor intervention, using an independent DMA controller that can access the memory where the data is set up in buffers by the host processor. In some implementations, the DMA controller may also be controlled by one or more programs set up in memory by the host processor. Access to the memory is done through the bus by "stealing" the bus cycle from the CPU.

A DMA controller may include one or more channels, where each channel executes its own program and handles one I / O device at a time.

[0005]

Conventionally known channels can handle only one data stream. Depending on the I / O device, such as standard data stream and status data stream,
Some have more than one data stream. In addition, there is sometimes a need to transfer data from one system memory buffer to another, or from system memory to another address space. If these operations could be performed without processor intervention, the performance of the host processor should improve. One reason for specifying an alternate address space in the key field is that an I / O device can exist as a port in another address space.

Therefore, it is an object of the present invention to provide a DMA controller with a channel that can handle more than one data stream of an I / O device.

Other objects and advantages of the present invention will be clarified in the following description. Some will be understood by reading the description, but others may be known by practicing the invention. Further, the objects and advantages of the present invention can be realized through the means and combinations specifically listed in the claims.

[0008]

SUMMARY OF THE INVENTION The present invention comprises at least one
It is intended for a DMA controller with one channel. A channel includes at least one command buffer having a key field and means for selecting one of a plurality of data sources or destinations, at least one of which is a data stream, in response to a bit of the key field. Includes and.

The method of the present invention involves fetching a command having a key field and transferring data between system memory and one of a plurality of data sources or destinations, at least one of which is a data stream. Executing the command by executing.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which form a part of this specification, schematically show preferred embodiments of the present invention, which are referred to as the above general description and the following. Together with the detailed description of the preferred embodiments of the invention, it is intended to be helpful in understanding the principles of the invention.

The present invention will be described below with reference to preferred embodiments. The preferred embodiment herein is a descriptor-based DMA controller and method for its operation. The descriptor here is DM
A command list element, sometimes referred to simply as a buffer descriptor. The term DMA refers to a relatively sophisticated processor (i
nitiator: A relatively simple state machine (called the target) that originates from the initiator
This means that data transfer is performed by a processing command. A system 30 utilizing such a DMA controller is shown in FIG.

The system 30 includes an initiator or host processor 32, a memory 34, a target or D
Input / output (I / I) of MA controller 36 and disk controller, network interface
O) Includes device 38. The operation is initiated by the initiator 32, which is an intelligent component that produces commands. In a typical DMA operation, the initiator creates a new command descriptor list 40, as indicated by arrow 42, and possibly adds these descriptors to an existing command list already in memory. There is also. The command descriptor may refer to a data buffer containing data to and from the I / O device, such as buffers 44 and 46, as indicated by arrows 48 and 50. The buffer is also used by the host processor 32 as indicated by arrow 52.

The host processor 32 sends a WAKEUP signal to the DMA controller 36 as indicated by arrow 54. This WAKEUP signal is used to send the command added recently.
The MA controller begins processing. WAKEUP
Upon receiving the signal, the DMA controller reads the new command and executes the command, as indicated by arrow 56.

For example, to execute command 58, it is necessary to read the data contained in buffer 46 as indicated by arrow 60 and transfer that data to device 38 as indicated by arrow 62. As command processing continues, the DMA controller returns a status to a certain location within the command entry, such as location 64, as indicated by arrow 66, and WAKE
A UP signal is sent to the host processor to indicate that another descriptor has been processed, as indicated by arrow 68. In response, the host processor examines the status information, as indicated by arrow 70, during which the DMA controller fetches and executes the next command 72.

Each device is typically connected to its own data transfer channel. Therefore, the I / O driver software is relieved of the responsibility of dynamically assigning DMA channels to I / O devices. Full duplex
l-duplex) devices (such as Ethernet) are usually assigned two data transfer channels,
In that case, the data is being transmitted simultaneously in both directions. For half-duplex devices (such as disk controllers) one channel is sufficient.

In most cases, the transfer of control information (such as seek address) occurs before the start of the data transfer.
Similarly, status information (short transfer count, etc.)
Will be returned after the data transfer is complete. In either case, the control information transfer, the data transfer, and the status information transfer are sequentially performed, so that the same DMA channel resource can be shared.

The commands in the device-specific command list are expected to be used individually to support half-duplex traffic and in pairs to support full-duplex traffic. The commands in these lists are usually temporary in that they are constantly consumed as I / O operations are performed. However, some I / O operations (such as terminal reads and flow control writes) may persist indefinitely.

The descriptor list space 40 is allocated by the host processor 32 and contains a set of command list entries before its ownership is passed from the host processor to the DMA controller 36. DM
The A controller 36 fetches the command entry, executes the data transfer operation specified by the command entry, and processes the command entry until the STOP entry is reached or an exceptional condition is detected.

There are several possible ways to construct the descriptor list. For example, configure itself to loop (circular queue), link individual data transfer operations (linked list), or link groups of data transfer operations (hybrid approach) It is possible. Most commands can include branches. The detailed structure of the command list depends on the rules of the I / O driver software.

While the previously started DMA operation is in progress, additional commands are
It can be added dynamically to the list. command·
The list is typically added by creating an additional command list and overwriting the STOP command at the end of the existing command list with a branch to the first command of the new list.

The wait field can be used to perform flow control within the channel. The channel can be programmed to wait until notified by the processor or another device.

Descriptor-based DMA, as shown in FIG.
The controller 36 is expected to indirectly connect a plurality of devices 38, 38 'to the system bus 74, which means that the system bus is in the system memory 3
This is the case where read / write transactions to 4 are supported (FIG. 1). Processor interrupts are either triggered through a special signal wire (for motherboard designs) or by sending a WAKE event (for a 32-bit write to a pre-specified register address). The controller states include a shared state 80 and a channel state 78 (which is duplicated for each connected device).

In some embodiments, the hardware can use some ContextIndex state 80 to identify which of the DMA contexts are currently active, but this state is directly Indirectly, the software cannot access it. Data transfer engine 76
Has the functionality to perform the requested data transfer.

In another embodiment, multiple data transfer engines operate in parallel to create a bus arbiter.
You can access the bus through. This embodiment will be described in detail later.

The I / O devices can be connected to a stream of data bytes, in which case the controller will move the data bytes, excluding these addresses, to or from system memory. Handle what to do. The controller provides a 3-bit key value, as described in detail below. Key·
Four of the key encodings are used to identify which byte stream is being used. Typically, the standard data stream will be stream 0 and the optional control / status stream will be stream 1.

The controller can support direct movement of data between device registers and memory. In this case, the controller provides the sequence of device register addresses while the data is being transferred. The additional key encoding is used to identify transfers to device registers.

Each channel comprises a number of memory mapped registers. These registers contain the CommandPtr used to initialize the sequencer pointer to the command list.
Register 82 (FIG. 2) may be included. 64
This register can be split into a 32-bit CommandPtrLo register and a 32-bit CommandPtrHi register when needed to support bit addressing. Other memory map registers are described below.

There are registers other than the memory map. For example, addPtr register 86 holds the address in memory where the data is read, and count register 88 holds the amount of data that should be read but remains.

The other registers are shown in FIG. 2 as extendState register 84. Some of them are memory maps.

Unrecoverable errors that occur when accessing system memory include parity errors and addressing errors. Retry in use (busy-retry)
The error can be viewed as a recoverable bus error and can be retried until either it completes successfully or the DMA controller command processing is aborted prematurely.

When an unrecoverable error occurs, the dead bit is set in the ChannelStatus register of the currently executing DMA channel. Software is ChannelSta
You must explicitly reset the run bit in the tus register to zero and then return it to the operational state by setting it back to 1.

The control and status registers of the device can be mapped directly into the system memory space so that the processor can access them directly using read and write transactions. In some applications, the processor needs to update these registers after each data transfer, when the channel program does not have to explicitly return device status. However, some devices have the intelligence to autonomously handle multiple data transfer requests. In these applications, processor performance will be impacted if the channel cannot autonomously return device status before starting the next data transfer. The status stream and device status register are the two sources from which the returned device status is obtained.

If the status stream is used, another data transfer command is used to
The byte stream can be transferred to memory.
The unique key value is used to distinguish between the status byte stream and the regular data transfer stream.

If the status register is used, another data transfer command will
Values in the register address range can be transferred to memory. Another unique key value can be used to distinguish this memory map transfer from a normal data transfer stream. However, LOAD_QUAD and STORE_QUAD described later
It is preferred to use special commands such as. Using these commands eliminates the need for additional address registers.

As will be described later, INPUT, OUTPUT and NO
The P command specifies the condition and address for optional branching in the command sequence. A similar mechanism is used to specify conditional interrupt generation and conditional suspension of command processing.

The DB DMA controller architecture has two components that are directly visible to the processor. One is a linear array of channel registers and the other is a linear array that can be directly mapped to the supported device registers. The base of these data structures
The address is defined by the relevant bus standard, or in a ROM data structure whose format is defined by the relevant bus standard, or in the case of a motherboard implementation, a chip or system specification.

Each channel directly stores a STORE_QUAD or LO, which will be described later, through the system address space.
It has a set of registers that can be accessed via commands such as AD_QUAD. Some of these registers are optional and are used to extend the functionality provided by the base channel. Table 1 shows the offset of each of the channel registers. This offset is
When a register is accessed indirectly, it is literally in the Command.address field described below. When directly accessed by a host or channel command, the address of the register is the system-defined channel base address plus the offset value of the register.

[0038]

[Table 1]

In summary, the functions of the mandatory registers are: ChannelControl and ChannelStatus are used to control the channel and monitor channel activity. CommandPtr is used to indicate where in the memory the command list for the channel is located. Details of the entire register set are described below.

The read-only ChannelStatus register allows access to the internal status bits of the channel. The bits in the ChannelControl register are ChannelS
It can also be viewed via the tatus register. ChannelStat
Writing to the us register is ignored. ChannelStatus
The register format is shown in FIG.

In summary, the run bit and pa
The use (pause) bit is a "control" bit that is set and cleared by software. The flush and wake bits are "command" bits that are set by software and cleared by hardware when an action is performed. The dead, active, and bt bits are hardware status bits. Bits s7 ... s0 are available for general purpose status and control. These meanings are channel specific,
These bits can be controlled by either hardware or software.

When the ChannelStatus.run bit is set to 1 by software, the channel will start running. This should only be done after the CommandPtr register has been initialized. Otherwise, the channel's operation will be undefined. When software clears this bit to zero, the channel's operation is aborted. When the operation of the channel is aborted, the data transfer is aborted, the status is returned and an interrupt is generated.
The data temporarily stored in the channel buffer may be lost.

When the ChannelStatus.pause bit is set to 1 by software, command processing is suspended (suspended). In response to this, the hardware suspends data transfer and command execution, and then clears the ChannelStatus.active bit.

Software must reset the ChannelStatus.pause bit to zero to resume command processing.

When the ChannelStatus.flush bit is set to 1 by software, the channel that is executing the INPUT_MORE or INPUT_LAST command will receive the data from the device, but if there is data that has not been written to the memory, the memory will be flushed with that data. Update. When the memory update is completed,
The hardware depends on the channel currently in memory.
Update the xferStatus and resCount fields of the command (the channel command or descriptor fields are described below) and then clear the flush bit. So a "partial" status update would be xferStatus
This is indicated by the flush bit of the field going to '1', and the'final 'status update has this bit set to' 0 '.
Is indicated by.

The ChannelStatus.wake bit, when set by software, wakes up the idle channel, refetches the command pointed to by CommandPtr, and continues command processing. The channel becomes idle after executing the STOP command. The STOP command is Commandd
Do not increment the Ptr register.

The ChannelStatus.dead bit is set by the hardware when the channel stops running due to a significant event such as a bus error or device error. The current command is aborted and the hardware attempts to write the write status back to memory. Subsequent commands are not executed. An unconditional interrupt occurs if the hardwired interrupt signal is implemented. Hardware is ChannelS
Setting tatus.dead causes ChannelStatus.active to be deasserted at the same time. Hardware is ru
If n bits are cleared by software, Chan
Reset the nelStatus.dead bit to zero.

The ChannelStatus.active bit is set to 1 by the hardware in response to this when the software sets the run bit to 1. ChannelStatus.
active means the software clears the run bit or
When the pause bit is set, it is reset by hardware in response to this. This bit is STOP
It is also reset to zero after the command is executed and also when the hardware sets the dead bit to 1.

ChannelStatus.bt bit is NOP, INPUT
, And set by the hardware when the OUTPUT command completes, indicating that a branch has occurred. As described below, the branch is controlled by the Command.b field in the command descriptor, the ChannelStatus.s7..s0 bit and the value of the Mask and Value fields of the BranchSelect condition register. This bit is Command.xfer
Its presence in the Status field allows software to follow the actual channel program flow with minimal overhead.

Each DMA channel has up to eight general purpose state bits (ChannelControl.s7..ChannelControl.s).
0), these bits can be written through the channel control register and read through the ChannelStatus register. Some channel implementations may wish to have other methods of setting and clearing these bits directly through hard-wired connections (eg, on error or logical). To signal the completion of the record). These bits can be tested at the completion of each command to determine if any action is needed. Such actions include generating a hardwired interrupt signal, suspending subsequent command processing, and branching to a new location for subsequent command fetches.

The format of the Channel Control register is shown in FIG. ChannelControl register is Chan
Used as a write port for the bits shown in the nelStatus register. The ChannelControl.mask field selects which of the lower 16 bits should be changed by write. Bits in the lower half of ChannelControl are written only if the corresponding bit in ChannelControl.mask is set.

The value of the ChannelControl.data field is
Conditionally based on the ChannelControl.mask field
Written to ChannelStatus register. Note that, as mentioned above, some of the bits in the ChannelStatus register may not be writable or may only be written to the one state or zero state.

The CommandPtrHi register and the CommandPtrLo register specify the address of the command entry to be fetched next. 1 for all channel commands
Since the boundary is aligned with 6 bytes, the least significant 4 bits of the CommandPtrLo register are always written with zero. If these bits are written with a non-zero value, the operation of the channel is undefined. The value returned when these bits are read is undefined. Comm
The andPtr register can be read at any time, but Co
Writes to the mmandPtr register are ignored unless both ChannelStatus.run and ChannelStatus.active bits are zero.

The InterruptSelect condition register is used to generate interrupt condition bits. This bit is tested at the completion of each command to determine if the hardwired interrupt signal should be asserted.
Its format is shown in FIG.

The two 8-bit res fields are reserved. The software writes a zero value, but the hardware ignores the data value written there. The values returned in these fields when the register is read are undefined. The 8-bit mask and value fields affect the occurrence of interrupts when the command descriptor is processed. The interrupt condition signal "c" can be tested by each channel command and is generated according to the following equation:

[0056]

## EQU00001 ## c = (ChannelStatus.s7..s0 & InterruptSelect.mask) == (InterruptSelect.value & InterruptSelect.mask). The BranchSelect condition register is used to generate the branch condition bit, which is used for each command. Will be tested upon completion to determine if the branch should be taken. The BranchSelect condition register has the same format as the InterruptSelect condition register. The branch condition signal is generated according to the following equation.

[0057]

C = (ChannelStatus.s7..s0 & BranchSelect.mask) == (BranchSelect.value & BranchSelect.mask). The WaitSelect condition register is used to generate wait condition bits, which is Tested on completion to determine if command execution should be suspended (suspended). The WaitSelect condition register has the same format as the InterruptSelect condition register. The wait condition signal is generated according to the following equation.

[0058]

[Formula 3] c = (ChannelStatus.s7..s0 & WaitSelect.mask) == (WaitSelect.value & WaitSelect.mask). The Data2PtrHi and Data2PtrLo registers are moved from the device register space to the second system memory space. Or a secondary 64-bit base address when data is transferred from the channel register or from the channel register.

The AddressHi register is a 32-bit Comman
Used to extend the d.address field to 64 bits. In a 64-bit implementation,
This is the ST that precedes all data transfer commands.
Must be loaded with the ORE_QUAD command. During the initial execution phase of transferring data to the addressed destination, the AddressHi value is the upper 32 bits (DataPtr) of the channel's data buffer address register.
Hi) is loaded.

The BranchAddressHi register is a 32-bit
Used to extend the Command.branchAddress field to 64 bits. In a 64-bit implementation, this needs to be loaded with a STORE_QUAD command that precedes all commands specifying a branch. When a branch is taken, BranchAddressH
The value of i is loaded into CommandPtrHi.

The general format of the command is, as shown in FIG. 6, a 16-bit op-code field (including a 4-bit cmd field), a 16-bit reqCount field, a 32-bit address parameter, and 3 bits.
It consists of a 2-bit cmdDep parameter. xferStat
The us and resCount fields are used by the channel to report status after command completion. The location and size of cmdDep is standardized for all commands, but its interpretation depends on the value of Command.cmd.

The Command.cmd field specifies which type of data transfer is to be performed and is defined as in Table 2 and described below.

[0063]

[Table 2]

The Command.key field is used to select which of the device's "access ports" to use, as specified in Table 3.

[0065]

[Table 3]

In the INPUT and OUTPUT commands, the key field may also specify alternative device streams (eg, data and status), as indicated by arrows 90, 90 ', 92 and 92' in FIG. An alternate secondary address space can also be specified when a two-address transfer is made (along with the Data2Ptr which provides the address to be accessed), as indicated by arrows 94, 94 'and 94 "in 7. System Memory Transfers performed by using the spaces 32 and 32 'as both the source and the destination can be performed by designating as shown by arrows 96 and 96' in FIG. The transfer involving the register space can be designated and executed as shown by an arrow 98 in FIG.

In the LOAD_QUAD command and STORE_QUAD command, the key field is immediate data (immediate dat).
It specifies to which address space a) is transferred.
KEY_STREAM0 to KEY_STREAM3 are invalid in this context.

Table 4 summarizes how the key field works in combination with each of the data transfer commands.

[0069]

[Table 4]

A hardwired interrupt can optionally be triggered when each command completes. Interrupt generation is controlled by the 2-bit Command.i field in combination with the internal interrupt condition bits generated by the channel. The channel uses the current value of the ChannelStatus.s7..s0 bits in combination with the mask and data values contained in each channel's InterruptSelect condition register to generate an interrupt condition based on these values. The algorithm for generating the interrupt condition is as follows.

[0071]

## EQU00004 ## c = (ChannelStatus.s7..s0 & InterruptSelect.mask) == (InterruputSelect.value & InterruptSelect.mask) It should be noted that many implementations interrupt all of the general status bits. Is that it does not need to be generated. In these cases, the interrupt condition can be as simple as tying it to a single status bit or tying it to zero. The above formula is for multiple status
It should be used when it is desirable to generate an interrupt based on the value of a bit.

Table 5 shows how the interrupt condition bits are used with the Command.i field to determine whether to cause an interrupt.

[0073]

[Table 5]

When each command is completed, subsequent command fetches can be optionally suspended. This is controlled by the Command.w field in conjunction with internal wait condition bits generated by the channel interface. Channel interface is Channe
l The current value of status.s7..s0 bit is set to WaitSe of each channel.
Used in conjunction with the mask and data values contained in the lect condition register to generate wait condition bits based on these values. The algorithm for generating the wait condition is as follows.

[0075]

## EQU00005 ## c = (ChannelStatus.s7..s0 & WaitSelect.mask) == (WsitSelect.value & WaitSelect.mask) Table 6 shows how the wait condition bits are used in conjunction with the Command.w field Indicates whether to decide whether to suspend execution.

[0076]

[Table 6]

Most commands (INPUT_MORE / LAST, OUTP
(UT_MORE / LAST and NOP) is completed, CommandPtr
Updated to point to the target of the next command or branch. The branch is controlled by the Command.b field in conjunction with an internal branch condition bit generated by the channel. The channel is ChannelStatus.
The current value of the s7..s0 bit is used together with the mask value and data value contained in the BranchSelect condition register of each channel, and the branch condition bit is generated based on these values. The algorithm for generating the branch condition is as follows.

[0078]

## EQU00006 ## c = (ChannelStatus.s7..s0 & BranchSelect.mask) == (BranchSelect.value & BranchSelect.mask) Table 7 shows how branch conditions are used in conjunction with the Command.b field to branch It indicates whether or not to decide.

[0079]

[Table 7]

As soon as the command completes, the branch condition is evaluated and the CommandPtr is updated.

The Command.reqCount field is used to specify the number of bytes transferred by the data transfer command.

The Command.address field is the primary 32-bit address (ie 6
Used to specify the lowest part of a 4-bit address). For INPUT and OUTPUT commands, this is always the system memory address and points to the data buffer. LOAD_QUAD command and STORE_QUAD
In commands, this is the address from which immediate data is loaded or stored. In this case, this can point to system memory space, device memory space, or channel registers,
This is controlled by the Command.key field.

The meaning and format of the 32-bit Command.cmdDep field are as follows. It depends on the value of cmd. STORE_QUAD command and LOAD_QUA
For the D command, this is the data value read or written. For INPUT and OUTPUT commands this is 32
Used to specify the bit conditional branch target (ie, the least significant part of the 64-bit branch target). A description of each command will be given later.

When the command is complete, the channel's Channe
The current contents of the lStatus register is written to the Command.xferStatus field. The format of the ChannelStatus register is as described above. Commond.xferStat
ChannelStatus.active when us is written to memory
The bit corresponding to is always set to 1. This serves to indicate that the corresponding command has been executed, and xferSt
Both the atus and resCount fields are updated. To take advantage of this feature, the host software must have this bit initialized to zero in the xferStatus field. In the INPUT command, Chan
The nelControl.flush bit provides a mechanism by which software forces the data in the buffer to be written to memory and the status updated before the command completes. The partial status report shows that the flush bit is xfer
It is indicated by being set to 1 in the Status field.

Depending on the device, it may be desirable to automatically get an intermediate status to see how many data bytes have been transferred before the transfer specified in the command descriptor is complete. This can be accomplished by giving the device the ability to set the flush bit in the ChannelControl register. Intermediate status reporting may be useful when the host needs to respond quickly to incoming data, such as terminal input, but it is not desirable to cause a byte-by-byte interrupt.

The intermediate status function is an optional device-dependent function. When this feature is implemented, the conditions under which the partial status is reported are device dependent. For example, this can be done periodically when signaled through device dependent state bits, when a minimum number of data bytes were available, or when a combination of these conditions occurred.

Upon completion of the command, the 16-bit residual byte count value is written to Command.resCount.
This value is usually zero, but can be greater than zero if the device aborts the data transfer.

Command.resCount field and Command.xf
The erStatus field is updated with indivisible operations.

INPUT_MORE, INPUT_LAST, OUTPUT_MORE,
And the OUTPUT_LAST command transfers data between memory and device streams. OUTPUT_MORE and OUTPUT_L
The AST command transfers data from system memory (this data is normally sent to the attached device). The INPUT_MORE and INPUT_LAST commands transfer data (which is usually retrieved from the attached device) to memory. Data chaining is done by using the "MORE" and "LAST" versions of these commands. In the "MORE" command, the current buffer is a logical record (network packet, etc.).
Shows that it is not expected to be completed. "LAS
The T "command indicates that the buffer is expected to complete a logical record. The reqCount field specifies the number of bytes to be transferred, the address field specifies the starting address in system memory, and branch
The Address field specifies the address from which the next command will be fetched if the branch test is successful. These fields are shown in FIG. Comm
The and.key field is used to select which of the device's "access ports" to use.

As is conventional, the OUTPUT or INPUT commands that transfer between system memory and unaddressed device streams are Command.ke
y value must be specified as KEY_STREAM0. The additional stream identification may be used to access other streams available from the device, such as control / status information. Command.key value KEY_SYSTEM and
KEY_DEVICE is used in conjunction with the (optional) Data2Ptr register to transfer two addresses between system memory and the designated space.

In the 64-bit implementation, the upper 32 bits of the buffer address are AddressH
The value of the i register is loaded and before the command, Addr
There is always a STORE_QUAD command that sets essHi to the appropriate value.

The STORE_QUAD command stores a 32-bit immediate value in memory. The 32-bit data32 field specifies the data value, and the address field (used in combination with the key field) specifies the destination address. These fields are shown in FIG.

The field (Command.b) that is normally used to specify whether or not to branch is reserved in this command, and therefore a value of zero is to be written. The operation of the channel is undefined when a non-zero value is written in this field.

Valid values in the reqCount field are 1, 2
Or only 4. For example, if the count is 4, the lower 2 bits of the address are considered to be zero and are ignored, since only aligned transfers are supported.
Similarly, if the count is 2, the low order bits of the address are considered to be zero. If the count is less than 4 bytes,
The least significant byte of data32 is transferred.

Invalid counts are mapped to valid counts as shown in Table 8. ("X" is "Ignore"
(don't care) bit. )

[0096]

[Table 8]

While the STORE_QUAD command is being executed, Co
The mmand.key value is the destination of immediate data.
Specify the address. The key value is KEY_REGS, KEY_SYST
Only EM and KEY_DEVICE can be specified. When other key values are used, the channel's operation is undefined.

The LOAD_QUAD command loads a 32-bit immediate value from memory. The 32-bit data32 field is the destination and the address field (used in combination with the key field) specifies the source address. These fields are shown in FIG.

The field (Command.b) normally used to specify whether to branch is reserved for this command. The software writes a value of zero in this field. When a non-zero value is written to this field, the channel's operation is undefined.

The size and boundary of data transfer are stored in STOR
It is treated the same as for the E_QUAD command.

When the LOAD_QUAD command is executed,
For the value of Command.key, specify the source address of immediate data. The key value that can be specified in KEY_REGS is KEY_SYSTEM
And KEY_DEVICE only. When other key values are used, the channel's operation is undefined.

The NOP command does not transfer data. However, it is possible to use standard mechanisms for specifying to perform an interrupt, branch, or wait action. The NOP command is shown in FIG.

The STOP command deactivates channel processing. This command is placed at the end of the command list, indicating that there are currently no more commands to process. The effect of the STOP command is to idle the channel and
It just clears the ChannelStatus.active bit.
The format of the STOP command is shown in FIG.

Activate additional commands (active)
To add to the channel program, the following sequence must be done. 1) Add a new command to an existing channel program in memory. 2)
Overwrite the STOP command with a branch command. 3) Set the wake bit in the Channel Control register to 1. This allows the channel to process an existing command and process a new command whether or not it had been idle.

[0105]

FIG. 13 is a block diagram showing an embodiment of a DMA controller 100 and devices (102 and 102 'are shown in the drawing) connected thereto. Each channel has its own descriptor execution unit (104 and 10 in the figure).
4'is shown). Other elements 106, 108, 110, 112, 114 and 11
Reference numeral 6 is required as an interface connecting the DMA logic and the specific bus 122. Below, each block shown in the drawing will be described.

Each descriptor execution unit (104 and 1 in the figure)
04 'is shown) and a sequencer state machine (shown at 118 and 118' in the figure) and a data transfer engine (shown at 120 and 120 'in the figure). Contains. As detailed below,
The sequencer state machine fetches the current channel command, parses the command, executes or dispatches the command to the data transfer engine, and sends conditional action bits and commands controlled by the data transfer engine. Responsible for testing the conditional action field and returning the status of the command.

As described in detail below, the data transfer engine uses the data transfer commands OUTPUT_MORE, OUTPUT_
Perform LAST, INPUT_MORE or INPUT_LAST. These commands move data to or from an unaddressed data stream, to or from an addressed stream. Typically, the unaddressed stream is to or from the attached device and the addressed stream is a 32-bit address located in the system memory space.

The bus interface master state machine 116 receives transfer requests from the sequencer state machine and data transfer engine. The transfer request contains information about the size, direction, and type of request to perform. When the transfer request is received, the bus interface master state machine
Cooperate with the state machine 106 to arbitrate and execute the required bus cycles. When the transfer request is complete, the bus interface master state machine signals the completion of the transaction by acknowledging the request.

The bus interface master arbiter 114 arbitrates and handles all sequencer state
Transfer requests and modifier signals from machines and data transfer engines
The qualifying signal is multiplexed into one request and this request is presented to the bus interface master state machine 116. The bus interface master arbiter 114 also demultiplexes the transfer acknowledgment from the bus interface master state machine to the current requester (requestor). The bus interface master
This is so that the state machine design does not depend on the number of requesting channels.

The bus state machine 106 controls the signaling protocol of the system bus. The system bus may be, for example, a peripheral component interconnect (Peripheral Component Intercon
nect-PCI) Can be a bus. For more information, see "PCI Local Bus Spec.
ifications) ”, revised version 2.0.

The interrupt module 108 contains four registers and associated control logic. Interrupt is DM
Three types are supported: A channel interrupts, device interrupts, and external interrupts. DMA channel interrupts are controlled by the interrupt condition field contained in the descriptor or command (see description above). Device interrupts are triggered by connected devices, such as serial communication controllers. External interrupts, like slot interrupts from other onboard PCI devices, are triggered from external sources that are independent of the DMA controller's I / O functions.

The bus interface unit slave state machine module 110, along with the bus state machine module 106
Undertake the PCI slave request targeted by C. For details, refer to the above-mentioned “PCI local bus specification” revised version 2.0. These requirements fall into two categories. Configuration cycle
cycle) and memory cycles. The composition cycle is
Accepted by the bus interface unit slave state machine module to access the configuration registers contained in the module. memory·
The cycle is passed to the bus interface unit slave address decoder module 112 and targets registers located elsewhere in the configuration.

When KEY--DEVICE is specified in the key field of the descriptor, the DMA controller starts an I / O bus cycle instead of a memory bus cycle.

The bus interface unit slave state machine module 110 receives the request as a memory cycle from the PCI bus 122 and sends the request to the bus interface unit slave address
The decoder module 112 decodes and demultiplexes the request received from the bus interface unit slave state machine module 110. When a request comes from the bus interface unit slave state machine module 110, the associated address is decoded and the request is forwarded to the appropriate slave. In the block diagram of FIG. 13, the target of the request can be a sequencer state machine, a data transfer engine, or a register located in the interrupt module. Bus interface unit slave address
The decoder module 112 also multiplexes the acknowledge and read data signals returned from the slave in question.
Present it to the bus interface unit slave state machine module.

When a command is fetched, the sequencer
The state machine "parses" the command. If the command is not a data transfer command (that is, if the command is a STORE_QUAD, NOP or STOP command),
The sequencer state machine is responsible for executing that command. Command is a data transfer command (OUT
PUT_MORE, OUTPUT_LAST, INPUT_MORE, or INPUT_LA
ST), the sequencer state machine hands control to the associated data transfer engine.

When execution of the command is complete (either by the sequencer state machine or the data transfer engine, depending on which command it is), the sequencer state machine tests the conditional field of the current command. The first field tested is the wait field. The sequencer state machine does not advance from the current state until the wait condition test result is false. When the wait test results false, the sequencer state machine writes back the status for the current command. The status information is written back to the last 4 bytes of the 16-bit descriptor (command) structure. When the status write is complete, the sequencer state machine then tests the branch condition for the current command. If the branch condition test is false, the sequencer state machine increments the value of the command pointer register by 16 to point to the next descriptor in the sequence. If the branch condition test is true, the sequencer state machine reads the branch address of the current command and writes that address to the command pointer register. The last condition tested is the interrupt condition. If the test result of the interrupt condition is true, the sequencer state machine notifies the interrupt module to set the DMA channel interrupt for that channel.

The operation of the sequencer state machine will be described with reference to the flow charts of FIGS. 14 and 15. The DMA channel starts in reset state S124 and is set to run when the software writes a "1" to the "Run" bit of the ChannelControl register.
This bit is tested in step S126 of FIG. In response, the sequencer, as indicated by fetch step S128 and fetch completion test S130,
Fetch the descriptor pointed to by the CommandPtr register. Whether or not an error has occurred while fetching the command is tested in test S132, and if an error has occurred, control is performed in status writing step S146.
(Fig. 15). If there are no errors,
The current command is executed as shown in step S134. After test S136 indicates that command execution is complete, a test S138 tests for the presence of errors. Also in this case, if an error has occurred, control is passed to the status writing step S146. If no error has occurred, the wait condition is tested at step S140 and the run bit is tested at test S142. If the run bit is reset, control is passed to the write status step S146. Otherwise, the waiting completion test S144 is performed, and the control right is passed to the test waiting condition step S140 or the status writing step S146 depending on the test result. Once the status is written as shown in status completion test S148, the run bit is tested in test S150. r
If the un bit has been reset, the channel is in reset state S124. If not, the presence or absence of a serious device error is tested in test S152. If an error has occurred, the channel enters dead state S166 after the interrupt is triggered in step S154.
If there are no errors, the interrupt condition is tested in step S158, and if true, an interrupt is generated in step S156. The branch condition is tested in test S160, and the command pointer is incremented by 16 according to the test result (step S164) or set to the branch address (step S162).
In either case, the fetch step S128 is executed next.

When the channel is dead, the run bit is tested in test S168. Channel is in reset state S1 when run bit is reset
24.

The possible data path selections for the key fields are shown in FIGS. 16 and 17, which show different data transfer engines to the I / O device interface and the bus The same sequencer state machine up to the interface is shown. 16 and 17 show a sequencer state machine 170 with a command buffer 176 having a key field 178, a data transfer engine 172 having a command buffer 180 with a key field 182 and a FIFO 186, and an input buffer 172. Output device 17
4 is a block diagram showing FIG. 16 and 17, commands such as LOAD_QUAD are executed by the sequencer state machine 170. Data is transferred to or from the bus interface (not shown) via line 206 and line 204 is used to specify the address space to be accessed. Combinational logic block 184
Can be used to convert the encoding of the key field 178 into the encoding used by the bus interface (eg, selected I / O space or configuration cycle).

Commands such as INPUT_MORE are executed by the data transfer engine 172. At least a portion of the command to be executed is written to the data transfer engine command buffer 180 via line 202. F
IFO 186 is connected to the bus interface through line 200. In FIG. 16, the device 17
4 has a single data input / output for all streams and another input for selecting a particular stream. The FIFO 186 is connected to the data input / output via line 188, and the stream information in the key field 182 is transmitted to the device 174 via line 190. In FIG. 17, device 174 has separate inputs and outputs for different streams and has lines 194 and 196.
It is connected to the. FIFO 186 is connected to lines 194 and 196 via multiplexer / demultiplexer 192 which is controlled by the value of key field 182 through line 198.

FIG. 18 illustrates conditional waits, conditional interrupts, and conditional action permits for conditional branches.
An example is shown for determining each of the (enabling) bits 258, 260 and 262. As shown, the sequencer state machine 170 command
Buffer 176 contains conditional action field Co
mmand.b 208, Command.i 210 and Command.w 2
I have twelve. The data transfer engine 172 may include at least the portion 214 of the ChannelStatus register that contains the bits s7..s0 that affect the execution of the conditional action, as described above. The data transfer engine 172 also has a WaitSelect with a mask field 218 and a value field 220.
InterruptSelect condition register 2 with condition register 216, mask field 232 and value field 234
30 and mask field 246 and value field 2
It is also possible to include a Branchselect register 244 with 48.

Bit s of ChannelStatus register 214
The value of 7..s0 and the value of the mask field 218 of the WaitSelect condition register 216 are the AND gate array 2
22 and the output is (ChannelStatus.s7..s0 &
WaitSelect.mask). WaitSelect condition register 21
The value of the mask field 218 of 6 and the value of the value field 220 of the WaitSelect condition register 216 are input to the AND gate array 224, whose output is (WaitSelec
t.value & WaitSelect.mask). Arrays 222 and 2
The output of 24 is input to the comparator 226, and its 1-bit output is (ChannelStatus.s7..s0 & WaitSelect.mask)
== (WaitSelect.value & WaitSelect.mask). This output, along with the 2 bits of the Command.w field 212, is applied to the combinatorial logic block 228 in the sequencer state machine 170. The truth table for logic block 228 is shown in Table 9.

[0123]

[Table 9]

Bits 260 and 262 are obtained in the same way and elements 216, 218, 220, 222, 22 are included.
4, 226 and 228 are elements 230,
232, 234, 236, 238, 240, and 24
2 corresponding to elements 244 and 24, respectively.
6, 248, 250, 252, 254 and 256.

FIG. 19 shows the ChannelStatus register 268.
It is a figure which shows the Example of. This register is ChannelStatu
It is read using line 270, which corresponds to the address of the s register, and line 266, which corresponds to the data field of the ChannelControl address.
Line 2 corresponding to the mask field of the trol address
Written to the bits allowed by 64.

[0126]

In summary, an apparatus and method for specifying an alternate device stream and memory address space during a DMA transfer has been described. According to the present invention, it is possible to handle I / O devices with more than one data stream and data transfers from one system memory buffer to another location in the same or different address space without processor intervention. it can.

Although the invention has been described with reference to the preferred embodiments, it is not limited to the embodiments shown and described above, but the scope of the invention is as defined in the claims. is there.

[Brief description of drawings]

FIG. 1 is a schematic block diagram illustrating a system that utilizes a DMA controller according to the present invention.

FIG. 2 is a schematic block diagram showing a DMA controller according to the present invention.

FIG. 3 is a diagram showing a format of a ChannelStatus register.

FIG. 4 is a diagram showing a format of a Channel Control register.

[Fig.5] InterruptSelect, BranchSelect and WaitSe
It is a figure which shows the format of a lect condition register.

FIG. 6 is a diagram showing a format of a command entry.

FIG. 7 is a schematic block diagram illustrating the operation of the data port selection function.

[Figure 8] INPUT_MORE, INPUT_LAST, OUTPUT_MORE and
It is a figure which shows the format of OUTPUT_LAST command.

FIG. 9 is a diagram showing a format of a STORE_QUAD command.

FIG. 10 is a diagram showing a format of a LOAD_QUAD command.

FIG. 11 is a diagram showing a format of a NOP command.

FIG. 12 is a diagram showing a format of a STOP command.

FIG. 13 is a schematic block diagram showing an embodiment of a DMA controller according to the present invention.

FIG. 14 shows a flowchart of the operation of the sequencer state machine of FIG.

FIG. 15 shows a flowchart of the operation of the sequencer state machine of FIG.

16 is a schematic block diagram illustrating an embodiment of a data port selection function using a sequencer state machine and a data transfer engine to implement the DMA controller of FIG.

17 is a schematic block diagram of another embodiment of a data port selection engine using a sequencer state machine and a data transfer engine suitable for implementing the DMA controller of FIG.

FIG. 18 is a schematic block diagram showing an embodiment of a conditional action function of the present invention.

FIG. 19 is a schematic block diagram showing an embodiment of a write function with a mask of the control register of the present invention.

[Explanation of symbols]

30 system 32 host processor 34 system memory 36 DMA controller 38 input / output device 40 command descriptor list space 44 buffer 46 buffer 74 system bus 76 data transfer engine 82 CommandPtr register 84 extendState register 86 addPtr register 88 count register 100 DMA Controller 102 connection device 104 descriptor execution unit 106 bus state machine 108 interrupt module 110 bus interface unit slave
State machine module 112 Bus interface unit slave
Address decoder module 114 Bus interface master arbiter 116 Bus interface master state machine 118 Sequencer state machine 120 Data transfer engine 122 PCI bus 170 Sequencer state machine 172 Data transfer engine 174 Input / output device 176 Command Buffer 178 Key Field 180 Command Buffer 182 Key Field 184 Combinatorial Logic Block 186 FIFO

 ─────────────────────────────────────────────────── ─── Continuation of front page (71) Applicant 595167203 1 Infinite Loop, Cupertino California 95014 U. S. A. (72) Inventor David V.I. James United States 94306 Palo Alto South Court, California 3180 (72) Inventor Bruce E. Ecstein USA 95014 Cupertino California Drive 1091 California

Claims (12)

[Claims] 1. A direct memory access (DMA) controller with at least one channel, at least one command buffer having a key field; and the key of the at least one command buffer.
Means for selecting one of a plurality of selectable data sources or destinations, at least one of which is the first data stream, in response to the bits of the field. 2. The DMA controller according to claim 1, wherein the selecting means includes an encoder having an output for connection with an input / output device. 3. The DMA controller according to claim 1, wherein the selecting means includes a group of lines for connecting the key field to an input / output device. 4. The DMA controller of claim 1 wherein said means for selecting comprises a demultiplexer whose output is selected by said bit and whose input receives data from system memory. 5. The means for selecting comprises: an input of which is selected by the bit, and an output of which is system data.
The DMA controller of claim 1, including a multiplexer for transmitting to a memory. 6. The DMA controller of claim 1, 2, 3, 4 or 5, wherein at least one of the selectable data source or destination is a second data stream. 7. At least one of the selectable data source or destination has an address space, and an address accessed by a command in the address space is specified by a register not set by the command. Claim 1, characterized in that
The DMA controller according to 2, 3, 4 or 5. 8. At least one of the selectable data sources or destinations has an address space, and an address accessed by a command within the address space is specified by a register not set by the command. The DMA controller according to claim 6, which is characterized in that: 9. A method of operating a channel of a DMA controller, comprising fetching a command having a key field, system memory and a plurality of selectable data, at least one of which is a first data stream. A method comprising executing the command by transferring data to or from one of a source or a destination. 10. The method of claim 9, wherein at least one of the selectable data source or destination is a second data stream. 11. At least one of the selectable data sources or destinations has an address space, and addresses accessed within the address space are:
10. Designated by a register that was set up before the fetch step.
The method described in. 12. At least one of the selectable data sources or destinations has an address space, and addresses accessed within the address space are:
2. Designated by a register that was set up before the fetch step.
The method described in 0.