JPH08228353A - Motion compensation circuit for moving image encoding - Google Patents

Abstract

PURPOSE: To compress a circuit scale by sharing two filters; a half picture element interpolation filter for MPEG system and a loop filter for H261 system. CONSTITUTION: A filter circuit is operated by switching to a loop filter in accordance with an H261 mode and an MPEG mode and the half picture element interpolation filter by the switching of selectors S61 to 70. When the H261 mode is set, the selectors S61 to 68 select delay circuits 61, 62, delay devices D61, D63 and D67, averaging devices M62 and M64 in accordance with a contact H. Also, the selectors S69, S70 select one of other contacts H1, H2 without selecting a contact M in accordance with the output of the delay devices D66, D67. When the MPEG mode is set, the selectors S61, S63 to 68 select a terminal 61, the delay devices D62, D63, D66 and D67 and the delay circuit 61 in accordance with the contact M. Also, the selectors S62, S69 select one of other two contacts without selecting the contact H in accordance with the output of the delay device D61, D67.

Description

Detailed Description of the Invention

For a sub-block consisting of 8 pixels in the horizontal direction and 8 pixels in the vertical direction in the block that is input to the one half-pixel interpolation filter, 1 is set for the pixels at the upper and lower ends of this sub-block. A vertical one-dimensional filter having coefficients of 1/4, 1/2, and 1/4 for other pixels and 1 for pixels at the left and right ends of the sub-block, and for other pixels. 1/4, 1/2, 1
A moving picture code, wherein a loop filter formed by connecting horizontal one-dimensional filters having a coefficient of / 4 is realized by using the delay means, the averaging means and the selecting means in the moving picture coding filter. Motion compensation circuit.

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation circuit for moving picture coding, and more particularly to the MPEG system and H.264 standard. The present invention relates to a moving picture coding motion compensation circuit used in a moving picture coding circuit shared with the H.261 system.

[0003]

2. Description of the Related Art Since a moving image has an enormous amount of data, it is often desired that the moving image is compressed or transmitted or recorded and then decompressed on the receiving or reproducing side. Conventionally, the application of this type of compression / expansion technology has been limited mainly to large-scale dedicated devices such as video conferencing devices in the field of communication because a means for efficiently compressing / expanding a huge amount of data has not been obtained at low cost. Recently, due to improvements in compression / expansion technology and advances in semiconductor technology, it has become possible to construct a moving image compression / expansion apparatus that can withstand low-cost practical use with a relatively small number of LSIs.

Such a moving picture compression / decompression method is also called a moving picture coding / decoding method, and studies of international standardization have been made. One of them is H.264, which was recommended by CCITT (International Telegraph and Telephone Consultative Committee) in 1990. The H.261 standard mainly targets moving image coding / decoding methods used in videophones and videoconference systems. Also, ISO and C
CITT expert group (ISO / IEC, JTC1
/ SC2 / WG8 (Moving Picture E)
xpert Group (MPEG) MP specified in 1993 as Recommendation ISO / IEC-11172-2
The EG1 standard targets a moving image coding / decoding method used for recording on a storage medium or the like.

In this type of compression method, a motion-compensated interframe predictive coding method is adopted. This is because the prediction frame is created from the previously coded frames by utilizing the high correlation between the frames that make up the moving image, and the difference between the current coding frame (hereinafter referred to as the current frame) and the prediction frame. That is, this is a method of increasing the compression rate by encoding the prediction error. Further, since the position of the moving subject is gradually changed within the frame, the value is reduced by extracting the prediction error after moving the prediction frame according to the movement of the subject, and the compression rate can be further improved. Information representing this motion is called a motion vector, and is transmitted or recorded together with a prediction error.

Predicted frames are generated from frames transmitted or recorded in the past. In a coding / decoding method (hereinafter referred to as H.261 method) conforming to the H.261 standard, a past frame one frame before (hereinafter referred to as past frame) is set as a prediction frame. In addition, in an encoding / decoding method (hereinafter, MPEG method) based on the MPEG1 standard, a future frame (hereinafter, future frame) several frames after, in addition to a past frame several frames before, and this past frame and future frame An imaginary frame obtained by interpolating in the time axis direction (hereinafter, imaginary frame) can be used as the prediction frame. However, when the prediction frame is generated from the future frame, the order of the frames is exchanged, and the current frame is encoded after the future frame to be referenced. When the correlation with the prediction frame is low, such as when the scene changes, the compression rate can be increased by coding the current frame as it is rather than coding the prediction error. Therefore, compression is performed by adaptively switching between the case of encoding the prediction error and the case of encoding the current frame as it is.

Hereinafter, the case where the past frame is used as the prediction frame is called forward prediction coding, the case where the future frame is used as the prediction frame is called backward prediction coding, and the case where the fictitious frame is used as the prediction frame is called bidirectional prediction coding. , These 3
These are collectively called interframe predictive coding. In addition, the case where the current frame is encoded as it is is called intraframe encoding. Therefore, according to the MPEG method, forward predictive coding, backward predictive coding, bidirectional predictive coding and intra-frame coding are possible. In the H.261 system, forward predictive coding and intraframe coding are possible.

H. Referring to FIG. 4 which is a block diagram showing a first moving picture coding circuit corresponding to the H.261 system,
The moving picture coding circuit of (1) calculates the difference between the current frame FI and the past image data DPS corresponding to the predicted frame and outputs difference data DD, and the discrete cosine transform of the difference data DD to generate the signal DT. Cosine transform circuit (DCT) 102 and data D by quantizing signal DT
A quantization circuit 103 for generating Q, a Huffman coding circuit 104 for Huffman coding and compressing the data DQ and outputting coded data DO, a dequantization circuit 105 for dequantizing the data DQ and generating a signal IT, An inverse discrete cosine transform circuit (IDCT) 106 that performs an inverse discrete cosine transform of the signal IT to generate a signal ID, and an adder 107 that adds the signal ID and the past image DP to generate reference frame data PI.
A frame memory 108 that stores the data PI and outputs the predicted frame data FR including the reference area AR; and a motion compensation circuit 109 that generates the address AV and the evaluation data E in response to the supply of the data FR and the vector V. Data F
A motion vector detection circuit 110 for generating a motion vector V from R and DI, a loop filter 111 for filtering an address AV to generate data DP, a current frame FI (MBI), and evaluation data E are supplied and a coding type And a coding type determination circuit 112 for determining the coding type K and outputting the coding type K, and the data DP controlled by the coding type K.
And a selector 113 for selectively outputting data 0.

Referring to FIG. 5, which illustrates the concept of motion vector detection, H.264. In the H.261 format image, the current frame F
I has 16 pixels in each of the horizontal and vertical directions (hereinafter 16
It is divided into square macroblocks of (× 16 pixels).
The macro block MB is further composed of four luminance signal blocks Y of 8 × 8 pixels and two types of color difference signal C blocks of the same number of pixels, that is, a total of six blocks. Here, since the color difference signal is thinned out to 1/2 in the horizontal and vertical directions as compared with the luminance signal, 8 × 8 in the color difference signal block C described above.
The pixels correspond to the 16 × 16 pixel range of the luminance signal block Y. Referring to FIG. 4, the motion vector detection circuit 11
0, each processing of the coding type determination circuit 112 performs processing in macroblock units, and the other processing is performed in block units. Further, in the following description, the macroblock currently being processed in the current frame FI is called the current macroblock MBI.

The operation of the first moving picture coding circuit will be described with reference to FIGS. 4 and 5. First, the coding type judging circuit 112 and the evaluation data E, which will be described later, from the motion vector detecting circuit 110 and the present data. When the current macroblock MBI is supplied with the macroblock MBI, it is determined whether to perform forward predictive coding or intraframe coding. When the first frame is encoded, invalid data is stored in the frame memory 108. In this frame, intraframe encoding is selected for all macroblocks as will be described later. At the time of encoding, one reference frame FR decoded after encoding is stored, and one of forward prediction encoding and intraframe encoding is selected.

The reference area AR is a larger luminance signal area including a macroblock located at the same position as the current macroblock MBI in the reference frame FR. The motion vector detection circuit 110 detects the current macroblock MBI within the reference area AR.
An area of 16 × 16 pixels (hereinafter referred to as a similar block BS) that is most similar to is searched, and the motion vector V in that case is output to the motion compensation circuit 109. The motion vector V of the current macroblock MBI is the difference between the projection position PBS and the position of the current macroblock MBI on the current frame FI of the similar block BS searched in the reference area AR.

At this time, the motion vector detection circuit 110 calculates the evaluation data E for similarity evaluation between the current macroblock MBI and the similar block BS, and supplies it to the coding type determination circuit 112 as described above. The coding type determination circuit 112 compares the evaluation data E with the evaluation data when intraframe coding is performed, and estimates which one of the forward prediction coding and the intraframe coding has a higher compression rate. Then, the coding type K that is the determination result is supplied to the selector 113. However, if the current frame FI has a low correlation with the first frame to be encoded or the reference frame stored in the frame memory 108, such as when the scene changes, it is always determined to be intra-frame encoding.

Next, the current macroblock MBI of the current frame FI is coded block by block according to the coding type K. Therefore, the four luminance signal blocks Y and the two color difference signal blocks C that form the current macroblock MBI are sequentially input. Below, the block currently being processed is called the current block. The motion compensation circuit 109 inputs the motion vector V of the current macroblock MBI, and this vector V and the current block on the current frame FI (hereinafter referred to as the current block FI).
The position of the similar block BS of the reference frame FR stored in the frame memory 108 is obtained from the position of. Next, the address AV of the 8 × 8 pixel luminance signal block or chrominance signal block corresponding to the current block FI
Is calculated, this block is read, and the loop filter 11
Output to 1. Here, the loop filter is H.264. The H.261 method is an option that does not necessarily have to be applied, but is often used because it has an effect of reducing block distortion that occurs in a decoded image.

Referring to FIG. 6 for explaining the principle of the loop filter 111, the loop filter 111 has four kinds of filter coefficients d for weighting the signal level corresponding to the pixel data position in the block. e,
It is a filter that distributes either f or g. This filter has a coefficient of 1 at both ends of the block and 1/4 at the middle.
A one-dimensional filter having three coefficients arranged in the order of 2/4 and 1/4 can be realized by a two-dimensional filter formed by horizontally and vertically applying to an input block. Therefore, the coefficient d is 1, the coefficient e is three coefficient groups arranged in the order of 1/4, 2/4, and 1/4 in the horizontal direction (row), and the coefficient f is 1/4 in the vertical direction (column). 2/4, 1
The three coefficient groups arranged in the order of / 4, and the coefficient g is three coefficients arranged in the order of 1/16, 2/16, 1/16 in the first and third rows and 2/16 in the second row. , 4/1
Each of the groups is composed of nine coefficient groups consisting of three coefficients arranged in the order of 6, 2/16. In this way, the motion compensation circuit 109 and the loop filter 111 form a prediction frame DP, and a prediction block for current block prediction (hereinafter, prediction block DP) is obtained.

The selector 113 is supplied with the prediction block DP and a block with all values of 0 (block 0). If the coding type K is forward predictive coding, the prediction block DP is In the case of encoding, block 0 is selected and output.

The adder 101 calculates the difference data DD as the current block F when the coding type K is forward predictive coding.
The difference between I and the prediction block DP, that is, the prediction error block is output, and in the case of intraframe coding, the current block FI
And block 0, that is, the current block FI is output as it is.

The DCT 102 converts the difference data DD into frequency component data DT by discrete cosine transform and supplies it to the quantization circuit 103. The quantizing circuit 103 divides this frequency component data DT by a parameter called a quantizing threshold value to quantize the quantizing data DQ in the Huffman coding circuit 1.
04 and the inverse quantization circuit 105. As a result,
Although some loss of high frequency component information occurs, it is inconspicuous, so that compression is possible without substantial image quality deterioration. Next, the Huffman coding circuit 104 further compresses the quantized data DQ using statistical properties and outputs it as output data DO.

On the other hand, the dequantization circuit 105 multiplies the supplied quantized data DQ by the quantized threshold value and restores the frequency component data to generate the data IT. The inverse DCT 106 performs inverse discrete cosine transform on the data IT and supplies the data ID obtained by restoring the prediction error block or the current block to the adder 107. However, this data ID is used for quantization, inverse quantization operation, DCT, and inverse DC.
Although it does not match the difference data DD due to the T calculation error,
It can be close enough. When the coding type K is forward predictive coding, the adder 107 adds the data ID corresponding to the restored prediction error block and the prediction block DP from the selector 113, and restores as the data PI corresponding to the current block FI. it can. In the case of intra-frame coding, the restored current block FI and block 0 are added,
Similarly, the data PI corresponding to the current block FI can be restored.
After being encoded in this way, the decoded data PI corresponding to the current block is stored in a predetermined address of the frame memory 108 and used as the reference frame FR of the next encoding target frame.

Next, referring to FIG. 7, in which the second moving picture coding circuit corresponding to the MPEG system is also shown in the same block with common reference characters / numerals attached to the same components as in FIG. 4, The difference between this second moving picture coding circuit and the first moving picture coding circuit is that instead of the frame memory 108, a frame memory 108A for storing two reference frames, past and future, and motion vector detection. Instead of the circuit 110, a motion vector detection circuit 110A that detects a motion vector V in half-pixel units, and inter-frame prediction when determining an employable coding type corresponding to each frame of I, P, and B described later. That is, the inter-frame prediction selection circuit 115 that selects an encoding method is provided, and the loop filter 111 is unnecessary.

The operation will be described. In the MPEG system, three types of frames called I frame, P frame, and B frame are defined, and the applicable coding types are different. That is, when the current frame is an I frame, all macroblocks in the frame are intraframe coded. In the case of the P frame, the macroblock in the frame is encoded by either the forward prediction encoding or the intraframe encoding type. In the case of a B frame, a macroblock in a frame is coded by selecting one of four coding types: forward predictive coding, backward predictive coding, bidirectional predictive coding, or intraframe coding. To do. As described above, when the current frame is the B frame, it is necessary to select the interframe predictive coding method when determining the coding type.

Therefore, the three types of interframe predictive coding prediction values obtained by the motion compensation circuit 109 and the current macroblock MBI are supplied to the interframe prediction selection circuit 315, and the interframe prediction selection circuit 115 receives these three types. Evaluate the similarity between each of the predicted values of P and the current macroblock MBI.
Then, the most similar predicted value DPM is set to the selector 113.
And the data PE including the evaluation data in the case of the interframe prediction method and the signal indicating the interframe prediction method to the coding type determination circuit 112. When the current frame is a P frame or an I frame, the inter-frame prediction selection circuit 115 can always handle the three types of frames by selecting the forward prediction coding. The coding type determination circuit 112 compares the input evaluation data PE with the evaluation data in the case of intra-frame coding, and sets the coding method estimated to increase the compression rate as the coding type K of the current macroblock. However, if the current frame is an I frame, the intraframe coding is always selected.

As described above, the frame memory 108
A stores two past and future reference frames for forward prediction and backward prediction, respectively. Furthermore, the motion vector detection circuit 310A is an H.264 / AVC. Unlike the 261 system,
The motion vector V is detected in half pixel units. In addition, in the B frame, in addition to the forward motion vector VA, the backward motion vector VB using the future reference frame is output.

In the half-pixel unit motion vector detection, first, half-pixel interpolation of the reference area is performed, and then a similar block is searched.

The concept of half-pixel interpolation is shown, and the position of the half-pixel is defined as ×
The half-pixel interpolation method will be described with reference to FIG. 8, which is an explanatory diagram shown in FIG. 7. As an example, the pixel data c1 to c5 at the half-pixel position in the area HB1 shown in the lower part of the figure are used to determine the positions of the surrounding original pixels. The pixel data b1 to b4 are interpolated. First, the surrounding pixel data c1 to c4 are respectively pixel data b1 and b2, b3 and b4, b1 and b3, and b.
It is calculated by averaging each of 2 and b4. Further, the central pixel data c5 is obtained by first averaging the pixel data c3 and c4 in the horizontal direction first by the average in the vertical direction, or by vertically averaging the pixel data c1 and c2 initially obtained by the average in the horizontal direction. . Pixel data in half-pixel units is created by such half-pixel insertion, and a similar block is searched using this data to calculate a motion vector V in half-pixel units.
Ask for. The prediction block DP used for coding each block in the current macroblock MBI is also obtained by half-pixel interpolation if the motion vector indicates half-pixel accuracy.

As described above, H. Although the H.261 coding system and the MPEG coding system have been described, since both of these systems have many similar parts, a common moving picture coding circuit that implements both coding systems is used.

Conventional MPEG, H.264. 261 which is a block diagram of the motion compensation circuit 109B for both of the two systems, the motion compensation circuit 109B shown in the figure is similar to the H.261 motion compensation circuits 109, 109A and H.264. It has the functions of the H.261 system loop filter 111 and the MPEG system inter-frame prediction selection circuit 115. The motion compensation circuit 109B is an address generator 1 that generates an address of the frame memory 2 in response to the supply of the motion vector V.
, A frame memory 2, an address generator 3 for generating addresses in the reference memories 4 and 5, reference memories 4 and 5 in forward and backward directions, a loop filter 16, and forward and backward directions, respectively. Half-pixel interpolation filters 17 and 18 for outputting the forward and backward prediction frames FRA and FRB, respectively, by half-pixel interpolation, and an averaging unit 19 including an adder and a 1/2 multiplier, An inter-frame prediction selection circuit 7 and a selector 12 are provided.

For convenience of explanation, MPEG, H.264 and H.264 are used. The H.261-based encoding operation is performed in the MPEG mode,
H. 261 mode, and the operation of the conventional motion compensation circuit 109B will be described with reference to FIG.
In the H.261 mode, the address generator 1 is supplied with the motion vector V of the current macroblock MBI, and the prediction block D is calculated from the motion vector V and the position of the current block FI.
The pixel data address ADP for generating P is calculated and output. Next, this pixel data is read from the frame memory 2 and stored in the reference memory 4. Referring to FIG. 10, the reference memory 4 has a capacity of 9 × 9 pixels corresponding to respective addresses from the upper left pixel data a0 to the lower right pixel data a80, and the read area of 8 × 8 pixels is the upper left. 8 × 8
Store at the pixel position.

Next, the address generator 3 includes the reference memory 4
Addresses are generated in the order of raster scanning from the pixel data a0 at the upper left stored in the pixel data a0 to the pixel data a80 at the lower right in the horizontal direction, and the addresses are output to the loop filter 6 for each pixel data.

Referring to FIG. 11 which shows the configuration of the loop filter 16 in blocks, the loop filter 16 delays the pixel data a0 to a80 corresponding to the reference frame FR by 9 clocks and a delay circuit 61 by 8 clocks. Delay device 62 and D flip-flop (hereinafter DFF)
1-clock delay devices D161 to D166, averaging devices M161 to M164, selectors S161 and S16
In order to realize the loop filter shown in FIG. 6 including 2 and 1, first, a vertical filter is generated, and then a horizontal filter is generated.

The operation will be described with reference to FIG. 11 and FIG. 12 showing an operation time chart. Here, it is assumed that the pixel data A (a0 to a80) is input pixel by pixel for each clock. First, in the vertical filtering process, a total of 18 clocks of delayed pixel data AD and input pixel data A that have passed through the delay circuits 61, D161 and 162 are passed.
Is calculated by the averaging device M161, and the average value is delayed by one clock by the delay device D162 and the delay device D1.
The average CA with the output AA of 61 is obtained by the averaging device M162. Since the reference memory 4 in the forward direction has a capacity of 9 pixels in the horizontal direction, the output of the averaging device M161 is the average of the input pixel data ai at an arbitrary position and the pixel data two pixels above in the vertical direction. , The output CA of the averager M162
Is the average of the average and the pixel data one pixel above in the vertical direction from the input pixel, that is, the output of the vertical filter having the coefficients of 1/4, 2/4, and 1/4. For example, at time t5 in FIG. 12, the input pixel a18 and a0 on the two pixels are averaged, and at time t6, (a0 + a18) / 2 is added to the delay device D16.
Write to 2. And this and the output AA of the delay device D161
The average (a0 + 2a9 + a18) / 4 with the corresponding a9 is C
A is written in the delay device D163 at time t7. In the selector S161, the pixel data AA is a region (a0 to a8, a72 to a80) indicated by the coefficients d and e of the loop filter.
If yes, select data AA, otherwise select data CA.

Next, the horizontal calculation is performed by the selector S161.
Output DA of the delay device D163 which is obtained by delaying the output of the vertical filter from 1 to 1 clock, and the output DA is further delayed by the delay device D
The average of the vertical filter output EA delayed by 2 clocks by 164 and D165 is obtained by the averaging device M163, and the average thereof is delayed by one clock by the delay device D166, and the average of the value FA and the value EA is obtained by the averaging device M164. . Here, since one pixel is delayed in the horizontal direction for one clock,
The output of the averaging device M163 is the vertical filter output DA.
And the average of the vertical filter outputs left by two pixels in the horizontal direction from that, and the output of the averager M164 is the average of the vertical filter outputs at a position between these averages, that is, 1/4, It becomes the output of the horizontal filter having the coefficients of 2/4 and 1/4. For example, at time t9, DFF
162 output EA (a0 + 2a9 + a18) / 4 and DF
FDA output DA (a2 + 2a11 + a20) / 4 and average (a0 + 2a9 + a18 + a2 + 2a11 + a2
0) / 8 is calculated, and the delay device D166 is calculated at time t10.
Write as data FA to. And this and delay device D16
5 output (a1 + 2a10 + a19) / 4 average (a0 + 2a9 + a18 + 2a1 + 4a10 + 2a19)
+ A0 + 2a9 + a18 + a2 + 2a11 + a20) /
16 is calculated and is output as data DPL. The selector S162 has a region (a0, a9, a1) in which the output EA of the delay device D165 is indicated by the loop filter coefficients d, f.
8, ..., A72, a8, a17, ..., A80), the data EA is selected, and the others are averager M1.
Select 64 output GAs. Thus, the selector S16
1, the loop filter 16 is controlled by controlling S162.
Can be realized.

The selector 12 uses the H.264 standard. In the 261 mode, the output data DPL of the loop filter 16 is selected and output as the data DP. As described above, this data DPL is composed of 9 × 9 pixels, of which the upper left 8 ×
8 pixels (time t0 to t7, t9 to t16, etc.) 26
It becomes a prediction block in one mode.

Next, in the MPEG mode, the motion compensation circuit 109B operates in the forward direction to select the interframe prediction method.
Prediction values FRA and FR for backward and bidirectional predictive coding
B and FRC are output in parallel. However, these three predicted values FRA, FRB, and FRC are valid only in the current frame F.
When I is a B frame and when it is a P frame, only the predicted value FRA is valid, and in the I frame, all three predicted values are invalid.

If the current frame FI is a B frame,
First, since half-pixel interpolation is performed in accordance with a half-pixel precision motion vector, the address generator 1 determines the address ADP from the forward and backward motion vectors VA and VB of the current macroblock MBI and the position of the current block. And the pixel data of 9 × 9 pixels for generating each of the forward and backward prediction blocks are stored in the reference memories 4 and 5, respectively. When the least significant bit (hereinafter, vx0) corresponding to the half-pixel precision of the horizontal component of the motion vector V is 0, the rightmost pixel is not necessary for predictive block generation, but is read and referenced for simplification of control. Fill memory 4 or 5 from the upper left corner. Similarly, the least significant bit (hereinafter vy0) corresponding to the half pixel precision of the vertical direction component of the motion vector V is 0.
In case of, the lowest pixel is not necessary, but it is read from the upper left corner and packed.

Next, the address generator 3 generates addresses in raster scanning order, and at the same time outputs pixel data from the reference memories 4 and 5 to the half pixel interpolation filters 17 and 18, respectively. The forward and backward prediction values FRA and FRB output from the half-pixel interpolation filters 17 and 18, and the averaging unit 1 of these prediction values FRA and FRB
The bidirectional prediction value FRC, which is the average value calculation result of 9 is supplied to the inter-frame prediction selection circuit 7 in parallel. The inter-frame prediction selection circuit 7 compares and evaluates each of the forward, backward and bidirectional prediction values FRA, FRB and FRC with the luminance signal Y of the current macroblock MBI and selects the most similar prediction value. The selected predicted value S in the selector 12
The FR outputs the evaluation data E in that case to the terminal T3. The selector 12 outputs the prediction value SFR supplied from the inter-frame prediction selection circuit 7 from the terminal T2 as the data DP.

When the current frame FI is a P frame, invalid pixel data is stored in the reference memory 5. However, by always selecting the forward value FRA by the inter-frame prediction / selection circuit 7, similar to the B frame. It can be processed. Also, I
In the case of a frame, invalid pixel data is stored in both the reference memories 4 and 5, but since it is always determined to be intra-frame coding by the coding type determination in the latter stage as described above, for example, inter-frame prediction selection Circuit 7 has forward value FRA
If is selected, the same processing can be performed.

Next, referring to FIG. 13 showing the configuration of the half pixel interpolation filters 17 and 18 in blocks, the half pixel interpolation filters 17 and 18 are composed of a delay circuit 61 for delaying 9 clocks and an averaging device. M171, M172 and selector S1
71, S172 and 1-clock delay devices D171 to D17
3 and 3.

The operation will be described with reference to FIGS. 13, 8 and 10 and FIG. 14 showing an operation time chart. First, the vertical half-pixel interpolation filter is followed by the horizontal half-pixel interpolation filter. It is configured to apply
Pixel data A (a0-a0) stored in the reference memory 4 shown in FIG.
a80) is input with 1 pixel data / 1 clock.

First, the half-pixel interpolation in the vertical direction is performed by the delay circuit 6
The average of the output data AB of 1 and the input pixel A is averaged by the averager M1.
The pixel data at the position corresponding to c3 or c4 shown in FIG. The selector S17 determines the pixel data vy
If 0 is 1, the output of the averager M171 is selected, and if 0, the output AB of the delay circuit 61, that is, pixel data one pixel above in the vertical direction from the input pixel A is taken. The average (a0 + a9) / 2 of the data a9 input at the time t0 and the data a0 on one pixel thereof is calculated, and the data vy is calculated at the time t1.
If 0 is 1, the average is (a0 + a9) / 2, and if 0 is a0
Is written in the delay device D171. Next, in half-pixel interpolation in the horizontal direction, the average of the output AC of the delay device D171 delayed by one clock from the input of the selector S171 and one clock before, that is, the input of the delay device D172 which is the output one pixel left is averaged. The half-pixel interpolation in the horizontal direction corresponding to c1, c2 or c5 in FIG. And the data vx0
If is 1, the output of the averager M172 is selected, and if 0, the output AE of the delay device D172 is selected. At time t2,
When the data vx0 is 0, the data a0 (vy0 is 0) or (a0 + a9) / 2 (vy) which is the output data AE.
If 0 is 1) and the data vx0 is 1, the averager M172 outputs (a0 + a1) / 2 (vy0 is 0).
Alternatively, (a0 + a9 + a1 + a10) / 4 (vy0 is 1) is selected and is output to the DFF 210 as the write output FR at time t3.

By switching the selector in this way, half-pixel interpolation can be realized. The predicted output value FR is 9 ×
It consists of 9 pixels, of which the upper left 8 × 8 pixels (from t3
(t10, t12 to t19, etc.) are the prediction blocks in the MPEG mode.

[0041]

The conventional motion compensation circuit for moving picture coding described above is provided with two half-pixel interpolation filters for the MPEG system, one for the forward direction and the other for the backward direction. 261
Since the loop filter for the system is provided independently, M
In the PEG mode, the loop filter is not used, and the H.264 standard is not used. In the case of the 261 mode, the above two half-pixel interpolation filters are not used, and there is a drawback that the circuit elements such as DFF, averaging device, selector, etc. which constitute these circuits are not effectively used.

An object of the present invention is to provide a motion compensating circuit for moving picture coding, which can realize the same function as the conventional one and can reduce the circuit scale.

[0043]

SUMMARY OF THE INVENTION A motion compensation circuit for moving picture coding according to the present invention comprises a predetermined vertical and horizontal search range for input image data and past image data one frame before the input image data. To detect the motion vector and compare the motion vector with the first and second encoding methods predetermined by the switching control signal.
And a motion compensating circuit of a motion picture coding apparatus, comprising: coding filter means for performing second filter processing to generate reference image data, and coding difference data between the input image data and the reference image data. The encoding filter means delays the input data by the first and second delay times corresponding to the predetermined first and second pixel clock numbers, respectively, and the input data by one pixel. A plurality of unit delay means for delaying by a delay time corresponding to the clock;
A plurality of averaging means for calculating the average of one input data,
In response to the supply of the switching control signal, the first and second
A plurality of selecting means for connecting the first and second delay means, the plurality of unit delay means, and the plurality of averaging means in predetermined first and second combinations respectively corresponding to the filtering processing It is configured with.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 9 are designated by common reference characters / numerals, the embodiment of this invention shown in FIG. The moving picture coding motion compensation circuit 109C of FIG. 1 includes an address generator 1, a frame memory 2 and an address generator 3 which are common to the conventional ones.
In addition to the reference memories 4 and 5 and the inter-frame prediction selection circuit 7, the loop filter 16 and the half pixel interpolation filter 1
Instead of the averaging circuit 7 and the averaging circuit 19 and the selector 12, there is provided an encoding filter circuit 6 in which the functions of the respective components 12, 16 to 19 are combined.

Referring to FIG. 2 which shows the coding filter circuit 6 in blocks, this coding filter circuit 6 has the same 9 clocks as the components of the conventional loop filter 16 and half-pixel interpolation filters 17 and 18. 8-clock delay circuits 61 and 62, selectors S61 to S70, 1-clock delay units D61 to D67 including DFF, an adder and 1 /
And two averaging devices M61 to M65.

Next, the operation of the present embodiment will be described with reference to FIGS. 1 and 2. The parts other than the coding filter circuit 6 are common to the first and second moving picture part coding circuits described above. Since the operation is the same as that of the present invention, the description thereof will be omitted so that it is not redundant except for those related to the present invention. In the moving image encoding circuit of this embodiment, the filter circuit 6 is switched to the H.264 signal by switching the selectors S61 to S70 in the encoding filter circuit 6. The H.26D mode and the MPEG mode are switched to the corresponding loop filter and half-pixel interpolation filter, respectively. The operation of each of the 261 mode and the MPEG mode is switched.

First, H. In the H.261 mode, each of the selectors S61 to S68 of the encoding filter circuit 6 selects the contact H side, and the pixel data A and the invalid pixel data output from the reference memories 4 and 5 to the terminals T62 and T61, respectively. Supply each. As a result, the predicted value DPL which is the output of the loop filter is output to the terminal T65. At this time, the outputs of the terminals T63 and T64 are invalid, but the inter-frame prediction selection circuit 7 in the subsequent stage always outputs the terminal T65.
There is no problem because the output of is selected.

Referring to FIG. 2, these selectors S61
To S68 are the delay circuit 61, the delay device D67, the delay device D67, the averaging device M62, which correspond to the contact H, respectively.
The delay device D63, the delay circuit 62, the averaging device M64, and the delay device D61 are selected. Further, each of the selectors S69 and S70 controls so as to select one of the other two contacts H1 and H2 without selecting the contact M corresponding to the output of the delay devices D66 and D67. It will be described below that the operation of the loop filter circuit shown in FIG. 11 can be realized under this condition.

Referring to FIG. 6 together, first, the realization of the filter coefficient f (1/4, 2/4, 1/4) in the vertical direction will be described. The above-mentioned selectors S61 and S66 to S70 will be described.
Selection result, delay circuit 61, delay device D61, delay circuit 6
2, averaging device M64, delay device D65, averaging device M65,
The circuit including the selector S69 is a delay circuit 61, a delay device D161, a delay circuit 62, and an averaging device M1 shown in FIG.
The circuit is the same as the circuit including 61, delay device D162, averaging device M162, and selector S161. Therefore, if the selector S69 is controlled in the same manner as the selector S161 of FIG. 11, the vertical filter coefficient f is output to the output of the delay device D67.

Next, the realization of the filter coefficient e in the horizontal direction will be described. The above-mentioned selectors S62 to S65, S7.
As a result of selecting 0, the circuit including the delay devices D67, D62, D63, the averaging device M62, the delay device D64, the averaging device M63, and the selector S63 is the delay device D163 of FIG.
D164, D165, averaging device M163, delay device D16
5, the same circuit as the averager M164 and the selector S162. Therefore, the selector S70 is shown in FIG.
If the control is performed in the same manner as the selector S162 of 1, the horizontal filter coefficient e is output. Therefore, the terminal T65 is shown in FIG.
The same predicted value DPL as that of the loop filter 16 can be output.

Next, in the MPEG mode, each of the selectors S61 to S68 of the encoding filter circuit 6 selects the contact M side, and the pixels output from the reference memories 4 and 5 to the terminals T62 and T61, respectively. Data A and B are supplied respectively. As a result, terminals T63, T64, T6
Predicted values F in the backward, bidirectional, and forward directions respectively in 5
RA, FRC and FRC are output in parallel.

Referring again to FIG. 2, these selectors S
61 and S63 to S68 respectively select the terminal T61, the delay device D62, the delay device D63, the delay device D67, the delay circuit 61, the delay circuit 61, and the delay device D66 corresponding to the contact M, respectively. In addition, selectors S62 and S69
Controls the contacts H corresponding to the outputs of the delay devices D67 and D61 so as to select either one of the other two contacts. It will be described below that the operation of the two half-pixel interpolation filter circuits shown in FIG. 9 can be realized under this condition.

First, the half-pixel interpolation filter operation for forward prediction will be described. The selection result of the delay circuit 61 of the selector S66 described above, the delay circuit 61, and the averaging device M6.
4, the circuit including the selector S67 is the same as the circuit including the delay circuit 61, the averager M171, and the selector S171 in FIG. Therefore, as in the conventional case, the selector S
It is obvious that half-pixel interpolation in the vertical direction is possible if 67 is controlled by the forward motion vector vy0. Similarly, as a result of the selection of the delay device D66 of the selector S68 and the non-selection of the delay device D61 of the selector S69, the circuit including the delay devices D65, D66, the averaging device M65 and the selector S69 is shown in FIG.
The delay circuit D171, D172, the averaging device M172, and the selector S172 are the same circuits. Therefore, as in the conventional case, the selector S69 is set to the forward motion vector vx0.
If it is controlled by, half-pixel interpolation in the horizontal direction becomes possible. The selection result of the delay device D67 of the selector S70 indicates that the terminal T65
Is the output data FR of the forward prediction half-pixel interpolation filter.
A is output.

Next, the backward prediction half-pixel interpolation filter operation will be described. As a result of the selection at the terminal T61 of the selector S61, the delay device D61 and the subsequent delay circuit 62 perform the same operation as the delay circuit 61 of FIG. As a result of the non-selection of the delay device D67 of the selector S62, the circuit composed of the averaging device M61 and the selector S62 becomes the same as the circuit composed of the averaging device M171 and the selector S171 of FIG. Therefore, as in the conventional case, the selector S62 is set to the backward motion vector v
If controlled by y0, half-pixel interpolation in the vertical direction is possible. Similarly, the selection result of the delay device D62 of the selector S63,
Delay devices D62, D68, averaging device M62, selector S6
The circuit composed of 4 has delay circuits D171, D172 and
The circuit is the same as that of the averaging device M172 and the selector S172. Therefore, as in the conventional case, if the selector S64 is controlled by the backward motion vector vx0, half-pixel interpolation in the horizontal direction becomes possible. Therefore, the output data FRB of the backward prediction half-pixel interpolation filter is output to the terminal T63.

As a result of the selection of the delay device D67 of the selector S65, the output forward prediction value F of each of the delay devices D67 and D64 is obtained.
RA and the backward prediction value FRB are averaged by the averaging device M63, and the bidirectional prediction value FRC is output to the terminal T64.

Next, referring to FIG. 3, which is a block diagram of the coding filter circuit 6A of the second embodiment of the present invention, the same components as those in FIG. 2 are designated by common reference characters / numerals. The difference between the coding filter circuit 6A of this embodiment and the coding filter circuit 6 of the first embodiment is that the selector S6 is used.
2, S63, S65, S68 to S70 are replaced with selectors S71 to S78 inserted at different positions, and H.S. Two
Of the five averagers M61 to M65 for the 61-mode loop filter, the averager M6 is used in the first embodiment.
Whereas averagers M62 to M65 other than 1 are used,
This embodiment is to use M61 to M64 other than the averager M65.

H. In the H.261 mode, the selectors S61, S64, S66, S67, S of the encoding filter circuit 6A are
Each of 71 to S78 selects the contact H side.

Referring again to FIG. 3, the selector S61,
S64, S66, S67, S71, S72, S74, S
75 and S77 respectively include a delay circuit 61, an averaging device M62, a delay circuit 62, an averaging device M64, and a delay device D6.
1, D65, D66, D62, and D63 are respectively selected. Further, the selector S73 controls so as to select either the delay device D61 or the averaging device M61, and the selector S78 controls so as to select either the delay device D63 or the averaging device M61.

As a result, the delay circuit 61, the delay device D61,
The vertical filter circuit including the delay circuit 62, the averaging device M64, the delay device D65, the averaging device M61, and the selector S73 is the delay circuit 61, the delay device D161, the delay circuit 62, the averaging device M161, and the delay device D162 of FIG. , Averager M
The circuit is the same as the circuit including 162 and the selector S161.
Further, the horizontal filter circuit including the delay devices D62 and D66, the averaging device M62, the delay device D64, the averaging device M63, and the selector S78 is the delay devices D163, D164, and D164 of FIG.
The circuit is the same as the circuit including D165, averaging device M163, delay device D165, averaging device M164, and selector S162.

Therefore, the same predicted value DPL as that of the loop filter of FIG. 11 can be output to the terminal T65.

In the MPEG mode, the selectors S61, S64, S66, S67, S7 of the coding filter circuit 6A are used.
Each of 1 to S78 selects the contact M side.

Referring again to FIG. 3, these selectors S
61, S66, S71, S72, S74, S75, S7
7 and S78 are terminals T6 corresponding to the contacts M, respectively.
1, delay circuit 61, delay circuit 62, terminal T61, delay devices D62, D65, D67, D68 are selected. Further, the selector S73 controls so that the delay device D61 is not selected.

As a result, the delay circuit 61 and the averaging device M6
4, the circuit including the selector S67 is the same as the circuit including the delay circuit 61, the averager M171, and the selector S171 in FIG. Similarly, the circuit including the delay devices D65 and D66, the averaging device M65, and the selector S76 is the same as the circuit including the delay devices D171, D172, the averaging device M172, and the selector S172 in FIG. As a result, similarly to the first embodiment, the vertical / horizontal half-pixel interpolation operation for forward prediction becomes possible.

Further, similarly to the first embodiment, the selector S6
As a result of the selection of the terminal T61 of No. 1, the delay device D61 and the delay circuit 62 subsequent thereto operate the same as the delay circuit 61 of FIG. 13, and the selectors S72 and S71 select the terminal T61 and the delay circuit 62, respectively. Since the selector S73 selects either the delay circuit 62 or the averaging device M61, the circuit including the averaging device M61 and the selector S73 is the averaging device M171 and the selector S17 shown in FIG.
It is the same as the circuit consisting of 1. Similarly, since the selector S74 selects the delay device D62, the delay devices D62 and D6 are selected.
3, the circuit composed of the averager M62 and the selector S64 is
Delay devices D171, D172 and averaging device M17 of FIG.
2, the circuit is the same as the circuit including the selector S172. As a result, similarly to the first embodiment, the vertical / horizontal half-pixel interpolation operation for backward prediction can be performed.

Further, as a result of the selection of the delay device D67 of the selector S77, the forward and backward prediction values FRA and FRB which are output data of the delay devices D67 and D64 are averaged by the averaging device M6.
3 and average to generate the bidirectional predicted value FRC, and the terminal T6
4 is output.

In the conventional motion compensation circuit shown in FIG. 9, the 9-clock and 8-clock delay circuits are 9 delay units and 8 delay units, respectively.
While the loop filter and the two half-pixel interpolation filters each include 47 delay units, 9 averaging units, and 6 selectors, in the first embodiment, 24 delay units, averaging units are included. There are 5 rectifiers and 10 selectors. In the second embodiment, only 12 selectors are added to the first embodiment. Therefore, the number of delay circuits and averaging circuits having a large circuit size is reduced by half, and the number of selectors having a small circuit size is approximately doubled as compared with the conventional circuit.

[0067]

As described above, in the motion compensation circuit for moving picture coding according to the present invention, the coding filter means includes a plurality of unit delay means, a plurality of averaging means, and the first and second means.
By providing the plurality of unit delay means and the plurality of selecting means for connecting the plurality of unit delay means and the averaging means in the first and second combinations respectively corresponding to the filter processing of 1, the delay means and the averaging means having a large circuit scale are provided. The first and second
Since it can be commonly used for the filter processing of 1, the number of the delay means and the averaging means can be reduced by half as compared with the conventional circuit, and the overall circuit scale can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a motion compensation circuit for video encoding according to the present invention.

FIG. 2 is a block diagram of a coding filter circuit which constitutes a motion compensation circuit for moving picture coding according to the present embodiment.

FIG. 3 is a block diagram of an encoding filter circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a first moving image encoding circuit.

5 is an explanatory diagram of an operation concept of the motion vector detection circuit shown in FIG.

FIG. 6 is an explanatory diagram of an operation concept of the loop filter shown in FIG.

FIG. 7 is a block diagram showing an example of a second moving image coding circuit.

8 is an explanatory view of the concept of the half-pixel interpolation filter shown in FIG.

FIG. 9 is a block diagram showing an example of a conventional motion compensation circuit for video encoding.

10 is an explanatory diagram of a concept of a reading order of the reference memory shown in FIG.

11 is a block diagram of the loop filter circuit shown in FIG. 9. FIG.

FIG. 12 is a time chart showing the operation of the loop filter circuit.

13 is a block diagram of the half-pixel interpolation filter circuit shown in FIG.

FIG. 14 is a time chart showing the operation of the half-pixel interpolation filter circuit.

[Explanation of symbols]

1,3 Address generator 2,108 Frame memory 4,5 Reference memory 6,6A Encoding filter circuit 7,115 Inter-frame prediction selection circuit 12,113, S61 to S78, S161, S162,
S171, S172, selector 16,111 loop filter 17,18 half-pixel interpolation filter 19, M61 to M65, M161 to M164, M17
1, M172 Averager 61, 62 Delay circuit 101, 107 Adder 102 DCT 103 Quantization circuit 104 Huffman coding circuit 105 Inverse quantization circuit 106 IDCT 109, 109A, 109B, 109C Motion compensation circuit 110, 110A Motion vector detection Circuit 112 Encoding type determination circuit D61 to D67, D161 to D166, D171 to D1
73 Delay device

Claims (2)

[Claims] 1. A motion vector is detected by comparing input image data with past image data one frame before the input image data within a predetermined vertical and horizontal search range, and this motion vector is switched and controlled. The input image data and the reference image data are provided with an encoding filter means for generating reference image data by performing first and second filtering processes respectively adapted to first and second encoding methods predetermined by a signal. In the motion compensation circuit of the moving picture coding apparatus for coding the difference data between the first and second pixel clock numbers, the coding filter means corresponds to predetermined first and second pixel clock numbers. First and second delay means for delaying each by a time, a plurality of unit delay means for delaying input data by a delay time corresponding to one pixel clock, and two input data A plurality of averaging means for calculating the average, the switching control of the first in response to the supply of the signal and the second
A plurality of selecting means for connecting the first and second delay means, the plurality of unit delay means, and the plurality of averaging means in predetermined first and second combinations respectively corresponding to the filtering processing A motion compensation circuit for video coding, comprising: 2. The first filter processing comprises: a first delay means for delaying input data by 9 pixel clocks; a first averaging means for averaging the input and output of the first delay means; A first selection unit that selects one of the output of the first delay unit and the output of the first averaging unit, and the output of the first selection unit is delayed by one pixel clock, and the first output unit is delayed. A first filter including a first unit delay means for generating a processed output; a second unit delay means for delaying the first processed output; and a second unit for averaging the inputs and outputs of the second unit delay means. 2 averaging means, a second selecting means for selecting one of the output of the second unit delay means and the output of the second averaging means, and the output of the second selecting means. Delay the first
And a second filter including a third unit delay means for generating output data of the filter processing of (1), and data of a block consisting of nine pixels in each of the horizontal direction and the vertical direction is input for each pixel. A first half-pixel interpolation process for the block in response to the control of the first and second selecting means;
And a second half-pixel interpolation filter, wherein the second filtering process includes the first delay unit, a fourth unit delay unit that delays an output of the first delay unit, and a second unit delay unit. The second delay means for delaying the output of the unit delay means of 4 by 8 pixel clocks, and the third averaging means for averaging the output of the second delay means and the input of the first delay means. A fifth unit delay means for delaying the output of the third averaging means, and a fourth averaging means for averaging the output of the fifth unit delay means and the output of the fourth unit delay means. And a third selecting means for selecting one of the output of the fourth averaging means and the output of the fourth unit delay means, and the second selecting means for delaying the output of the third selecting means. A third filter including fifth unit delay means for generating a processing output; and the second processing The sixth and seventh unit delay means for delaying the force, the fifth averaging means for averaging the second processing output and the output of the seventh unit delay means, and the fifth averaging means. Unit delay means for delaying the output of the second unit delay means, and any one of the output of the eighth unit delay means and the output of the seventh unit delay means is selected to output the second filter processing output. Forming a loop filter for weighting predetermined vertical / horizontal filter coefficients to a sub-block consisting of 8 pixels in each of the horizontal and vertical directions of the block The motion compensation circuit for moving picture coding according to claim 1.