JPH08222704A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To realize a semiconductor integrated circuit, which reduces effectively an electromagnetic radiation generated in the circuit, and is resistant also to noise. CONSTITUTION: A semiconductor integrated circuit is provided with an S/P conversion circuit 11, a P/S conversion circuit 13 and a clock (n) frequency dividing circuit 14, which are such a high-speed operating circuit part as a serial signal processing part which requires a high-speed operation, and a digital signal processing circuit 12, which is such a low-speed operating circuit part as a parallel signal processing part which is allowed an operation at a speed slower than that of this serial signal processing part. The capacitance (parasitic capacitance) of a transistor constituting the circuit 12 is increased, whereby a semiconductor integrated circuit is constituted of elements, whose rise and fall times are slow, and inhibits the generation of an electromagnetic radiation from the circuit 12 which is the low-speed operating circuit part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for reducing electromagnetic radiation, and more particularly to a semiconductor integrated circuit for reducing electromagnetic radiation generated by turning on / off a transistor element.

[0002]

2. Description of the Related Art With the recent operation of semiconductor integrated circuits, transistors inside the semiconductor integrated circuits turn on at high speed.
When it is turned off, its high frequency component becomes a source of electromagnetic radiation when it rises or falls, and this electromagnetic radiation causes electromagnetic interference to surrounding circuits and equipment, and causes deterioration of these performances and malfunctions. Has become.

For example, FIG. 9 shows an example of a circuit that performs serial-parallel conversion of a serial data signal once and performs signal processing. The S / P conversion circuit 11 is a serial data signal input at a frequency f from a data input terminal IN. Is parallel-converted into n columns by the output of the clock n frequency dividing circuit 14 that divides the clock input from the clock input terminal C by n, and f
The data 1 to n of the n-column having the frequency of / n are output. The digital signal processing circuit 12 executes a predetermined process on each of the n columns of data. Further, the P / S conversion circuit 13 serially converts the data of the n columns processed by the digital signal processing circuit 12, and outputs it as data of the frequency f from the data output terminal out.

In such a circuit, in order to speed up the signal processing, a semiconductor element, such as an MO, which constitutes each circuit, is formed.
In the S transistor, all MOS transistors are designed so that the gate is driven at the maximum operating frequency. Therefore, the rise time and fall time of the MOS transistor of each circuit are extremely short, and at this time, the above-mentioned high frequency is generated, which causes electromagnetic radiation. In order to reduce such electromagnetic radiation, conventionally, for example, JP-A-64-15820 or JP-A-3-
There is one described in Japanese Patent No. 129416. In the former case, a clock having a frequency lower than the clock frequency required in the circuit is input to the circuit, and the frequency is generated in the circuit to reduce electromagnetic radiation due to the frequency clock in the input section. It is a thing.
In the latter, the sine wave is input to the input section, and this sine wave is converted into a rectangular wave inside the circuit to prevent the rectangular section from being input at the input section, reducing electromagnetic radiation at the input section. To do.

Although the electromagnetic radiation (EMI) has been described above, a semiconductor integrated circuit in which a transistor is turned on and off at a high speed is weak with respect to the opposite electromagnetic susceptibility (EMS) and immunity. That is, turning on and off at high speed means that the MOS transistor reacts even with a small amount of noise and easily causes a malfunction. For example, in FIG.
Is an example of a circuit that performs serial-parallel conversion of a serial data signal and performs signal processing. The S / P conversion circuit 11 converts a serial data signal input from the data input terminal IN at a frequency f into a clock input terminal. The clock input from C is divided into n by the output of the clock n frequency dividing circuit 14 that divides the clock by n, and the n columns of data 1 to n having the frequency of f / n are output. Digital signal processing circuit 12
Performs a predetermined process on each of the n columns of data. Further, the P / S conversion circuit 13 serial-converts the data of the n columns processed by the digital signal processing circuit 12, and outputs it again as the data of the frequency f from the data output terminal OUT. Further, the P / S conversion circuit 13 has an output control signal input terminal S, and when receiving the control signal, it stops outputting data from the output terminal OUT.

In such a circuit, in order to speed up signal processing, a semiconductor element, such as an MO, which constitutes each circuit, is formed.
In the S transistor, all MOS transistors are designed so that the gate is driven at the maximum operating frequency. Therefore, the rise time and fall time of the MOS transistor of each circuit are extremely short, the cutoff frequency of the element is high, and it becomes easy to react to noise. In particular, a place that is an external terminal such as the control input terminal S is easily affected by noise and causes a malfunction.

[0007]

However, although the technique described in the above-mentioned publication can prevent the electromagnetic radiation at the input portion where the electromagnetic radiation is remarkable, the operation of the elements inside the circuit still remains. Since high-speed operation is performed, it is difficult to reduce electromagnetic radiation generated inside the circuit. Further, in these publications, since a frequency conversion circuit and a waveform shaping circuit are required for the integrated circuit, the circuit configuration of the integrated circuit becomes large, which is not preferable for realizing a compact and high-density semiconductor integrated circuit.
The second problem is that it is vulnerable to external noise and easily malfunctions. The reason for this is that the cutoff frequency of the transistor is high, so that it also reacts to high frequency noise.

An object of the present invention is to provide a semiconductor integrated circuit capable of effectively reducing electromagnetic radiation in the circuit section and resistant to noise.

[0009]

A semiconductor integrated circuit according to the present invention has a structure including a high-speed operation circuit section that requires high-speed operation and a low-speed operation circuit section that is allowed to operate at a slower speed. The low-speed operation circuit unit is composed of elements having a slow rise time and a slow fall time.

For example, the element forming the low speed operation circuit section is composed of a MOS transistor having a channel length longer than that of the MOS transistor of the high speed operation circuit section. Further, the bias voltage supplied to the elements forming the low speed operation circuit section is set to be lower than the bias voltage supplied to the elements forming the high speed operation circuit section. Further, the element forming the low-speed operation circuit section is formed of a MOS transistor in which the capacitance (parasitic capacitance) of the output section of the MOS transistor in the high-speed operation circuit section is increased.

[0011]

In general, in an element such as a MOS transistor or a bipolar transistor, the amount of electromagnetic radiation from the element is inversely proportional to the rise time and fall time of the signal, and the faster it is, the more it increases. Therefore, a circuit part with a high frequency must be realized by a gate with a fast rise time or a fall time, but a circuit part with a low frequency must increase the channel length of the transistor, lower the bias voltage, or reduce the output voltage. By increasing the capacitance (parasitic capacitance) of the element and forming it by an element whose rise time and fall time are delayed, at least electromagnetic radiation in this circuit portion is reduced. Furthermore, since the cut-off frequency of the element is low, the semiconductor integrated circuit has a strong immunity and does not malfunction due to difficulty in reacting to noise.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

First, the first embodiment of the present invention is applied to a circuit for performing signal processing by once serial-parallel converting a data signal, as in the conventional example described above. That is, as shown in FIG. 9, the S / P conversion circuit 11 has a data signal input terminal IN.
From the serial data signal input at the frequency f to n columns, and the data of n columns of the frequency f / n
Output n. The clock n frequency dividing circuit 14 frequency-divides the clock signal input from the clock input terminal C by n,
It is input to the S / P conversion circuit 11 to enable the parallel conversion described above. The digital signal processing circuit 12 executes a predetermined process on each of the n columns of data. Also, P
The / S conversion circuit 13 serially converts the data of the n columns processed by the digital signal processing circuit 12, and outputs the data of the frequency f again from the data output terminal OUT.

FIG. 1 is a circuit diagram of the circuit of FIG.
FIG. 10 is a block diagram of a configuration when it is configured as an integrated circuit on 00. The elements of the short channel element region 101 that form the S / P conversion circuit 11, the P / S conversion circuit 13, and the clock n frequency dividing circuit (1 / n) 14 have a short rise time and a short fall time corresponding to the frequency f. It is composed of a MOS transistor having a short channel length so that a high speed operation can be performed in time. On the other hand, since the elements in the long channel element region 102 forming the digital signal processing circuit 13 operate at a relatively low frequency of the frequency f / n, the rise time and fall time are long and the channel length is long. It is composed of MOS transistors. Further, a bias circuit 15 for supplying a bias to each circuit is provided.

Therefore, when this integrated circuit is driven,
S / P conversion circuit 11, P / S conversion circuit 13, clock n
In the frequency divider circuit 14, when a signal or clock of frequency f is input, the channel lengths of the MOS transistors forming them are short, so that the rise time and fall time are about 1 nS as shown in FIG. The operation is performed at a high speed. On the other hand, in the digital signal processing circuit 12, since the channel length of the MOS transistor is long,
For example, when signals of the same frequency f are input,
As in (b), the rise time and fall time are 3
The operation is performed in a slow state of about nS. In this case, since the digital signal processing circuit 12 operates at the frequency f / n, the operation is not adversely affected even when the rise time and the fall time are delayed.

Thus, in this integrated circuit, the digital signal processing circuit 12, which occupies most of the circuit, is composed of MOS transistors having a long channel length, so that the rising time and the rising time of the MOS transistors are not affected by the operation. The fall time can be delayed. Then, as described above, the amount of electromagnetic radiation accompanying the operation of the MOS transistor is inversely proportional to the speeds of the rising time and the falling time, so that the electromagnetic radiation generated in the digital signal processing circuit 12 can be reduced. Becomes In this example, the rise time and the fall time are delayed from 1 nS to 3 nS, so that the amount of electromagnetic radiation is reduced accordingly.

Therefore, the other S / P conversion circuits 11, P
In the / S conversion circuit 13 and the clock n frequency dividing circuit 14, even if electromagnetic radiation similar to the conventional one is generated, since these circuits occupy a small proportion in the integrated circuit, the electromagnetic radiation of the integrated circuit as a whole is significantly reduced. Can be reduced to.

Next, a second embodiment of the present invention will be described.

FIG. 3 shows a second embodiment of the present invention.
FIG. 10 is a block configuration diagram corresponding to FIG. 1 of the first embodiment when the present invention is applied to the circuit of FIG. 9. Here, S /
The P conversion circuit 11, the digital signal processing circuit 12, the P / S conversion circuit 13, and the clock n frequency dividing circuit (1 / n) 14 are elements having the same configuration, for example, M having the same channel length.
Although it is composed of an OS transistor, a high voltage bias circuit 15A and a low voltage bias circuit 15B are provided, and the S / P conversion circuit 11, the P / S conversion circuit 13, and the clock n frequency dividing circuit 14 have a frequency f. Corresponding to, the high voltage bias circuit 15A applies a high voltage as each bias of the gate and drain of the MOS transistor so that the high speed operation can be performed with the short rise time and the fall time. On the other hand, the digital signal processing circuit 12
Since the operation is performed at a relatively low frequency f / n,
A low voltage is applied by the low voltage bias circuit 15B as each bias of the gate and the drain of the MOS transistor so that the rising time and the falling time become long.

Therefore, when this integrated circuit is driven,
S / P conversion circuit 11, P / S conversion circuit 13, clock n
In the frequency dividing circuit 14, when a signal or clock of the frequency f is input, a high-voltage bias is supplied to the MOS transistors forming them, so that FIG.
As in (a), the rise time and fall time are 1
The operation is performed in a fast state of about nS. On the other hand, in the digital signal processing circuit 12, since a low voltage bias is supplied to the MOS transistor, for example, when a signal of the same frequency f is input, as shown in FIG. Then, the operation is performed in a state in which the fall time is about 3 nS.

As a result, also in the second embodiment, in the digital signal processing circuit 12 which occupies most of the circuit,
The rise time and fall time of the MOS transistor can be delayed without being affected by the operation. Therefore, it is possible to reduce the electromagnetic radiation generated in the digital signal processing circuit 12, which occupies most of the circuit. Therefore, the other S / P conversion circuit 11, P / S conversion circuit 13, clock n frequency dividing circuit 1
In No. 4, even if electromagnetic radiation similar to the conventional one is generated, since the ratio of these circuits to the integrated circuit is small, the electromagnetic radiation of the integrated circuit as a whole can be significantly reduced.

Here, in the first and second embodiments, an example in which the present invention is applied to an integrated circuit for performing digital signal processing of serial-parallel conversion system is shown. However, a circuit having a high operation speed and an operation speed are shown. The present invention can be applied in the same manner as in the above-mentioned respective embodiments as long as it is an integrated circuit in which slow circuits are mixed.

In each of the above embodiments, a MOS transistor is used as an element for performing the operation. In particular, the structure of the second embodiment in which biases are supplied to the circuit is different from the circuit using a bipolar transistor as an element. Can be similarly applied.

Next, a third embodiment of the present invention will be described.

FIG. 4 shows a third embodiment of the present invention.
FIG. 10 is a block configuration diagram corresponding to FIG. 1 of the first embodiment when the present invention is applied to the circuit of FIG. 9.

The S / P conversion circuit 11, the P / S conversion circuit 13, and the clock n frequency dividing circuit (1 / n) 14 are formed.
The element in the region 101 'having a small capacitance (parasitic capacitance) has a cutoff frequency with a small output capacitance (parasitic capacitance) so that high speed operation can be performed with a short rise time and a fall time corresponding to the frequency f. High MO
It is composed of S transistors. On the other hand, the capacitance (parasitic capacitance) that constitutes the digital signal processing circuit 12
Since the element in the region 102 'having a large frequency is operated at a relatively low frequency f / n, the output capacitance (parasitic capacitance) in which the rise time and the fall time are long
The MOS transistor has a high cutoff frequency and a low cutoff frequency. Further, a bias circuit 15 for supplying a bias to each circuit is provided.

Therefore, when this integrated circuit is driven,
S / P conversion circuit 11, P / S conversion circuit 13, clock n
In the frequency divider circuit 14, when a signal or clock of the frequency f is input, the capacitance (parasitic capacitance) of the output of the MOS transistors forming them is small.
As shown in FIG. 5A, the operation is performed in a state where the rise time and the fall time are about 1 nS, which is fast. On the other hand, in the digital signal processing circuit 12, since the output capacitance (parasitic capacitance) of the MOS transistor is large, for example, when a signal of the same frequency f is input, FIG.
As in (b), the rise time and fall time are 5
The operation is performed in a slow state of about nS. In this case, since the digital signal processing circuit 12 operates at the frequency f / n, the operation is not adversely affected even when the rise time and the fall time are delayed.

Thus, in this integrated circuit, the digital signal processing circuit 12, which occupies most of the circuit, is composed of MOS transistors having a large output capacitance (parasitic capacitance), so that the operation is not affected by the operation.
The rise time and fall time in the transistor can be slow.

As described above, the amount of electromagnetic radiation accompanying the operation of the MOS transistor is inversely proportional to the speed of the rise time and the fall time, so the electromagnetic radiation generated in the digital signal processing circuit 12 is reduced. It becomes possible. In this example, the rise time and fall time are delayed from 1 nS to 5 nS,
The following calculation shows that the amount of electromagnetic radiation is reduced.

The trapezoidal wave equation is expressed by the following equation 1.

[0031]

[Equation 1] Where I: peak-to-peak crest value d: duty cycle tr: rise time, fall time
T: Period n: Represented by the order of higher order wave.

FIG. 5A shows d: 0.5 (50%) tr.
= 1nS f = 10MHz T = 100nS.

This eleventh harmonic is expressed by the following mathematical formula 2.

[0034]

[Equation 2] FIG. 5B shows d: 0.5 (50%) tr = 5 nS f.
= 10 MHz T = 100 nS The 11th harmonic is expressed by the following mathematical formula 3.

[0035]

(Equation 3) Equation 3 shows that 58% (4.7 dB) radiation is reduced relative to Equation 2.

FIG. 6 shows a graph of the trapezoidal wave envelope curve of FIGS. 5 (a) and 5 (b). From this figure, it can be seen that the higher the higher-order wave with a particularly high frequency, the smaller the amount of electromagnetic radiation with a slower rise and fall time.

Therefore, the other S / P conversion circuits 11, P
In the / S conversion circuit 13 and the clock frequency dividing circuit 14,
Even if electromagnetic radiation similar to the conventional one is generated, since the ratio of these circuits to the integrated circuit is small, the electromagnetic radiation of the integrated circuit as a whole can be significantly reduced.

FIG. 7 is a block diagram showing a fourth embodiment of the present invention. In FIG. 7, the output of the P / S conversion circuit 13 is stopped or output according to a signal from the output control signal input terminal S. The transistor forming the output control signal input terminal S is less likely to react to noise by using an element having a low cutoff frequency and a large capacitance (parasitic capacitance). This means that immunity is improved because malfunctions due to noise are reduced.

FIG. 8 shows an example of locations in a semiconductor in which a high frequency element and a low frequency element according to the present invention coexist. The high frequency signal element is arranged as close as possible to the high frequency signal input / output terminal (pin) to minimize the current loop created by the high frequency signal. This makes it possible to reduce the radiation from the high frequency signal, which is the biggest problem of electromagnetic radiation. In FIG. 8, 6
01 is an input / output pin, and 602 is a wire.

As described above, the third and fourth embodiments also show an example in which the present invention is applied to an integrated circuit for performing digital signal processing of the serial-parallel conversion system. However, an integrated circuit in which circuits with high operating speed are mixed is shown. As long as it is a circuit, the present invention can be applied similarly to the third and fourth embodiments.

Further, the third and fourth embodiments show an example in which a MOS transistor is used as an element for performing the operation,
It can also be applied to other integrated circuits such as bipolar transistors.

[0042]

As described above, according to the present invention, a low speed operation is provided in a structure including a high speed operation circuit section that requires high speed operation and a low speed operation circuit section that is allowed to operate at a slower speed. By configuring the circuit section with elements with slow rise and fall times, the circuit section that requires high-speed operation must be realized with a gate with fast rise and fall times, while the low-speed operation circuit section Is composed of an element whose rise time and fall time are delayed, so that electromagnetic radiation is reduced at least in this circuit section.

For example, an element forming a low speed operation circuit is
By using a MOS transistor having a channel length longer than that of the MOS transistor of the high-speed operation circuit unit, the rise time and the fall time of the MOS transistor of the low-speed operation circuit unit are delayed to suppress electromagnetic radiation from the low-speed operation circuit unit. be able to.

Further, the bias voltage supplied to the elements forming the low-speed operation circuit section is set to be lower than the bias voltage supplied to the elements forming the high-speed operation circuit section, so that the transistor in the low-speed operation circuit section rises. By delaying the time and the fall time, it is possible to suppress the electromagnetic radiation from the low speed operation circuit unit.

Further, the elements constituting the low speed operation circuit are
By using a transistor having a capacitance (parasitic capacitance) larger than that of the MOS transistor of the high-speed operation circuit section, the rise time and fall time of the MOS transistor of the low-speed operation circuit section are delayed, and electromagnetic radiation from the low-speed operation circuit section is reduced. Can be suppressed.

[Brief description of drawings]

FIG. 1 is a block layout diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing rise time and fall time in each circuit unit of FIG. 1, in which (a) is a high-speed operation circuit unit,
(B) shows rise time and fall time in the low-speed operation circuit unit.

FIG. 3 is a block layout diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block layout diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

5A and 5B are diagrams showing rise time and fall time in each circuit unit of FIG. 4, in which FIG.
(B) shows rise time and fall time in the low-speed operation circuit unit.

6 is a diagram showing a graph of an envelope curve of a Fourier spectrum of the trapezoidal wave of FIGS. 5 (a) and 5 (b). FIG.

FIG. 7 is a block layout diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram of the physical location of a semiconductor integrated circuit implementing the circuit of the present invention.

FIG. 9 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 11 S / P conversion circuit 12 Digital signal processing circuit 13 P / S conversion circuit 14 Clock n frequency divider circuit 15 Bias circuit 15A High voltage bias circuit 15B Low voltage bias circuit 100 Semiconductor substrate 101 Short channel element region 102 Long channel element region 101 'A region with a small capacitance (parasitic capacitance) 102' A region with a large capacitance (parasitic capacitance) 601 I / O pin 602 Wire

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04B 15/00

Claims (9)

[Claims] 1. A semiconductor integrated circuit comprising a high-speed operation circuit section that requires a high-speed operation and a low-speed operation circuit section that is allowed to operate at a speed lower than the high-speed operation circuit section. A semiconductor integrated circuit comprising a device having a slow fall time. 2. The semiconductor integrated circuit according to claim 1, wherein
A MOS element having a channel length longer than that of the MOS transistor forming the high speed operation circuit
A semiconductor integrated circuit comprising a transistor. 3. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein a bias voltage supplied to an element forming a low speed operation circuit section is lower than a bias voltage supplied to an element forming a high speed operation circuit section. 4. The semiconductor integrated circuit according to claim 1, wherein the element forming the low-speed operation circuit section is provided with a capacitance (parasitic capacitance) so that the element forming the low-speed operation circuit section is made a high-speed operation circuit. A semiconductor integrated circuit comprising an element which has a slower on / off operation and a lower cut-off frequency than the elements constituting the part. 5. The semiconductor integrated circuit according to claim 4, further comprising a control input terminal for controlling a signal output, wherein a capacitance (parasitic capacitance) of a transistor at the control input terminal is a capacitance of an element forming a circuit portion (parasitic capacitance). The semiconductor integrated circuit is characterized in that it is formed larger than the parasitic capacitance. 6. The semiconductor integrated circuit according to claim 4, wherein the element operating at high speed is arranged outside the wafer to minimize a loop formed by a signal operating at high speed. Integrated semiconductor circuit. 7. A semiconductor integrated circuit which converts a serial signal into a parallel signal and then performs signal processing, wherein a MOS element which is an element forming a circuit section for processing a serial signal is an element forming a circuit section for processing a parallel signal. A semiconductor integrated circuit comprising a MOS transistor having a channel length longer than that of a transistor. 8. A semiconductor integrated circuit for converting a serial signal into a parallel signal and performing signal processing, wherein the circuit section for processing a serial signal is a bias voltage supplied to an element forming a circuit section for processing a parallel signal. The semiconductor integrated circuit is characterized in that the voltage is lower than the bias voltage supplied to the element. 9. A semiconductor integrated circuit for converting a serial signal into a parallel signal and performing signal processing, wherein the output capacitance (parasitic capacitance) of an element constituting a circuit unit for processing the parallel signal is a circuit for processing the serial signal. A semiconductor integrated circuit, which is formed to have a larger capacitance than the output capacitance (parasitic capacitance) of the elements forming the unit.