JPH08221279A - External interrupt signal processor - Google Patents

Abstract

PURPOSE: To prevent the malfunction such as multiplex interrupt owing to the noise which occurs during the external interrupt processing to a personal computer by using an extension card on the external interrupt signal processor. CONSTITUTION: In the external interrupt processing to a personal computer by using an extension card 1, a flip-flop 1a sends the required external interrupt signal (b) to the personal computer when an interrupt signal (a) is set. A personal computer 2 to which an interrupt signal is inputted writes the required data in a mask register 2a and outputs an address signal and a control signal S1 under the control of a control part 2b so as to prohibit the external interrupt. The address signal and the control signal S1 are sent to a decoder 1b of an extension card and the decoder decodes it. The flip-flop is reset by the decode signal (acknowledge signal c) and the interrupt signal is returned to an initial state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external interrupt signal processing device, and more particularly, to an external interrupt processing for a personal computer by using an expansion card, such as a multiple interrupt due to noise generated during the external interrupt processing. Preventing malfunctions.

[0002]

2. Description of the Related Art Conventionally, in the case of an external interrupt to a personal computer using an expansion card, an external interrupt signal S11 is sent from an expansion card (PC card) 11 to a personal computer 12 via a bus transmission line, as shown in FIG. Here, when the bus system is, for example, an ISA bus (IBM specification), the external interrupt is recognized at the rising edge of the interrupt signal. In this case, the interrupt signal is recognized by the personal computer side (processor) after the rising. Must stay high until. Further, in the past, since there was no interrupt acknowledge signal (a response signal indicating that the interrupt was recognized), it was unclear when the interrupt was permitted. Therefore, the interrupt signal is usually low → high → low ... Here, the duration of "high" is not uniform, but it is a unit of μsec or msec, and is predetermined in the design stage.

[0003]

However, as described above, since it is unknown when the interrupt is permitted, the "high" duration is set to a slightly longer time. Therefore, there is a high possibility that noise will be mixed in during this high state. When this noise is mixed, the maintenance of the high state is disturbed and an interrupt occurs, which causes a malfunction of multiple interrupts. Therefore, when the above-mentioned acknowledge signal is generated on the expansion card side and the interrupt on the personal computer side is recognized, if the interrupt signal can be returned to the initial state (low), the duration of "high" can be shortened and noise It is possible to reduce the degree of the possibility of being mixed.
The present invention has been made from such a point of view, and after the external interrupt is applied to the personal computer, when the external interrupt is recognized, the external interrupt signal is returned to the initial state to prevent malfunction due to noise mixing. Another object of the present invention is to provide an external interrupt signal processing device.

[0004]

According to the present invention, in an external interrupt processing to a personal computer by using an expansion card, a flip-flop for sending a required external interrupt signal to the personal computer when set by an interrupt signal, and the external device. Provided is an external interrupt signal processing device having a decoder for decoding an address signal and a control signal output from a personal computer side based on an input of an interrupt signal and resetting the flip-flop with the decoded signal in the expansion card. To do.

[0005]

When the flip-flop is set by the interrupt signal (set terminal), the external interrupt signal (high level) is sent from the flip-flop to the personal computer side. On the personal computer side to which the external interrupt signal is input, processing for prohibiting external interrupts is performed after the transition from the main routine to the interrupt routine. This is done by writing the required data in the mask register. This disables interrupts. Further, when the above data is written in the mask register, an address signal and a control signal are output, and this is sent to the decoder on the expansion card side. The decoder decodes these and uses this as an interrupt acknowledge signal. The flip-flop is reset by the acknowledge signal (reset terminal). As a result, the interrupt signal returns to the initial state (low level). On the other hand, the personal computer side writes the data to the mask register again at the end of the interrupt routine and enables the next interrupt.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An external interrupt signal processing device according to the present invention will be described below with reference to the drawings. 1 is a block diagram of essential parts showing an embodiment of an external interrupt signal processing device according to the present invention, and FIG. 2 is a time chart for explaining FIG. In FIG. 1, 1 is an expansion card (PC card), 1a
Has a set (S) terminal and a reset (R) terminal, and when an interrupt signal is input to the set terminal, a flip-flop that sends an external interrupt signal from the output (Q) terminal to the personal computer side, 1b from the personal computer side A decoder that decodes the control signal and the like that is sent and outputs this as an interrupt acknowledge signal, 2 is a personal computer in which the expansion card 1 is used, and 2a is provided in the personal computer device (existing), and external interrupt When there is, and at the end of the interrupt routine processing, a mask register to which required data is written respectively, 2b is a control unit (existing) which outputs a control signal or the like when writing control of the mask register 2a and writing at the time of external interrupt .

Next, the operation of the present invention will be described. In the following description, a bus system related to data transmission between the expansion card 1 and the personal computer 2 will be described by taking the ISA bus (IBM specification) as an example. When an external interrupt is applied to the PC 2 by the expansion card 1, first the flip-flop
The interrupt signal shown in FIG. 2A is input to the set (S) terminal of 1a. The flip-flop 1a outputs the external interrupt signal (H level) shown in FIG. 2B in synchronization with the falling edge (T1) of the interrupt signal (Q terminal), and the personal computer 2
Sent to the side. The PC 2 side is brought into the external interrupt state by the external interrupt signal which becomes the H level, and the main routine is shifted to the interrupt routine. Immediately after entering the interrupt routine, interrupt prohibition processing is performed. This is a mask register under the control of the controller 2b.
This is done by writing the required data in 2a. This required data is predetermined for each personal computer.

A new interrupt is prohibited by the above writing. Further, at the time of this writing, the address signal (10 bits of SA 0 to 9) and the control signal are output via the control unit 2b. The control signals are write strobe (IOW), bus control signals (AEN, BALE), etc. In FIG. 1, these are collectively referred to as S1. The control signal S1 and the like are sent to the decoder 1b on the expansion card 1 side and decoded by the decoder 1b. The decoded signal becomes the interrupt acknowledge signal shown in FIG. The interrupt acknowledge signal (C) is input to the reset (R) terminal of the flip-flop 1a, and the flip-flop 1a is reset at the falling edge (T2) of the signal. By this reset, the external interrupt signal (b) returns to low (L) and returns to the initial state of the interrupt.

On the other hand, at the end of the interrupt routine process on the personal computer 2 side, under the control of the control unit 2b again, the required data is written in the mask register 2a, and the process for permitting the next interrupt is performed. No control signal or the like is output during this processing. By the permission process and the reset of the flip-flop 1a, the next interrupt becomes possible. By operating as described above, for example, the personal computer 2
The external interrupt signal to the signal remains high level for a long time as in the conventional case [Fig. 2 (d)], and even if noise is mixed during this period, the reset process of the flip-flop 1a does not affect the noise. Like Also, as described above, when an external interrupt is applied on the personal computer side, the next interrupt is temporarily prohibited and the external signal is masked. As a result, the influence of noise is prevented even in this masked state. .

[0010]

As described above, according to the present invention, the external interrupt command to the personal computer by using the expansion card is issued only for a necessary period, and then the initial state is returned to and the long-time interrupt command as in the past is maintained. There is nothing to do. Therefore, conventionally, noise is mixed in the interrupt signal,
This solves the problem of malfunctions called multiple interrupts. Also, on the personal computer side, when there is an external interrupt, a process (software process) for temporarily prohibiting the next interrupt is performed, which also prevents the malfunction due to the noise mixing. From the above, the present invention can contribute to stabilizing the operation of the external interrupt by using the expansion card.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of an external interrupt signal processing device according to the present invention.

FIG. 2 is a time chart for explaining FIG.

FIG. 3 is a principal block diagram showing an example of a conventional external interrupt signal processing device.

[Explanation of symbols]

 1 Expansion card 1a Flip-flop 1b Decoder 2 Personal computer 2a Mask register 2b Controller

Claims (2)

[Claims] 1. In an external interrupt process for a personal computer using an expansion card, a flip-flop for transmitting a required external interrupt signal to the personal computer when set by an interrupt signal, and a personal computer based on the input of the external interrupt signal. An external interrupt signal processing device, characterized in that the expansion card is provided with a decoder for decoding an address signal and a control signal output from the side and resetting the flip-flop with the decoded signal. 2. A mask register in which the output of address signals and control signals from the personal computer side is written with required data for prohibiting a new external interrupt when the external interrupt signal is input, and a mask register of the mask register. An external interrupt signal processing device, wherein write control is performed by a control unit that outputs an address signal and a control signal at the time of the write.