JPH08214228A - Circuit for horizontally compressing sub-screen - Google Patents

Abstract

PURPOSE: To prevent the generation of a horizontal deviation in each line of a sub-screen picture even when a horizontal compression rate is changed at a moment generating a passing state or a passed state by allowing the number of horizontal samples of data written in a memory to coincide with that of data to be read out. CONSTITUTION: A sub-screen output signal (o) and a main screen field discriminating signal (i) are inputted to a reading circuit 18 and 1st and 2nd read enable pulses (p), (q) and a read reset pulse (r) are generated based upon data indicating the number of horizontal samples written in the address '0' of the memory. After generating these pulses, succeeding picture data are read out from the address '1' so that the number of horizontal samples of data practically written in a field memory is not deviated from that of data to be read out. Thereby even when a horizontal compression rate is changed at a moment generating a passing state or a passed state, a picture on a sub-screen is prevented from being deviated in the horizontal direction in each line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub-screen horizontal compression circuit for horizontally compressing a sub-screen when a plurality of video signals having different synchronisms are displayed on a video device.

[0002]

2. Description of the Related Art In recent years, there is an increasing need to obtain a plurality of images and information at the same time. Corresponding to such multimedia, when a plurality of video signals with different sync signal timing are simultaneously displayed on one video display device, a certain video signal is used as the main screen when viewed from the sync signal timing.
A display combining technique of a plurality of video signals when displaying other video signals as a sub-screen is important.

By the way, since the main screen signal is synchronized with the video display device, the video signal processing such as screen compression does not pose a problem in terms of timing, but the sub-screen signal is not synchronized with the display device. Consideration is required.

The present invention was invented with respect to a sub-screen horizontal compression circuit for horizontally compressing the sub-screen signal in the horizontal direction, and the video signals of both the main and sub-screens are premised on interlaced signals.

A conventional sub-screen horizontal compression circuit will be described below with reference to the drawings. 3 is a block diagram of a conventional sub-screen horizontal compression circuit, and FIG. 4 is an operation waveform diagram for explaining the operation of the conventional sub-screen horizontal compression circuit. The signals shown in FIGS. 3 and 4 correspond to each other.

In FIG. 3, reference numeral 31 is a horizontal compression for inputting a digitized sub-screen input signal a and a compression rate signal b which gives a horizontal compression rate, and for generating an interpolated sub-screen signal c and a horizontal write enable pulse d. It is a filter.

Reference numeral 32 inputs a horizontal write enable pulse d, a sub-screen field discrimination signal h and a main screen field discrimination signal i, and generates a first write enable pulse j, a second write enable pulse k and a write reset pulse l. It is a write control circuit for performing.

33 is a horizontal write enable pulse d
And a main screen field discrimination signal i are input, and a first read enable pulse p and a second read enable pulse q are input.
And a read control circuit for generating a read reset pulse r.

34 receives the interpolated sub-screen signal c, the first write enable pulse j, the write reset pulse l, the first read enable pulse p described later, and the read reset pulse r described later, and outputs the first 2 is a first field memory for outputting the compressed sub-screen signal m of.

35 receives the interpolated sub-screen signal c, the second write enable pulse k, the write reset pulse l, the second read enable pulse q described later, and the read reset pulse r described later, and outputs the second 2 is a second field memory for outputting the compressed sub-screen signal n.

A selector 36 receives the first compressed sub-screen signal m, the second compressed sub-screen signal n and the main screen field discrimination signal i and outputs the sub-screen output signal o. .

The operation of the sub-screen horizontal compression circuit configured as described above will be described below.

First, the digitized sub-screen input signal a
And the compression rate signal b which gives the compression rate
And the data to be sampled of the interpolated sub-screen signal c at a frequency according to the compression rate signal b and the interpolated sub-screen signal c obtained by interpolating the sub-screen input signal a according to the compression rate signal b. A horizontal write enable pulse d is generated which has a high level during the period synchronized with the above and a low level during the other periods.

Next, the horizontal write enable pulse d, the sub-screen field discrimination signal h, and the main screen field discrimination signal i are input to the write control circuit 32, and the first write enable pulse j and the second write enable pulse k are inputted. A write reset pulse 1 is generated. At this time, the first described later
Field memory 34 and second field memory 35
Basically, the data is written alternately, but when it is predicted that read overwriting will occur because the read speed is faster than the write speed, the reverse write operation is performed.

Next, the horizontal write enable pulse d and the main screen field discrimination signal i are input to the read control circuit 33 to generate the first read enable pulse p, the second read enable pulse q and the read reset pulse r. . At this time, the reading of data from the first field memory 34 and the second field memory 35, which will be described later, is alternately performed depending on the field polarity of the main screen.

Next, the interpolated sub-screen signal c, the first write enable pulse j, the write reset pulse l, the first read enable pulse p, and the read reset pulse r are input to the first field memory 34. , And outputs the first compressed sub-screen signal m.

Next, the interpolated sub-screen signal c, the second write enable pulse k, the write reset pulse l, the second read enable pulse q, and the read reset pulse r are input to the second field memory 35. , Second compressed sub-screen signal n is output.

At the output stage, the first compressed sub-screen signal m, the second compressed sub-screen signal n and the main screen field discrimination signal i are input to the selector 36 and the sub-screen output signal o is output. To do.

[0019]

SUMMARY OF THE INVENTION In the above conventional configuration,
Data writing to the first field memory and the second field memory is controlled in which memory the data is written so as not to overtake writing in reading. However, in the read control circuit, the read enable pulses are sequentially generated based on the horizontal enable pulse, depending on the field polarity of the main screen, so that the compression ratio is set at the moment when the read overwriting occurs. If changed, there is a problem that a field in which the number of horizontal samples of the data written in the memory does not match the number of horizontal samples to be read occurs.

The present invention has been invented in order to solve the above problems, although the occurrence frequency is low.

[0021]

In order to solve the above problems, the sub-screen horizontal compression circuit of the present invention is interpolated by inputting a digitized sub-screen input signal and a compression rate signal giving a horizontal compression rate. The horizontal compression filter that generates the sub-screen signal and horizontal write enable pulse, the horizontal sample number counter that inputs the horizontal write enable pulse and outputs the horizontal sample number, the horizontal write enable pulse, the sub-screen field discrimination signal, and the main screen A write control circuit that inputs a screen field determination signal to generate a first write enable pulse, a second write enable pulse, and a write reset pulse, an interpolated sub-screen signal, a horizontal sample number, and a control signal are input. Output a signal in which only the data with vertical synchronization period of the sub-screen signal interpolated by Of the first selector, the output signal of the first selector, the first write enable pulse, the write reset pulse, the first read enable pulse described later, and the read reset pulse described later are input to the first compressed sub-screen. A first field memory for outputting a signal,
The output signal of the first selector, the second write enable pulse, the write reset pulse, the second read enable pulse described later, and the read reset pulse described later are input and a second compressed sub-screen signal is output. A second field memory, a first compressed sub-screen signal and a second
Second selector for inputting the compressed sub-screen signal and the main screen field discrimination signal to output the sub-screen output signal, and the sub-screen output signal and the main screen field discrimination signal for the first read enable And a read control circuit for generating a second read enable pulse and a read reset pulse.

[0022]

With this configuration, the present invention ensures that the number of horizontal samples of the data written in the memory and the number of horizontal samples of the data to be read always match, and the horizontal compression rate is changed at the moment when the overtaking and overtaking occurs. Even if it makes it possible, it is possible to improve so that the image of the sub-screen does not shift in the horizontal direction line by line.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A sub-screen horizontal compression circuit showing an embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram of a sub-screen horizontal compression circuit showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram for explaining the operation of a sub-screen horizontal compression circuit showing an embodiment of the present invention. The signals shown in FIGS. 1 and 2 correspond to each other.

In FIG. 1, reference numeral 11 is a horizontal compression for inputting a digitized sub-screen input signal a and a compression rate signal b which gives a horizontal compression rate, and for generating an interpolated sub-screen signal c and a horizontal write enable pulse d. It is a filter.

A horizontal sample number counter 12 receives the horizontal write enable pulse d and outputs a horizontal sample number e.

A horizontal write enable pulse d, a sub-screen field discrimination signal h, and a main screen field discrimination signal i are inputted to 13 and the first write enable pulse j and the second write enable pulse j are inputted.
Write enable pulse k and write reset pulse l
Is a write control circuit that generates

Reference numeral 14 is a signal in which the interpolated sub-screen signal c, the horizontal sample number e and the control signal f are input, and only the data having the vertical synchronization period of the interpolated sub-screen signal c is replaced with the horizontal sample number e. It is a first selector that outputs g.

Reference numeral 15 receives the output signal g of the first selector, the first write enable pulse j, the write reset pulse l, the first read enable pulse p described later, and the read reset pulse r described later, 1 is a first field memory for outputting a compressed sub-screen signal m of 1.

Reference numeral 16 receives an output signal g of the first selector, a second write enable pulse k, a write reset pulse l, a second read enable pulse q which will be described later, and a read reset pulse r which will be described later. 2 is a second field memory for outputting 2 compressed sub-screen signals n.

A second selector 17 receives the first compressed sub-screen signal m, the second compressed sub-screen signal n and the screen field discrimination signal i and outputs the sub-screen output signal o. Is.

A read control circuit 18 receives the sub-screen output signal o and the main screen field discrimination signal i and generates a first read enable pulse p, a second read enable pulse q, and a read reset pulse r. .

The operation of the sub-screen horizontal compression circuit configured as described above will be described below.

First, the digitized sub-screen input signal a
And the compression rate signal b which gives the compression rate
The sub-screen input signal a is interpolated according to the compression rate signal b and the interpolated sub-screen signal c and the sub-screen signal c interpolated at a frequency according to the compression rate signal b are to be sampled. A horizontal write enable pulse d is generated which has a high level in the synchronized period and a low level in the other periods.

Next, the horizontal write enable pulse d is input to the horizontal sample number counter 12, the number of high-level clocks of the horizontal write enable pulse d per horizontal period is counted, and the horizontal sample number e is output.

Next, the horizontal write enable pulse d, the sub-screen field discrimination signal h and the main screen field discrimination signal i are input to the write control circuit 13, and the first write enable pulse j and the second write enable pulse k are inputted. A write reset pulse 1 is generated. At this time, the first described later
Basically, the data is written alternately in the field memory and the second field memory. However, when it is predicted that the read overwriting will occur because the read speed is faster than the write speed, the reverse write operation is performed.

Next, the interpolated sub-screen signal c, the number of horizontal samples e, and the control signal f are input to the first selector 14,
When writing only the data having the vertical synchronization period of the interpolated sub-screen signal c to the horizontal sample number e and outputting the signal g to write the data to the first field memory 15 and the second field memory 16 described later. , Digital data of the number of horizontal samples is written to address 0 of the memory.

Next, the output signal g of the first selector and the first signal
Write enable pulse j and write reset pulse l
And a first read enable pulse p, which will be described later, and a read reset pulse r, which will be described later.
, And outputs the first compressed sub-screen signal m.

Next, the output signal g of the first selector and the second signal
Write enable pulse k and write reset pulse l
And a second read enable pulse q, which will be described later, and a read reset pulse r, which will be described later, in the second field memory 16
And outputs the second compressed sub-screen signal n.

Next, the first compressed sub-screen signal m, the second compressed sub-screen signal n, the main screen field discrimination signal i and the second selector 17 are input to the sub-screen output signal o.
Is output.

Next, the sub-screen output signal o and the main-screen field discrimination signal i are input to the read control circuit 18, and based on the data of the horizontal sample number written in the address 0 of the memory, the first A read enable pulse p, a second read enable pulse q, and a read reset pulse r are generated. At this time, data of the horizontal sample number is taken into the read control circuit, and the read control circuit generates the first read enable pulse p, the second read enable pulse q, and the read reset pulse r, and then continues from the address 1. By reading the image data, the number of horizontal samples of the data actually written in the field memory and the number of horizontal samples of the data to be read do not shift.

The first field memory 15 and the second field memory 15
The data is read from the field memory 16 alternately according to the field polarity of the main screen.

As described above, according to the present embodiment, by writing the data of the horizontal sample number in the header portion of the memory, the horizontal sample number of the data written in the memory and the horizontal sample number of the data to be read are set. It is possible to make sure that they match, and even if the horizontal compression ratio is changed at the moment when overtaking occurs, it is possible to improve so that the image on the sub-screen does not shift horizontally in each line.

[0043]

As described above, according to the present invention, by writing the data of the horizontal sample number in the header portion of the memory, the horizontal sample number of the data written in the memory and the horizontal sample number of the data to be read out can be determined. It is possible to realize an excellent sub-screen horizontal compression circuit in which the images on the sub-screen do not shift in the horizontal direction line by line even if the horizontal compression ratio is changed at the moment when overtaking occurs. .

[Brief description of drawings]

FIG. 1 is a block diagram of a sub-screen horizontal compression circuit showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram for explaining the operation of the circuit.

FIG. 3 is a block diagram of a conventional sub-screen horizontal compression circuit.

FIG. 4 is an operation waveform diagram for explaining the operation of the circuit.

[Description of Reference Signs] 11 horizontal compression filter 12 horizontal sample number counter 13 write control circuit 15, 16 field memory 14, 17 selector 18 read control circuit a sub-screen input signal b compression rate signal c interpolated sub-screen signal d horizontal write Enable pulse e number of horizontal samples f control signal g output signal of first selector h sub-screen field determination signal i main screen field determination signal j first write enable pulse k second write enable pulse l write reset pulse m first Compressed sub-screen signal n Second compressed sub-screen signal o Sub-screen output signal p First read enable pulse q First read enable pulse r Read reset pulse

Claims (1)

[Claims] 1. A horizontal compression filter for generating a horizontal write enable pulse and a sub-screen signal interpolated by inputting a digitized sub-screen input signal and a compression ratio signal for providing a horizontal compression ratio, and the horizontal write enable pulse. And a horizontal sample number counter for outputting the number of horizontal samples, and the horizontal write enable pulse, the sub-screen field discriminating signal and the main screen field discriminating signal.
Write control circuit for generating the write enable pulse, the second write enable pulse, and the write reset pulse, and the interpolated sub-screen by inputting the interpolated sub-screen signal, the horizontal sample number, and the control signal f. A first selector that outputs a signal in which only data having a vertical synchronization period of the signal is replaced with the horizontal sample number, an output signal of the first selector, the first write enable pulse, the write reset pulse, and Inputting a first read enable pulse and a read reset pulse, which will be described later, to output a first compressed sub-screen signal; an output signal of the first selector; and a second field memory. A write enable pulse, the write reset pulse, a second read enable pulse described later, and a read reset described later. A second field memory for receiving a pulse and outputting a second compressed sub-screen signal, the first compressed sub-screen signal, the second compressed sub-screen signal and the main screen A second selector for receiving a field discrimination signal and outputting a sub-screen output signal; and a first read enable pulse and a second read enable pulse for receiving the sub-screen output signal and the main screen field discrimination signal And a sub-screen horizontal compression circuit having a read control circuit for generating a read reset pulse.