JPH08204982A - Sigmoid correction adjustment circuit - Google Patents

Abstract

PURPOSE: To reduce components and to perform appropriate sigmoid correction corresponding to plural horizontal scanning frequencies by turning on and off a switch connected to a sigmoid correction capacitor within respective horizontal scanning cycles. CONSTITUTION: When signals for turning off an FET 8 for switching are inputted to the gate of the FET 8 at a timing t1 from a switch control circuit 10, a current made to flow to the sigmoid correction capacitor 7 is cut off at the timing t1 as well. As a result, the FET 8 is turned off and a charging current is made to flow only to the sigmoid capacitor 6 of this sigmoid correction adjustment circuit A. The sigmoid capacitor 6 is charged up to maximum corresponding to the horizontal scanning cycle at the timing t2 of a scanning period and the capacitor 6 is discharged after the timing t2. A horizontal output transistor 1 is turned on by the discharging and a discharging current is made to flow from the capacitor 6 in the route of a linearity coil 5, a deflection yoke 4, the transistor 1 and the capacitor 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an S-shaped correction adjusting circuit used in a horizontal deflection circuit of a multi-scan display device capable of automatically supporting a plurality of horizontal scanning frequencies.

[0002]

2. Description of the Related Art In recent years, as the frequency of cathode ray tube display devices and the like has increased, multi-scan display devices that can automatically cope with a plurality of horizontal scanning frequencies have been widely used. By the way, in these multi-scan display devices, an appropriate S-shaped correction corresponding to the horizontal scanning frequency is required each time the horizontal scanning frequency changes. Therefore, in the conventional multi-scan display device, the S-shaped correction adjusting circuit A as shown in FIG. 5 is used for the horizontal deflection circuit so that an appropriate S-shaped correction corresponding to the horizontal scanning frequency is performed. Was.

That is, in the conventional S-shaped correction adjusting circuit A shown in FIG. 5, in response to changes in the horizontal scanning frequency,
For example, the S-shaped capacitor 6 and the S-shaped correction capacitor 7a
By combining (7b, 7c), the capacity of the composite S-shaped capacitor is changed, and an appropriate S-shaped correction corresponding to the horizontal scanning frequency is performed.

Each of the FETs 8a, 8b and 8c acts as a switch, and whether the FETs 8a, 8b and 8c are turned on or off is determined by their respective horizontal scanning frequencies. And FET8a, 8b, 8c
Whether to turn on or off is specifically determined by the output signal of the switch control circuit 10 whose input signal is the output signal from the microcomputer 12 which receives the horizontal synchronizing signal 14 and the vertical synchronizing signal 15 as input signals. Is configured. On the other hand, FIG. 6 shows the current flowing through the S-shaped capacitor 6 in the horizontal deflection circuit using the conventional S-shaped correction adjustment circuit.

[0005]

By the way, in the conventional S-shaped correction adjusting circuit constructed as shown in FIG. 5, the horizontal scanning frequency is, for example, 31.5.
In the case of changing in the range of kHz to 57 kHz, the S-shaped capacitor 6 and the S-shaped correction capacitors 7a, 7b and 7c and the FETs 8a, 8b and 8c that act as switches are required as the components of the S-shaped correction adjustment circuit. . For this reason,
Since the number of components of the S-shaped correction adjustment circuit is large, there is a problem in manufacturing workability, and there is a problem that the S-shaped correction adjustment circuit becomes expensive.

The present invention solves these problems, requires a small number of constituent parts, and is suitable for a multi-scan display device capable of automatically supporting a plurality of horizontal scanning frequencies, and provides an inexpensive S-shaped correction adjusting circuit. Is what you are trying to do.

[0007]

An S-shaped correction adjustment circuit used in a horizontal deflection circuit of a multi-scan display device capable of supporting a plurality of horizontal scanning frequencies, the S-shaped capacitor 6, the S-shaped correction capacitor 7, and a diode. 9 and a switching FET 8 and outputs the respective outputs of the microcomputer 12 having the horizontal synchronizing signal 14 and the vertical synchronizing signal 15 as input signals and the AFC circuit 13 having the horizontal synchronizing signal 14 as an input signal. By the output signal of the switch control circuit 10, the FET is synchronized with the horizontal scanning period and turned on within the horizontal scanning period.
By switching to turn off, the FE
The T switching timing is adjusted to perform an appropriate S-shaped correction for a plurality of horizontal scanning frequencies.

[0008]

With the use of the AFC circuit, the FET, which is a switch connected to the S-shaped correction capacitor, can be synchronized with the horizontal scanning cycle and switched so as to be turned on and off within the horizontal scanning period. Since the switching timing of is adjusted and the capacitance of the S-shaped correction capacitor is changed equivalently, proper S-shaped correction corresponding to a plurality of horizontal scanning frequencies can be performed with an inexpensive structure.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram of a horizontal deflection circuit in which an S-shaped correction adjusting circuit according to the present invention is used, and FIG. 2 is a waveform diagram of a main part in FIG. In the figure, reference numeral 1 is a horizontal output transistor, and a damper diode 2 and a resonance capacitor 3 are provided on the collector side thereof.
Is connected, and a series circuit of the deflection yoke 4 and the linearity coil 5 is connected. Further, an S-shaped capacitor 6 and an S-shaped correction capacitor 7 forming an S-shaped correction adjustment circuit A are connected to one end of the linearity coil 5, and an FET 8 in which a diode 9 is connected in parallel to the S-shaped correction capacitor 7 Are connected in series, and a flyback transformer T is connected to the collector side of the horizontal output transistor 1.

On the other hand, reference numeral 12 is a microcomputer which receives the horizontal synchronizing signal 14 and the vertical synchronizing signal 15 as input signals, and outputs an output signal corresponding to the horizontal scanning period to the switch control circuit 10. An AFC circuit 13 receives the horizontal synchronizing signal 14 as an input signal and outputs a signal for switching the FET 8 in synchronization with the horizontal scanning period to the switch control circuit 10. 10 is a microcomputer 12
Of the AFC circuit 13 and the output of the AFC circuit 13 as input signals. The switch control circuit is configured to output a signal for adjusting the switching timing of the FET 8 to the gate of the FET 8.

The operation of S-shaped correction by the S-shaped correction adjusting circuit A of the present invention thus constructed will be described with reference to FIG.
Although the gate voltage waveform of the FET 8 is shown in FIG. 2A, the FE is in a period during which the FET 8 can be controlled as a switch.
Only when the current flowing through T8 is in the forward direction. Then, when a signal for turning off the FET 8 which is a switch is input from the switch control circuit 10 to the gate of the FET 8 at the timing of t1, the current flowing through the S-shaped correction capacitor 7 is also t1 as shown in FIG. 2B. It is cut off at the timing. As a result, FET8 is turned off and the charging current is S
Only the S-shaped capacitor 6 of the character correction adjustment circuit A comes to flow.

Next, as shown in FIG. 2 (c), the timing of t2 in the scanning period is the timing at which the S-shaped capacitor 6 is maximally charged in accordance with the horizontal scanning cycle, and after t2, the S-shaped capacitor 6 is charged. The discharge starts. Then, when the S-shaped capacitor 6 starts discharging, the horizontal output transistor 1 is turned on, and the discharge current changes from the S-shaped capacitor 6 to the linearity coil 5, the deflection yoke 4, and the like.
It flows in the path of the horizontal output transistor 1 and the S-shaped capacitor 6.

On the other hand, the FET8 is also turned on at the timing of t2.
However, the S-shaped correction capacitor 7 does not flow a discharge current until the potential of the S-shaped capacitor 6 becomes slightly lower than the potential of the S-shaped correction capacitor 7. Here, S-shaped capacitor 6
If the timing at which the potential of is slightly lower than the potential of the S-shaped correction capacitor 7 is t3, the discharge current is t3 to t4.
The current flows through the diode 9 during the period.

FIG. 3 shows the waveform of the current flowing in the deflection yoke 4. The deflection current 16 when the S-shaped correction adjusting circuit A according to the present invention is used in the horizontal deflection circuit and the horizontal deflection circuit of the conventional circuit are shown. Comparing with the deflection current 17 in the present invention, the deflection current 16 in the present invention has a gradient of the current 16 which is slightly steeper than the current 17 of the conventional circuit in the middle of the scanning period, and also at the beginning and end of the scanning period. Current is 17
It's more gentle.

FIG. 4 shows an S-shaped correction adjusting circuit A according to the present invention.
Is used in the horizontal deflection circuit, the scanning frequency is 31.5
The specific current waveforms flowing in the S-shaped correction capacitor 7 at kHz, 48 kHz and 57 kHz are shown.

[0016]

As described above, according to the S-shaped correction adjusting circuit of the present invention, the FET connected to the S-shaped correction capacitor and functioning as a switch is synchronized with each horizontal scanning period,
Moreover, by switching so as to turn on and off within each horizontal scanning cycle, it is possible to adjust the switching timing of the FET, and it is possible to equivalently change the capacitance of the S-shaped correction capacitor. As a result, a horizontal deflection circuit suitable for a multi-scan display device capable of performing an appropriate S-shaped correction corresponding to a plurality of horizontal scanning frequencies can be obtained. Further, since it is a simple means of adjusting the switching timing of the FET, the number of constituent parts of the S-shaped correction adjusting circuit is small, and an inexpensive horizontal deflection circuit excellent in manufacturing workability can be obtained. The practical effects are great.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a horizontal deflection circuit using an S-shaped correction adjustment circuit of the present invention.

FIG. 2 is a waveform diagram of main parts in FIG.

FIG. 3 is an explanatory diagram showing a waveform of a current flowing through a deflection yoke 4.

FIG. 4 is an explanatory diagram showing a current waveform of an S-shaped correction capacitor at each scanning frequency.

FIG. 5 is a circuit diagram showing a conventional S-shaped correction adjustment circuit.

FIG. 6 is a waveform diagram of a current flowing through the S-shaped capacitor 6.

[Explanation of symbols]

 1 horizontal output transistor 2 damper diode 3 resonance capacitor 4 deflection yoke 5 linearity coil 6 S-shaped capacitor 7, 7a, 7b, 7c S-shaped correction capacitor 8, 8a, 8b, 8c FET 9, 9a, 9b, 9c diode 10 switch control Circuit 12 Microcomputer 13 AFC circuit 14 Horizontal sync signal 15 Vertical sync signal 16,17 Deflection current A S-shaped correction adjustment circuit T Flyback transformer

Claims (1)

[Claims] 1. An S-shaped correction adjusting circuit used in a horizontal deflection circuit of a multi-scan display device capable of supporting a plurality of horizontal scanning frequencies, the S-shaped capacitor 6, the S-shaped correction capacitor 7, a diode 9 and switching. A microcomputer 1 which comprises a FET 8 of and which receives a horizontal synchronizing signal 14 and a vertical synchronizing signal 15 as input signals.
2 and the output signal of the switch control circuit 10 having the respective outputs of the AFC circuit 13 having the horizontal synchronizing signal 14 as an input signal, the FET 8 is synchronized with the horizontal scanning period and turned on and off within the horizontal scanning period. The S-shaped correction adjusting circuit is configured so that the switching timing of the FET 8 is adjusted by performing such switching so as to perform an appropriate S-shaped correction for a plurality of horizontal scanning frequencies.