JPH08204377A - Shielding body - Google Patents
Shielding bodyInfo
- Publication number
- JPH08204377A JPH08204377A JP914095A JP914095A JPH08204377A JP H08204377 A JPH08204377 A JP H08204377A JP 914095 A JP914095 A JP 914095A JP 914095 A JP914095 A JP 914095A JP H08204377 A JPH08204377 A JP H08204377A
- Authority
- JP
- Japan
- Prior art keywords
- shield
- electrode
- circuit
- inner electrode
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/1617—Cavity coating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、遮蔽体に関し、特にデ
ィジタル回路とアナログ回路とが混在した回路のEMC
(電磁気的両立性)障害軽減に有効である遮蔽体に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shield, and more particularly to an EMC of a circuit in which a digital circuit and an analog circuit are mixed.
(Electromagnetic compatibility) The present invention relates to a shield that is effective in reducing obstacles.
【0002】[0002]
【従来の技術】周知のように、PLL回路はディジタル
信号を扱うディジタル回路とアナログ信号を扱うアナロ
グ回路との混在回路で構成されている。従来、このよう
な混在回路の電磁遮蔽は図3に示すようにして行われて
いる。2. Description of the Related Art As is well known, a PLL circuit is composed of a mixed circuit of a digital circuit that handles digital signals and an analog circuit that handles analog signals. Conventionally, electromagnetic shielding of such a mixed circuit is performed as shown in FIG.
【0003】PLL回路はディジタル回路部32を有す
る。ディジタル回路部32から発生するノイズが同一基
板内に実装されている他の回路に影響を及ぼさないよう
に、ディジタル回路部32を金属板で構成される遮蔽体
31で遮蔽する。さらに、遮蔽体31に設けられた複数
の貫通孔に複数個の貫通コンデンサ33を挿入して半田
付けすることにより、ディジタル回路部32から発生し
た高周波ノイズ成分を複数個の貫通コンデンサ33を介
して遮蔽体31に逃がす。このよう構造により、ディジ
タル回路部32で発生したノイズが複数のパタン36を
介して他回路に混入しないようにされている。遮蔽体3
1はネジ37で基板38に取付けられている。尚、複数
のパタン36と複数個の貫通コンデンサ33とは、それ
ぞれ、基板38上に立設された複数個の端子34と複数
本の線材35を介して接続されている。The PLL circuit has a digital circuit section 32. The digital circuit section 32 is shielded by a shield 31 made of a metal plate so that noise generated from the digital circuit section 32 does not affect other circuits mounted on the same substrate. Further, by inserting a plurality of feedthrough capacitors 33 into a plurality of through holes provided in the shield 31 and soldering them, a high frequency noise component generated from the digital circuit section 32 is passed through the plurality of feedthrough capacitors 33. Let it escape to the shield 31. With such a structure, noise generated in the digital circuit section 32 is prevented from mixing into other circuits through the plurality of patterns 36. Shield 3
1 is attached to a substrate 38 with screws 37. The plurality of patterns 36 and the plurality of feedthrough capacitors 33 are connected to a plurality of terminals 34 standing on a substrate 38 and a plurality of wires 35, respectively.
【0004】ここで、先行技術として、例えば特開平4
−26082号公報には、アナログ回路とディジタル回
路との間を遮蔽するために、複数本の導線が貫通する複
数個の透孔が形成された誘電板に導電部材を積層したサ
ブシールド板を用いる技術が開示されている。Here, as a prior art, for example, Japanese Patent Laid-Open No.
JP-A-26082 uses a sub-shield plate in which a conductive member is laminated on a dielectric plate in which a plurality of through holes through which a plurality of conductors pass is formed in order to shield between an analog circuit and a digital circuit. The technology is disclosed.
【0005】[0005]
【発明が解決しようとする課題】以上述べたように、従
来の遮蔽体では、図3に示すように、遮蔽体31を基板
38にネジ37で取付け、さらに貫通コンデンサ33を
遮蔽体31の貫通孔に半田付けしている。このような構
成では、遮蔽体31を基板38上に取付けるのに多数の
手間を要するため、作業効率が良くないという問題があ
る。また、高周波ノイズをシールドするには個別にコン
デンサ33が必要であるため、そのコンデンサ33の実
装スペースや実装の際の作業効率も問題となる。さら
に、従来の遮蔽体では、遮蔽体内部のノイズ源から放射
される電磁波を遮蔽体の外部へ漏らさないようにノイズ
対策を行っているだけなので、遮蔽体外部へのノイズ対
策には有効であるが、遮蔽体内部の回路への影響につい
て配慮がなされていない。As described above, in the conventional shield body, as shown in FIG. 3, the shield body 31 is attached to the substrate 38 with the screw 37, and the feedthrough capacitor 33 penetrates the shield body 31. Soldered in the hole. In such a configuration, it takes a lot of time and effort to mount the shield 31 on the substrate 38, so that there is a problem that work efficiency is not good. Further, since a capacitor 33 is individually required to shield high frequency noise, the mounting space of the capacitor 33 and the work efficiency at the time of mounting become a problem. Furthermore, in the conventional shield, only noise countermeasures are taken so that the electromagnetic waves radiated from the noise source inside the shield are not leaked to the outside of the shield, which is effective as a noise countermeasure to the outside of the shield. However, no consideration is given to the influence on the circuit inside the shield.
【0006】本発明は上記の課題を解決するためになさ
れたもので、その目的はディジタル・アナログ回路混在
基板において、高周波ノイズの混入を防止できる、取付
けが簡易な遮蔽体を提供することにある。The present invention has been made to solve the above problems, and an object of the present invention is to provide a shield which is capable of preventing high-frequency noise from being mixed in a mixed digital / analog circuit board and which can be easily mounted. .
【0007】ここで、上記先行技術は、導線と導電性部
材とが誘電板を介して貫通コンデンサを形成して、高周
波ノイズを効率良くシールドする技術を開示するもので
あって、サブシールド板に導線の数だけの透孔を形成し
なければならず、サブシールド板を製造することが難し
いという欠点がある。Here, the above-mentioned prior art discloses a technique in which a conducting wire and a conductive member form a feedthrough capacitor via a dielectric plate to efficiently shield high frequency noise. There is a drawback that it is difficult to manufacture the sub-shield plate because it is necessary to form as many through-holes as there are conducting wires.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するため
に本発明に係る遮蔽体は、ディジタル回路とアナログ回
路とが混在した回路を同一基板上に実装した場合に、前
記ディジタル回路から発生するノイズが前記アナログ回
路に影響を及ぼさないように遮蔽する遮蔽体において、
一面が開口した箱形の誘電体と、該誘電体の内側に形成
された内側電極と、前記誘電体の外側に形成された外側
電極とからなる積層構造を持ち、前記内側電極と前記外
側電極との間に電荷を蓄える機能を有し、前記内側電極
の内面に電波吸収体を有することを特徴とする。In order to achieve the above object, a shield according to the present invention is generated from a digital circuit when a circuit in which a digital circuit and an analog circuit are mixed is mounted on the same substrate. In a shield that shields noise from affecting the analog circuit,
It has a laminated structure including a box-shaped dielectric material having an opening on one side, an inner electrode formed inside the dielectric material, and an outer electrode formed outside the dielectric material. And a radio wave absorber on the inner surface of the inner electrode.
【0009】[0009]
【作用】本発明による遮蔽体では、遮蔽体を構成する層
に電極−誘電体−電極の積層構造を持たせ、遮蔽体自体
にコンデンサとしての機能を持たせる。In the shield according to the present invention, the layer forming the shield has a laminated structure of electrode-dielectric-electrode, and the shield itself has a function as a capacitor.
【0010】コンデンサの容量Cは、 C=ε0 ・εs ・A/d [F/m] と表される。ここで、ε0 は真空の誘電率(=8.85
5×10-12 )、εs は誘電体の比誘電率、Aは電極の
対極面積、dは電極間距離である。コンデンサの容量C
は上記のεs 、A、およびdを適切に設定すれば良い。The capacitance C of the capacitor is expressed as C = ε 0 · ε s · A / d [F / m]. Here, ε 0 is the dielectric constant of vacuum (= 8.85).
5 × 10 −12 ), ε s is the relative permittivity of the dielectric, A is the counter electrode area of the electrode, and d is the distance between the electrodes. Capacitance C of capacitor
Should set the above-mentioned ε s , A, and d appropriately.
【0011】また、遮蔽体の内側となる面には電波吸収
体を設ける。2つの電極にはそれぞれリード線が接続さ
れており、遮蔽体の実装方法はリード線を基板のスルー
ホースに差し込んで、リード線を半田付けすれば良い。A radio wave absorber is provided on the inner surface of the shield. A lead wire is connected to each of the two electrodes, and the shield may be mounted by inserting the lead wire into a through hose of the substrate and soldering the lead wire.
【0012】[0012]
【実施例】以下、図面を参照して本発明の実施例につい
て詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【0013】図2は本発明の一実施例に係る遮蔽体の実
装図である。図1は遮蔽体1をプリント基板10上に実
装したときの断面図である。プリント基板10にディジ
タル回路である集積回路5が実装されている。遮蔽体1
は、誘電体セラミックス23を遮蔽体の形(箱形)にプ
レスし、その両面に導電性の塗料を塗布することにより
外側電極21および内側電極22を形成し、さらに内側
電極22に電波吸収体フェライト24を塗布することに
よって、作成される。尚、本実施例では、外側電極21
に絶縁性被膜塗料30が塗布されている。FIG. 2 is a mounting view of a shield according to an embodiment of the present invention. FIG. 1 is a cross-sectional view when the shield 1 is mounted on the printed board 10. An integrated circuit 5 which is a digital circuit is mounted on a printed circuit board 10. Shield 1
Is formed by pressing the dielectric ceramics 23 into a shield shape (box shape) and applying conductive paint on both surfaces thereof to form the outer electrode 21 and the inner electrode 22. It is created by applying ferrite 24. In this embodiment, the outer electrode 21
Insulating film paint 30 is applied to.
【0014】遮蔽体1の内側電極22および外側電極2
1にはそれぞれリード線3、4が接続されている。ま
た、プリント基板10にはリード線3、4に対応する位
置にそれぞれスルーホール11、12が空けられてい
る。この集積回路5をアナログ回路等の他の外部回路か
ら電磁界的に遮蔽するために、遮蔽体1を集積回路5に
かぶせ、リード線3、4をそれぞれスルーホール11、
12に差し込み、半田29付けをして、プリント基板1
0上に遮蔽体1を実装する。集積回路5は複数の電極ピ
ン6の他に、グランドピン7と電源ピン8を有してい
る。プリント基板10の表面には複数の信号パタン9が
形成されおり、信号パタン9の一端に電極ピン6が接続
される。The inner electrode 22 and the outer electrode 2 of the shield 1
Lead wires 3 and 4 are connected to 1 respectively. Also, through holes 11 and 12 are formed in the printed circuit board 10 at positions corresponding to the lead wires 3 and 4, respectively. In order to electromagnetically shield the integrated circuit 5 from other external circuits such as analog circuits, the shield 1 is covered with the integrated circuit 5, and the lead wires 3 and 4 are provided in the through holes 11, respectively.
Printed circuit board 1
The shield 1 is mounted on 0. The integrated circuit 5 has a ground pin 7 and a power supply pin 8 in addition to the plurality of electrode pins 6. A plurality of signal patterns 9 are formed on the surface of the printed board 10, and the electrode pins 6 are connected to one ends of the signal patterns 9.
【0015】プリント基板10の裏面には電源プリント
パタン25およびグランドプリントパタン26が形成さ
れている。リード線3は電源プリントパタン25を介し
て集積回路5の電源ピン8と電気的に接続されている。
同様に、リード線4もグランドプリントパタン26を介
して集積回路5のグランドピン7に接続されている。A power supply print pattern 25 and a ground print pattern 26 are formed on the back surface of the printed circuit board 10. The lead wire 3 is electrically connected to the power supply pin 8 of the integrated circuit 5 via the power supply print pattern 25.
Similarly, the lead wire 4 is also connected to the ground pin 7 of the integrated circuit 5 via the ground print pattern 26.
【0016】プリント基板10には電源一面パタン27
とグランド一面パタン28とが形成されている。遮蔽体
1の内側電極22と電源一面パタン27又はグランド一
面パタン28とによって閉空間が形成されている。The printed circuit board 10 has a pattern 27 on one surface of the power source.
And a ground surface pattern 28 are formed. A closed space is formed by the inner electrode 22 of the shield 1 and the power supply one-side pattern 27 or the ground one-side pattern 28.
【0017】上記のように遮蔽体1を実装することで、
上記閉空間内で集積回路5から放射されるノイズを内側
電極22の表面の電波吸収体フェライト24で吸収さ
せ、かつ遮蔽体1の外部回路と同一基板内で電磁界的に
遮蔽することができる。By mounting the shield 1 as described above,
Noise radiated from the integrated circuit 5 in the closed space can be absorbed by the radio wave absorber ferrite 24 on the surface of the inner electrode 22 and electromagnetically shielded in the same substrate as the external circuit of the shield 1. .
【0018】また、外側電極21、誘電体セラミックス
23、および内側電極22によってコンデンサが形成さ
れる構造であるので、リード線3、4を集積回路5の電
源ピン8、グランドピン7にそれぞれ電気的に接続する
ことで、上記コンデンサを高周波的に極めて有効に作用
するバイパスコンデンサとして使用できる。上記コンデ
ンサをバイパスコンデンサとして使用することで、外部
回路からの電磁界的な遮蔽だけでなく、電源パタンへの
ノイズ放射をグランドへ逃がすことができる。Since the capacitor is formed by the outer electrode 21, the dielectric ceramics 23, and the inner electrode 22, the lead wires 3 and 4 are electrically connected to the power supply pin 8 and the ground pin 7 of the integrated circuit 5, respectively. The capacitor can be used as a bypass capacitor that works extremely effectively at high frequencies. By using the above capacitor as a bypass capacitor, not only electromagnetic field shielding from an external circuit but also noise radiation to the power supply pattern can be released to the ground.
【0019】尚、本発明は上記実施例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲で種々変形し
ても同様に実施可能であることはいうまでもない。It is needless to say that the present invention is not limited to the above-mentioned embodiments, and that various modifications may be made without departing from the scope of the present invention.
【0020】[0020]
【発明の効果】以上述べたように本発明による遮蔽体
は、遮蔽体自体にバイパスコンデンサとしての機能があ
るため、集積回路に個別に接続した貫通コンデンサが不
要となり、遮蔽体の外部・内部の両回路への高周波ノイ
ズの放射を防止できる。また、遮蔽体のリード線を基板
のスルーホールに差し込み、半田付けをするという簡易
な作業で取り付けられるので、作業効率が良くなる。As described above, in the shield according to the present invention, since the shield itself has a function as a bypass capacitor, a feedthrough capacitor individually connected to an integrated circuit is not necessary, and the shield inside and outside the shield is not required. Radiation of high frequency noise to both circuits can be prevented. Further, since the lead wire of the shield is inserted into the through hole of the substrate and soldering is performed, the work efficiency is improved.
【図1】本発明の一実施例による遮蔽体を集積回路と共
に基板上に実装した状態で示す断面図である。FIG. 1 is a cross-sectional view showing a state where a shield according to an embodiment of the present invention is mounted on a substrate together with an integrated circuit.
【図2】図1に示す遮蔽体を基板上に実装するときの状
態を示す斜視図である。FIG. 2 is a perspective view showing a state in which the shield shown in FIG. 1 is mounted on a substrate.
【図3】従来の遮蔽体を基板上に実装した状態で示す一
部透視斜視図である。FIG. 3 is a partially transparent perspective view showing a conventional shield mounted on a substrate.
1 遮蔽体 3,4 リード線 5 集積回路 6 電極ピン 7 グランドピン 8 電源ピン 9 信号パタン 10 プリント基板 11,12 スルーホール 21 外側電極 22 内側電極 23 誘電体セラミックス 24 電波吸収体フェライト 25 電源プリントパタン 26 グランドプリントパタン 27 電源一面パタン 28 グランド一面パタン 29 半田 30 絶縁被膜塗料 1 Shield 3,4 Lead Wire 5 Integrated Circuit 6 Electrode Pin 7 Ground Pin 8 Power Pin 9 Signal Pattern 10 Printed Circuit Board 11, 12 Through Hole 21 Outer Electrode 22 Inner Electrode 23 Dielectric Ceramic 24 Radio Wave Absorber Ferrite 25 Power Print Pattern 26 Ground Print Pattern 27 Power Supply One Side Pattern 28 Ground One Side Pattern 29 Solder 30 Insulating Film Paint
Claims (2)
した回路を同一基板上に実装した場合に、前記ディジタ
ル回路から発生するノイズが前記アナログ回路に影響を
及ぼさないように遮蔽する遮蔽体において、 一面が開口した箱形の誘電体と、該誘電体の内側に形成
された内側電極と、前記誘電体の外側に形成された外側
電極とからなる積層構造を持ち、前記内側電極と前記外
側電極との間に電荷を蓄える機能を有し、前記内側電極
の内面に電波吸収体を有することを特徴とする遮蔽体。1. A shield that shields noise generated from the digital circuit so as not to affect the analog circuit when a circuit in which a digital circuit and an analog circuit are mixed is mounted on the same substrate. A box-shaped dielectric having an opening, an inner electrode formed inside the dielectric, and an outer electrode formed outside the dielectric, and having a laminated structure, the inner electrode and the outer electrode A shield having a function of accumulating electric charges between the inner electrode and a radio wave absorber on the inner surface of the inner electrode.
とグランドプリントパタンとが形成されており、前記基
板には前記電源プリントパタンおよび前記グランドプリ
ントパタンにそれぞれ達する第1および第2のスルーホ
ールが空けられており、前記遮蔽体は前記内側電極に一
端が接続されて前記第1のスルーホールに差し込まれる
第1のリード線と、前記外側電極に一端が接続されて前
記第2のスルーホールに差し込まれる第2のリード線と
を有する請求項1記載の遮蔽体。2. A power supply print pattern and a ground print pattern are formed on the back surface of the substrate, and first and second through holes reaching the power supply print pattern and the ground print pattern are formed on the substrate, respectively. The shield is provided with a first lead wire having one end connected to the inner electrode and inserted into the first through hole, and a shield wire having one end connected to the outer electrode and the second through hole. The shield according to claim 1, having a second lead wire inserted therein.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP914095A JPH08204377A (en) | 1995-01-24 | 1995-01-24 | Shielding body |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP914095A JPH08204377A (en) | 1995-01-24 | 1995-01-24 | Shielding body |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08204377A true JPH08204377A (en) | 1996-08-09 |
Family
ID=11712330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP914095A Withdrawn JPH08204377A (en) | 1995-01-24 | 1995-01-24 | Shielding body |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08204377A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11121976A (en) * | 1997-10-15 | 1999-04-30 | Kitagawa Ind Co Ltd | Heat-radiating structure for electronic component |
JP2001185888A (en) * | 1999-12-27 | 2001-07-06 | Mitsubishi Electric Corp | Shield case |
JP2002217585A (en) * | 2001-01-15 | 2002-08-02 | Kitagawa Ind Co Ltd | Electromagnetic wave suppression member, and method for suppressing electromagnetic wave |
US6545212B1 (en) | 1998-10-27 | 2003-04-08 | Murata Manufacturing Co., Ltd. | Radiation noise suppressing component attachment structure |
JP2008060358A (en) * | 2006-08-31 | 2008-03-13 | Nintendo Co Ltd | Electronic equipment |
WO2009107303A1 (en) * | 2008-02-28 | 2009-09-03 | 日本電気株式会社 | Electromagnetic shield structure, wireless device using the structure, and electromagnetic shield manufacturing method |
CN103872024A (en) * | 2014-02-18 | 2014-06-18 | 南京银茂微电子制造有限公司 | High frequency anti-electromagnetic interference power module |
CN105519240A (en) * | 2015-06-29 | 2016-04-20 | 深圳市柔宇科技有限公司 | Circuit board structure and electronic equipment |
JP2016070848A (en) * | 2014-09-30 | 2016-05-09 | 株式会社東芝 | Magnetic shield package |
JP2017092177A (en) * | 2015-11-06 | 2017-05-25 | 株式会社村田製作所 | Shield structure of semiconductor device and method of manufacturing shield cover device |
-
1995
- 1995-01-24 JP JP914095A patent/JPH08204377A/en not_active Withdrawn
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11121976A (en) * | 1997-10-15 | 1999-04-30 | Kitagawa Ind Co Ltd | Heat-radiating structure for electronic component |
US6545212B1 (en) | 1998-10-27 | 2003-04-08 | Murata Manufacturing Co., Ltd. | Radiation noise suppressing component attachment structure |
JP2001185888A (en) * | 1999-12-27 | 2001-07-06 | Mitsubishi Electric Corp | Shield case |
JP2002217585A (en) * | 2001-01-15 | 2002-08-02 | Kitagawa Ind Co Ltd | Electromagnetic wave suppression member, and method for suppressing electromagnetic wave |
JP2008060358A (en) * | 2006-08-31 | 2008-03-13 | Nintendo Co Ltd | Electronic equipment |
US8379408B2 (en) | 2008-02-28 | 2013-02-19 | Nec Corporation | Electromagnetic shield structure, wireless device using the structure, and method of manufacturing electromagnetic shield |
WO2009107303A1 (en) * | 2008-02-28 | 2009-09-03 | 日本電気株式会社 | Electromagnetic shield structure, wireless device using the structure, and electromagnetic shield manufacturing method |
JP5170232B2 (en) * | 2008-02-28 | 2013-03-27 | 日本電気株式会社 | Electromagnetic shield structure, radio apparatus using the same, and method for manufacturing electromagnetic shield |
CN103872024A (en) * | 2014-02-18 | 2014-06-18 | 南京银茂微电子制造有限公司 | High frequency anti-electromagnetic interference power module |
JP2016070848A (en) * | 2014-09-30 | 2016-05-09 | 株式会社東芝 | Magnetic shield package |
CN105519240A (en) * | 2015-06-29 | 2016-04-20 | 深圳市柔宇科技有限公司 | Circuit board structure and electronic equipment |
WO2017000110A1 (en) * | 2015-06-29 | 2017-01-05 | 深圳市柔宇科技有限公司 | Circuit board structure and electronic device |
CN105519240B (en) * | 2015-06-29 | 2019-12-27 | 深圳市柔宇科技有限公司 | Circuit board structure and electronic equipment |
JP2017092177A (en) * | 2015-11-06 | 2017-05-25 | 株式会社村田製作所 | Shield structure of semiconductor device and method of manufacturing shield cover device |
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