JPH08202653A - Parallel signal transmission equipment - Google Patents

Parallel signal transmission equipment

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Publication number
JPH08202653A
JPH08202653A JP1203195A JP1203195A JPH08202653A JP H08202653 A JPH08202653 A JP H08202653A JP 1203195 A JP1203195 A JP 1203195A JP 1203195 A JP1203195 A JP 1203195A JP H08202653 A JPH08202653 A JP H08202653A
Authority
JP
Japan
Prior art keywords
signal
transmission
request
test signal
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1203195A
Other languages
Japanese (ja)
Other versions
JP3487458B2 (en
Inventor
Toshiharu Murai
俊晴 村井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP01203195A priority Critical patent/JP3487458B2/en
Publication of JPH08202653A publication Critical patent/JPH08202653A/en
Application granted granted Critical
Publication of JP3487458B2 publication Critical patent/JP3487458B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE: To apply a parallel signal transmission equipment to a transmission line whose signal transmission direction is unidirectional or a half duplex transmission line, to prevent malfunction, and to correctly correct inter-signal skew without spoiling the efficiency of original signal transmission. CONSTITUTION: This transmission equipment is equipped with a means 16 which sends a test signal to all lines of a transmission line 13 in the same timing on the signal transmission side and means 171 -17n which measure and store the times from a test signal reception point of time to the reception of test signals from all the lines of the transmission line 13 by the lines of the transmission line 13 on the signal reception side and delays the signals transmitted through the transmission line 13 by the stored times to correct the inter-signal skew.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はSCSIバス等の並列信
号伝送路にて発生する信号間スキューを補正する機能を
有する並列信号伝送装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel signal transmission device having a function of correcting a signal skew generated in a parallel signal transmission line such as a SCSI bus.

【0002】[0002]

【従来の技術】複数の信号を並列に伝送路を介して伝送
する場合、複数の信号は伝送中に信号間スキューが発生
する。特開平1ー149154号公報には、対向する装
置間で信号の授受を行う並列インターフェースにおい
て、伝送路で発生する信号間スキューを補正するように
したデータ転送方式が記載されている。このデータ転送
方式では、転送路は各信号に対して双方向独立の線路を
持つ全二重構成である。対向する装置には主従関係があ
り、主装置が制御のほとんどを行う。
2. Description of the Related Art When a plurality of signals are transmitted in parallel via a transmission line, a skew between the signals occurs during the transmission of the plurality of signals. Japanese Unexamined Patent Publication No. 1-149154 discloses a data transfer system in which a signal-to-device skew is corrected in a parallel interface in which signals are exchanged between opposing devices. In this data transfer method, the transfer path is a full-duplex configuration having bidirectional independent lines for each signal. Opposing devices have a master-slave relationship, and the main device performs most of the control.

【0003】このデータ転送方式の動作としては、ま
ず、主装置から従装置に回線の1本を使って試験信号を
送信する。従装置は受信した試験信号を全ての回線を通
じて主装置側へ折り返す。主装置は受信した試験信号の
回線毎の遅延量を測定することにより従装置から主装置
への信号伝送における信号間スキューを検知して補正す
る。次に、主装置から従装置に回線毎に試験信号を送信
する。従装置は受信した信号を回線毎に主装置に折り返
す。主装置は受信信号の回線毎の遅延量から今度は主装
置から従装置への信号伝送における信号間スキューを検
知して補正する。
In the operation of this data transfer system, first, a test signal is transmitted from the main device to the slave device using one of the lines. The slave device returns the received test signal to the master device side through all the lines. The main unit detects the delay between signals in the signal transmission from the slave unit to the main unit by measuring the delay amount for each line of the received test signal and corrects it. Next, a test signal is transmitted from the master device to the slave device for each line. The slave device returns the received signal to the master device for each line. The main device detects the signal-to-signal skew in the signal transmission from the main device to the slave device from the delay amount of the received signal for each line, and corrects it.

【0004】[0004]

【発明が解決しようとする課題】上記データ転送方式で
は、対向する装置からの折り返し信号によって信号間ス
キューを検知して補正するので、伝送路の信号伝送方向
が一方向のみの場合や、伝送路が半二重の構成になって
いて各信号が一つの回線を時分割で共有して双方向に伝
送する場合には適用できない。また、試験信号の送信側
は試験信号の受信側が試験信号を受信する準備ができて
から試験信号の送信を開始しないと、誤動作が起こって
試験信号遅延量の正しい測定ができないが、そのような
構成は特開平1ー149154号公報に記載されていな
い。また、双方向の信号間スキュー補正を行うのに試験
信号が少なくとも伝送路を2往復する時間を必要とし、
本来の信号伝送の効率を損なうことになりかねない。
In the above-mentioned data transfer method, since the signal-to-signal skew is detected and corrected by the return signal from the opposite device, when the signal transmission direction of the transmission line is only one direction, This is not applicable when the signal has a half-duplex configuration and each signal shares one line in a time division manner and transmits in both directions. In addition, if the test signal transmission side does not start the test signal transmission after the test signal reception side is ready to receive the test signal, a malfunction occurs and the test signal delay amount cannot be measured correctly. The structure is not described in JP-A-1-149154. Further, it takes at least two round trips of the test signal through the transmission path to perform bidirectional signal skew correction.
This may impair the original efficiency of signal transmission.

【0005】本発明は、伝送路の信号伝送方向が一方向
のみの場合や伝送路が半二重の構成になっている場合に
も適用でき、誤動作を防止できて本来の信号伝送の効率
を損なうことなく信号間スキューを正しく補正できる並
列信号伝送装置を提供することを目的とする。
The present invention can be applied to the case where the signal transmission direction of the transmission line is only one direction or the case where the transmission line has a half-duplex configuration, and it is possible to prevent malfunction and improve the original signal transmission efficiency. An object of the present invention is to provide a parallel signal transmission device that can correct skew between signals without damage.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、請求項1記載の発明は、複数の信号を並列に伝送路
を介して伝送する並列信号伝送装置において、信号送信
側にて試験信号を生成して該試験信号を前記伝送路の全
ての回線に同じタイミングで送信する試験信号送信手段
と、信号受信側にて前記伝送路の各回線毎に前記試験信
号を受信した時点から前記伝送路の全ての回線から前記
試験信号を受信するまでの時間を測定して記憶し、前記
伝送路の各回線で伝送された前記複数の信号に対してそ
れぞれ前記記憶した時間分だけ遅延をかけることによ
り、前記複数の信号の伝送中に発生した信号間スキュー
を補正する信号間スキュー補正手段とを備えたことを特
徴とするものである。
In order to achieve the above object, the invention according to claim 1 is a parallel signal transmission apparatus for transmitting a plurality of signals in parallel via a transmission line, and a test signal is provided on the signal transmission side. Generating a test signal and transmitting the test signal to all the lines of the transmission path at the same timing, and the transmission from the time when the test signal is received for each line of the transmission line at the signal receiving side. Measuring and storing the time until the test signal is received from all the lines of the transmission line, and delaying each of the plurality of signals transmitted by each line of the transmission line by the stored time. According to the aspect of the invention, there is provided inter-signal skew correction means for correcting inter-signal skew that occurs during transmission of the plurality of signals.

【0007】請求項2記載の発明は、複数の信号を並列
に伝送路を介して伝送する並列信号伝送装置において、
試験信号の送信側にて試験信号の受信側に対して試験信
号を送信する前に試験信号の送信を知らせる要求信号を
送信し、試験信号の受信側にて前記要求信号を受信して
試験信号を受信する準備をした後に応答信号を試験信号
の送信側に返送し、試験信号の送信側にて前記応答信号
の受信を確認してから試験信号を前記伝送路の全ての回
線に同じタイミングで送信する信号間スキュー補正用信
号送受信手段と、試験信号の受信側にて前記伝送路の各
回線毎に前記試験信号を受信した時点から前記伝送路の
全ての回線から前記試験信号を受信するまでの時間を測
定して記憶し、前記伝送路の各回線で伝送された前記複
数の信号に対してそれぞれ前記記憶した時間分だけ遅延
をかけることにより、前記複数の信号の伝送中に発生し
た信号間スキューを補正する信号間スキュー補正手段と
を備えたことを特徴とするものである。
According to a second aspect of the present invention, there is provided a parallel signal transmission device for transmitting a plurality of signals in parallel via a transmission line,
The test signal transmitting side transmits a request signal to the test signal receiving side to inform the test signal transmitting side before transmitting the test signal, and the test signal receiving side receives the request signal and transmits the test signal. After returning to the test signal transmission side after preparing to receive the test signal, the test signal transmission side confirms the reception of the response signal and then sends the test signal to all lines of the transmission line at the same timing. Signal transmission / reception means for signal skew correction to be transmitted, and from the time of receiving the test signal for each line of the transmission line at the test signal receiving side until receiving the test signal from all the lines of the transmission line The signal generated during the transmission of the plurality of signals by measuring and storing the time, and delaying the plurality of signals transmitted by each line of the transmission path by the stored time. Inter-skew It is characterized in that a signal skew correcting means for correcting.

【0008】請求項3記載の発明は、複数の信号を並列
に伝送路を介して伝送し、この伝送路が半二重である並
列信号伝送装置において、前記伝送路の両側に設けられ
て相手側に対して試験信号の送信前に試験信号の送信を
知らせる要求信号を送信し、相手側からの要求信号を受
信して応答信号を相手側に返送し、相手側からの応答信
号を受信する2つの要求/応答信号送受信手段と、前記
伝送路の両側に設けられて前記2つの要求/応答信号送
受信手段のうち前記伝送路の同じ側に設けられた要求/
応答信号送受信手段の応答信号受信により試験信号を前
記伝送路の全ての回線に同じタイミングで送信し、前記
伝送路の各回線毎に前記試験信号を受信した時点から前
記伝送路の全ての回線から前記試験信号を受信するまで
の時間を測定して記憶し、前記伝送路の各回線で伝送さ
れてきた前記複数の信号に対してそれぞれ前記記憶した
時間分だけ遅延をかけることにより、前記複数の信号の
伝送中に発生した信号間スキューを補正する2つの信号
間スキュー補正手段とを備え、前記2つの要求/応答信
号送受信手段及び前記2つの信号間スキュー補正手段の
動作順位を予め決めておくことを特徴とするものであ
る。
According to a third aspect of the present invention, in a parallel signal transmission device in which a plurality of signals are transmitted in parallel via a transmission line, and the transmission line is half-duplex, the parallel signal transmission device is provided on both sides of the transmission line. Before sending the test signal to the side, it sends a request signal to notify the sending of the test signal, receives the request signal from the other party, sends back a response signal to the other party, and receives the response signal from the other party. Two request / response signal transmission / reception means and a request / response signal transmission / reception means provided on both sides of the transmission path and provided on the same side of the transmission path among the two request / response signal transmission / reception means.
The test signal is transmitted to all the lines of the transmission line at the same timing by receiving the response signal of the response signal transmitting / receiving means, and from the point of receiving the test signal for each line of the transmission line, from all the lines of the transmission line. The time until the test signal is received is measured and stored, and the plurality of signals transmitted by each line of the transmission path are delayed by the stored time respectively, thereby Two signal-to-signal skew correction means for correcting signal-to-signal skew generated during signal transmission are provided, and the order of operation of the two request / response signal transmission / reception means and the two signal-to-signal skew correction means is determined in advance. It is characterized by that.

【0009】請求項4記載の発明は、複数の信号を並列
に伝送路を介して伝送し、この伝送路が全二重である並
列信号伝送装置において、前記伝送路の両側に設けられ
て相手側に対して試験信号の送信前に試験信号の送信を
知らせる要求信号を送信し、相手側からの要求信号を受
信して応答信号を相手側に返送し、相手側からの応答信
号を受信する2つの要求/応答信号送受信手段と、前記
伝送路の両側に設けられて前記2つの要求/応答信号送
受信手段のうち前記伝送路の同じ側に設けられた要求/
応答信号送受信手段の応答信号受信により試験信号を前
記伝送路の全ての回線に同じタイミングで送信し、前記
伝送路の各回線毎に前記試験信号を受信した時点から前
記伝送路の全ての回線から前記試験信号を受信するまで
の時間を測定して記憶し、前記伝送路の各回線で伝送さ
れてきた前記複数の信号に対してそれぞれ前記記憶した
時間分だけ遅延をかけることにより、前記複数の信号の
伝送中に発生した信号間スキューを補正する2つの信号
間スキュー補正手段とを備え、前記2つの要求/応答信
号送受信手段の一方が前記要求信号を送信した場合に前
記2つの要求/応答信号送受信手段の他方も前記要求信
号を送信して前記2つの要求/応答信号送受信手段及び
前記2つの信号間スキュー補正手段が同時に双方向にて
同じ一連の動作を行うようにしたことを特徴とするもの
である。
According to a fourth aspect of the present invention, in a parallel signal transmission device in which a plurality of signals are transmitted in parallel via a transmission line, and the transmission line is full duplex, the parallel signal transmission device is provided on both sides of the transmission line. Before sending the test signal to the side, it sends a request signal to notify the sending of the test signal, receives the request signal from the other party, sends back a response signal to the other party, and receives the response signal from the other party. Two request / response signal transmission / reception means and a request / response signal transmission / reception means provided on both sides of the transmission path and provided on the same side of the transmission path among the two request / response signal transmission / reception means.
The test signal is transmitted to all the lines of the transmission line at the same timing by receiving the response signal of the response signal transmitting / receiving means, and from the point of receiving the test signal for each line of the transmission line, from all the lines of the transmission line. The time until the test signal is received is measured and stored, and the plurality of signals transmitted by each line of the transmission path are delayed by the stored time respectively, thereby Two signal-to-signal skew correction means for correcting signal-to-signal skew generated during signal transmission, wherein the two request / response signal transmission / reception means transmit / receive the request signal when one of the two request / response signal transmission / reception means transmits the request signal. The other of the signal transmitting / receiving means also transmits the request signal so that the two request / response signal transmitting / receiving means and the two signal skew correcting means simultaneously perform the same series of operations in both directions. It is characterized in that it has a Migihitsuji.

【0010】請求項5記載の発明は、請求項1,2,3
または4記載の並列信号伝送装置において、前記手段が
一連の動作を少なくとも電源投入時に行うことを特徴と
するものである。
The invention of claim 5 is the invention of claims 1, 2, and 3.
Alternatively, in the parallel signal transmission device according to the fourth aspect, the means performs a series of operations at least when the power is turned on.

【0011】請求項6記載の発明は、請求項1,2,
3,4または5記載の並列信号伝送装置において、前記
手段が一連の動作を所定時間毎に繰り返して行うことを
特徴とするものである。
The invention according to claim 6 is the same as claims 1, 2 and
In the parallel signal transmission device described in item 3, 4 or 5, the means repeats a series of operations at predetermined time intervals.

【0012】請求項7記載の発明は、請求項2,3,
4,5または6記載の並列信号伝送装置において、前記
信号間スキュー補正用信号送受信手段または前記要求/
応答信号送受信手段は前記伝送路が空き状態にあること
を確認して要求信号及び応答信号の送信を開始すること
を特徴とするものである。
The invention according to claim 7 is the invention according to claims 2, 3,
In the parallel signal transmission device according to 4, 5, or 6, the signal transmitting / receiving unit for skew correction between signals or the request / transmission means
The response signal transmitting / receiving means confirms that the transmission line is in an idle state and starts transmitting the request signal and the response signal.

【0013】請求項8記載の発明は、請求項2,3,
4,5,6または7記載の並列信号伝送装置において、
前記信号間スキュー補正用信号送受信手段または前記要
求/応答信号送受信手段は前記要求信号を受信すると前
記伝送路からの試験信号を遮断して外部に伝送しないよ
うにしたことを特徴とするものである。
The invention according to claim 8 is the invention according to claim 2, 3,
In the parallel signal transmission device according to 4, 5, 6 or 7,
When the request signal is received, the signal skew correction signal transmitting / receiving means or the request / response signal transmitting / receiving means blocks the test signal from the transmission path and does not transmit the signal to the outside. .

【0014】[0014]

【作用】請求項1記載の発明では、試験信号送信手段が
信号送信側にて試験信号を生成して該試験信号を伝送路
の全ての回線に同じタイミングで送信する。そして、信
号間スキュー補正手段は、信号受信側にて伝送路の各回
線毎に試験信号を受信した時点から伝送路の全ての回線
から試験信号を受信するまでの時間を測定して記憶し、
伝送路の各回線で伝送された複数の信号に対してそれぞ
れ記憶した時間分だけ遅延をかけることにより、複数の
信号の伝送中に発生した信号間スキューを補正する。
According to the first aspect of the present invention, the test signal transmitting means generates the test signal on the signal transmitting side and transmits the test signal to all lines of the transmission line at the same timing. Then, the signal-to-signal skew correction means measures and stores the time from the reception of the test signal for each line of the transmission line on the signal receiving side to the reception of the test signal from all the lines of the transmission line,
By delaying each of the plurality of signals transmitted through each line of the transmission path by the stored time, the signal-to-signal skew occurring during the transmission of the plurality of signals is corrected.

【0015】請求項2記載の発明では、信号間スキュー
補正用信号送受信手段は、試験信号の送信側にて試験信
号の受信側に対して試験信号を送信する前に試験信号の
送信を知らせる要求信号を送信し、試験信号の受信側に
て要求信号を受信して試験信号を受信する準備をした後
に応答信号を試験信号の送信側に返送し、試験信号の送
信側にて応答信号の受信を確認してから試験信号を伝送
路の全ての回線に同じタイミングで送信する。そして、
信号間スキュー補正手段は、試験信号の受信側にて伝送
路の各回線毎に試験信号を受信した時点から伝送路の全
ての回線から試験信号を受信するまでの時間を測定して
記憶し、伝送路の各回線で伝送された複数の信号に対し
てそれぞれ記憶した時間分だけ遅延をかけることによ
り、複数の信号の伝送中に発生した信号間スキューを補
正する。
According to another aspect of the present invention, the signal transmitting / receiving means for inter-signal skew correction requests the transmission side of the test signal to notify the reception side of the test signal of the transmission of the test signal to the reception side of the test signal. After sending the signal, the test signal receiving side receives the request signal and prepares to receive the test signal, then returns the response signal to the test signal transmitting side, and the test signal transmitting side receives the response signal. After confirming, the test signal is transmitted to all lines of the transmission line at the same timing. And
The signal-to-signal skew correction means measures and stores the time from the reception of the test signal for each line of the transmission line on the reception side of the test signal to the reception of the test signal from all the lines of the transmission line, By delaying each of the plurality of signals transmitted through each line of the transmission path by the stored time, the signal-to-signal skew occurring during the transmission of the plurality of signals is corrected.

【0016】請求項3記載の発明では、伝送路の両側に
設けられた2つの要求/応答信号送受信手段は、相手側
に対して試験信号の送信前に試験信号の送信を知らせる
要求信号を送信し、相手側からの要求信号を受信して応
答信号を相手側に返送し、相手側からの応答信号を受信
する。そして、伝送路の両側に設けられた2つの信号間
スキュー補正手段は、2つの要求/応答信号送受信手段
のうち伝送路の同じ側に設けられた要求/応答信号送受
信手段の応答信号受信により試験信号を伝送路の全ての
回線に同じタイミングで送信し、伝送路の各回線毎に試
験信号を受信した時点から伝送路の全ての回線から試験
信号を受信するまでの時間を測定して記憶し、伝送路の
各回線で伝送されてきた複数の信号に対してそれぞれ記
憶した時間分だけ遅延をかけることにより、複数の信号
の伝送中に発生した信号間スキューを補正する。これら
の2つの要求/応答信号送受信手段及び2つの信号間ス
キュー補正手段は予め決めておいた動作順位で動作す
る。
According to the third aspect of the present invention, the two request / response signal transmitting / receiving means provided on both sides of the transmission path transmit a request signal for notifying the other side of the transmission of the test signal before transmitting the test signal. Then, the request signal from the other party is received, the response signal is sent back to the other party, and the response signal from the other party is received. The two signal skew correction means provided on both sides of the transmission line are tested by receiving response signals from the request / response signal transmission / reception means provided on the same side of the transmission line among the two request / response signal transmission / reception means. The signal is sent to all the lines of the transmission line at the same timing, and the time from when the test signal is received to each line of the transmission line until the test signal is received from all the lines of the transmission line is measured and stored. , The signal-to-signal skew generated during the transmission of the plurality of signals is corrected by delaying the plurality of signals transmitted through each line of the transmission path by the stored time. These two request / response signal transmitting / receiving means and the two signal skew correcting means operate in a predetermined operation order.

【0017】請求項4記載の発明では、伝送路の両側に
設けられた2つの要求/応答信号送受信手段は、相手側
に対して試験信号の送信前に試験信号の送信を知らせる
要求信号を送信し、相手側からの要求信号を受信して応
答信号を相手側に返送し、相手側からの応答信号を受信
する。そして、伝送路の両側に設けられた2つの信号間
スキュー補正手段は、2つの要求/応答信号送受信手段
のうち伝送路の同じ側に設けられた要求/応答信号送受
信手段の応答信号受信により試験信号を伝送路の全ての
回線に同じタイミングで送信し、伝送路の各回線毎に前
記試験信号を受信した時点から伝送路の全ての回線から
試験信号を受信するまでの時間を測定して記憶し、伝送
路の各回線で伝送されてきた複数の信号に対してそれぞ
れ記憶した時間分だけ遅延をかけることにより、複数の
信号の伝送中に発生した信号間スキューを補正する。2
つの要求/応答信号送受信手段の一方が要求信号を送信
した場合に2つの要求/応答信号送受信手段の他方も要
求信号を送信して2つの要求/応答信号送受信手段及び
2つの信号間スキュー補正手段が同時に双方向にて同じ
一連の動作を行う。
According to another aspect of the invention, the two request / response signal transmitting / receiving means provided on both sides of the transmission line transmit a request signal to the other side to notify the transmission of the test signal before transmitting the test signal. Then, the request signal from the other party is received, the response signal is sent back to the other party, and the response signal from the other party is received. The two signal skew correction means provided on both sides of the transmission line are tested by receiving response signals from the request / response signal transmission / reception means provided on the same side of the transmission line among the two request / response signal transmission / reception means. The signal is sent to all the lines of the transmission line at the same timing, and the time from the point of receiving the test signal to the reception of the test signal from all the lines of the transmission line is measured and stored. Then, the signal-to-signal skew that occurs during the transmission of the plurality of signals is corrected by delaying the plurality of signals transmitted through each line of the transmission path by the stored time. Two
When one of the two request / response signal transmitting / receiving means transmits the request signal, the other of the two request / response signal transmitting / receiving means also transmits the request signal so that the two request / response signal transmitting / receiving means and the two signal skew correcting means Simultaneously perform the same series of operations in both directions.

【0018】請求項5記載の発明では、請求項1,2,
3または4記載の並列信号伝送装置において、前記手段
が一連の動作を少なくとも電源投入時に行う。
In the invention described in claim 5, claims 1, 2,
In the parallel signal transmission device described in 3 or 4, the means performs a series of operations at least when the power is turned on.

【0019】請求項6記載の発明では、請求項1,2,
3,4または5記載の並列信号伝送装置において、前記
手段が一連の動作を所定時間毎に繰り返して行う。
According to the invention of claim 6, claims 1, 2,
In the parallel signal transmission device described in 3, 4, or 5, the means repeats a series of operations at predetermined time intervals.

【0020】請求項7記載の発明では、請求項2,3,
4,5または6記載の並列信号伝送装置において、信号
間スキュー補正用信号送受信手段または要求/応答信号
送受信手段は伝送路が空き状態にあることを確認して要
求信号及び応答信号の送信を開始する。
According to the invention of claim 7, claims 2, 3,
In the parallel signal transmission device described in 4, 5, or 6, the signal transmission / reception means for signal skew correction or the request / response signal transmission / reception means confirms that the transmission path is in an idle state and starts transmission of the request signal and the response signal. To do.

【0021】請求項8記載の発明では、請求項2,3,
4,5,6または7記載の並列信号伝送装置において、
信号間スキュー補正用信号送受信手段または要求/応答
信号送受信手段は要求信号を受信すると伝送路からの試
験信号を遮断して外部に伝送しないようにする。
According to the invention described in claim 8,
In the parallel signal transmission device according to 4, 5, 6 or 7,
Upon reception of the request signal, the signal transmission / reception means for signal skew correction or the request / response signal transmission / reception means cuts off the test signal from the transmission path so that it is not transmitted to the outside.

【0022】[0022]

【実施例】図2は請求項1,2,5〜8記載の発明の実
施例の並列信号伝送装置(以後単に伝送装置と記す)を
用いたシステム構成の一例を示す。伝送装置11,12
は、伝送路13の両側に設けられ、端末機器14,15
にインターフェースコネクタによって接続される。端末
機器14は例えばホストコンピュータからなり、端末機
器15は例えばプリンタからなる。伝送装置11,12
は端末機器14,15と伝送路13との間の信号伝送を
行う。
FIG. 2 shows an example of a system configuration using a parallel signal transmission apparatus (hereinafter simply referred to as a transmission apparatus) according to an embodiment of the invention described in claims 1, 2, 5-8. Transmission device 11, 12
Are provided on both sides of the transmission line 13, and are connected to the terminal devices 14, 15
Connected by an interface connector. The terminal device 14 is, for example, a host computer, and the terminal device 15 is, for example, a printer. Transmission device 11, 12
Performs signal transmission between the terminal devices 14 and 15 and the transmission path 13.

【0023】図1は伝送装置11,12の構成例を示
す。この伝送装置11,12は、請求項1,2,5〜8
記載の発明の実施例であり、制御回路16及び信号伝送
回路171〜17nを有する。制御回路16は要求信号及
び応答信号の送受信や試験信号の生成などを行う部分で
ある。信号伝送回路171〜17nは、端末機器14,1
5と伝送路13の各回線131〜13nとの間の複数の信
号の中継伝送を行うものであり、各信号毎に設けられて
いる。
FIG. 1 shows a configuration example of the transmission devices 11 and 12. The transmission devices 11, 12 are claimed in claims 1, 2, 5-8.
It is an embodiment of the described invention, and has a control circuit 16 and signal transmission circuits 17 1 to 17 n . The control circuit 16 is a part that transmits and receives request signals and response signals and generates test signals. The signal transmission circuits 17 1 to 17 n are the terminal devices 14 and 1
5 and the lines 13 1 to 13 n of the transmission line 13 are relayed for transmission of a plurality of signals, and are provided for each signal.

【0024】図3は伝送装置11,12のうち試験信号
を送信する側の伝送装置における制御回路16の構成例
を示す。抵抗18とコンデンサ19は直流電源電源Vc
cと接地点との間に直列に接続され、抵抗18とコンデ
ンサ19の接続点がヒステリシス特性を有するバッファ
20の入力側に接続されている。電源が投入されると、
コンデンサ19が抵抗18を通して電源Vccから充電
され、バッファ20の入力電圧がゆるやかに上昇する。
バッファ20の入力電圧が所定のレベルを超えると、バ
ッファ20の出力電圧が高レベル(以下Hと称する)に
遷移する。このとき、後述するタイマー21の出力信号
S6が低レベル(以下Lと称する)であるとすると、ア
ンド回路22はバッファ20の出力信号が入力されると
共に、タイマー21の出力信号S6がインバータ23で
反転されて入力されてこれらのアンドをとることにより
出力信号S1がHとなる。
FIG. 3 shows an example of the configuration of the control circuit 16 in the transmission device of the transmission devices 11 and 12 which transmits the test signal. The resistor 18 and the capacitor 19 are DC power source Vc
It is connected in series between c and the ground point, and the connection point of the resistor 18 and the capacitor 19 is connected to the input side of the buffer 20 having a hysteresis characteristic. When the power is turned on,
The capacitor 19 is charged from the power supply Vcc through the resistor 18, and the input voltage of the buffer 20 gradually rises.
When the input voltage of the buffer 20 exceeds a predetermined level, the output voltage of the buffer 20 transitions to a high level (hereinafter referred to as H). At this time, if the output signal S6 of the timer 21 described later is at a low level (hereinafter referred to as L), the AND circuit 22 receives the output signal of the buffer 20 and the output signal S6 of the timer 21 is output by the inverter 23. The output signal S1 becomes H by being inverted and input and taking the AND of these.

【0025】立ち上がり遷移検出回路24はアンド回路
22からの入力信号S1のLからHへの遷移を検出して
出力信号S2がLからHになる。一方、伝送路空き検出
回路25は、端末機器14,15と伝送路13との間で
一切の伝送信号が無くて伝送路13が空き状態であるこ
とを検出すると、出力信号S3がLからHになる。アン
ド回路26は立ち上がり遷移検出回路24からの入力信
号S2と伝送路空き検出回路25からの入力信号S3と
のアンドをとって要求信号として出力する。したがっ
て、伝送路13の各回線131〜13nのいずれか1つで
も信号伝送中であれば要求信号はHにならない。要求信
号は試験信号を送信する前に試験信号の送信を知らせる
信号である。伝送路空き検出回路25はアンド回路26
からの要求信号がHになっている期間中は出力信号S3
をHに保持する。アンド回路26からの要求信号は伝送
装置11,12のうち試験信号を受信する側の伝送装置
における制御回路16へ制御信号ラインを介して送信さ
れる。
The rising transition detection circuit 24 detects the transition of the input signal S1 from the AND circuit 22 from L to H, and the output signal S2 changes from L to H. On the other hand, when the transmission path idle detection circuit 25 detects that there is no transmission signal between the terminal devices 14 and 15 and the transmission path 13 and the transmission path 13 is in the idle state, the output signal S3 changes from L to H. become. The AND circuit 26 takes the AND of the input signal S2 from the rising transition detection circuit 24 and the input signal S3 from the transmission path idle detection circuit 25 and outputs it as a request signal. Therefore, the request signal does not become H if any one of the lines 13 1 to 13 n of the transmission line 13 is transmitting a signal. The request signal is a signal notifying the transmission of the test signal before transmitting the test signal. The transmission path idle detection circuit 25 is an AND circuit 26.
Output signal S3 during the period when the request signal from H is H.
Is held at H. The request signal from the AND circuit 26 is transmitted via the control signal line to the control circuit 16 in the transmission device of the transmission devices 11 and 12 which receives the test signal.

【0026】アンド回路27はアンド回路26からの要
求信号が入力されると共に、伝送装置11,12のうち
試験信号を受信する側の伝送装置における制御回路16
からの応答信号が入力されてこれらのアンドをとる。試
験信号発生回路28は、アンド回路26からの要求信号
に対して伝送装置11,12のうち試験信号を受信する
側の伝送装置における制御回路16から応答信号が返っ
て要求信号と応答信号が同時にHになってアンド回路2
7からの入力信号S4がHになると、すなわち、応答信
号の受信を確認すると、試験信号の出力を開始する。こ
の試験信号は伝送路13の全ての回線131〜13nに同
じタイミングで送出される。
The AND circuit 27 receives the request signal from the AND circuit 26, and the control circuit 16 in the transmission device of the transmission devices 11 and 12 which receives the test signal.
The response signal from is taken and these ANDs are taken. In response to the request signal from the AND circuit 26, the test signal generation circuit 28 returns a response signal from the control circuit 16 in the transmission device on the side of the transmission devices 11 and 12 that receives the test signal, and the request signal and the response signal are sent simultaneously. Become H and AND circuit 2
When the input signal S4 from 7 becomes H, that is, when the reception of the response signal is confirmed, the output of the test signal is started. This test signal is sent to all the lines 13 1 to 13 n of the transmission line 13 at the same timing.

【0027】終了検出回路29は伝送装置11,12の
うち試験信号を受信する側の伝送装置における制御回路
16からの応答信号がHからLになるのを検出して出力
信号S5をLからHにする。立ち上がり遷移検出回路2
4は終了検出回路29からの入力信号S5がHになるこ
とによりリセットされて出力信号S2がLになる。これ
によってアンド回路26からの要求信号がLになる。終
了検出回路29は、アンド回路26からの要求信号がL
になることによりリセットされ、出力信号S5がLにな
る。したがって、信号S5は一時的にHになるだけであ
る。
The end detection circuit 29 detects that the response signal from the control circuit 16 in the transmission device on the side receiving the test signal of the transmission devices 11 and 12 changes from H to L and outputs the output signal S5 from L to H. To Rising transition detection circuit 2
4 is reset when the input signal S5 from the end detection circuit 29 becomes H, and the output signal S2 becomes L. As a result, the request signal from the AND circuit 26 becomes L. The end detection circuit 29 receives the request signal from the AND circuit 26 as L
Then, the output signal S5 goes low. Therefore, the signal S5 only goes high temporarily.

【0028】タイマー21は、終了検出回路29からの
入力信号S5がHになると起動し、それから所定の時間
を経過すると出力信号S6がLからHになる。ただし、
タイマー21は出力信号S6がHになることによって自
身をリセットするので、信号S6はすぐにLになる。タ
イマー21の出力信号S6はインバータ23で反転され
てアンド回路22に入力されるが、バッファ20の出力
信号は既にHになっていて変化しないから、アンド回路
22の出力信号S1が再び立ち上がり遷移を生じ、これ
によって上述と同じ動作が繰り返される。
The timer 21 is activated when the input signal S5 from the end detection circuit 29 becomes H, and the output signal S6 changes from L to H when a predetermined time has elapsed after that. However,
Since the timer 21 resets itself when the output signal S6 goes high, the signal S6 goes low immediately. The output signal S6 of the timer 21 is inverted by the inverter 23 and input to the AND circuit 22, but the output signal of the buffer 20 is already H and does not change. Therefore, the output signal S1 of the AND circuit 22 rises again. Occurs, which causes the same operation as described above to be repeated.

【0029】図4は伝送装置11,12のうち試験信号
を受信する側の伝送装置における制御回路16の構成例
を示す。この制御回路16は伝送路空き検出回路30、
遅延設定終了検出回路31、インバータ32及びアンド
回路33を有する。伝送路空き検出回路30は、上記伝
送路空き検出回路25と全く同じものである。ただし、
伝送路空き検出回路30は要求信号の代りにアンド回路
33からの応答信号が入力される。
FIG. 4 shows an example of the configuration of the control circuit 16 in the transmission device of the transmission devices 11 and 12 which receives the test signal. The control circuit 16 includes a transmission line idle detection circuit 30,
It has a delay setting end detection circuit 31, an inverter 32, and an AND circuit 33. The transmission line idle detection circuit 30 is exactly the same as the transmission line idle detection circuit 25. However,
The response signal from the AND circuit 33 is input to the transmission path idle detection circuit 30 instead of the request signal.

【0030】遅延設定終了検出回路31は、伝送装置1
1,12のうち試験信号を送信する側の伝送装置におけ
る制御回路16からの要求信号が入力され、この要求信
号がHになって伝送路13の全ての回線131〜13n
らの信号(試験信号)を受信したことを検出すると、出
力信号S8をHにする。アンド回路33は、遅延設定終
了検出回路31の出力信号S8がインバータ32で反転
されて入力されると共に、伝送装置11,12のうち試
験信号を送信する側の伝送装置における制御回路16か
らの要求信号及び伝送路空き検出回路30の出力信号S
7が入力され、これらのアンドをとって応答信号として
出力する。したがって、この制御回路は要求信号がHに
なると、伝送路13の全ての回線131〜13nの伝送信
号が無いことを確認して応答信号をHにすることにな
り、つまり、試験信号を受信する準備をした後に応答信
号をHにすることになる。アンド回路33からの応答信
号は、遅延設定終了検出回路31の出力信号S8がHに
なると、Lになる。アンド回路33からの応答信号は伝
送装置11,12のうち試験信号を送信する側の伝送装
置における制御回路16へ制御信号ラインを介して送信
される。
The delay setting end detection circuit 31 is used in the transmission device 1.
A request signal from the control circuit 16 in the transmission device on the transmission side of the test signal of 1 and 12 is input, the request signal becomes H, and signals from all the lines 13 1 to 13 n of the transmission line 13 ( When it is detected that the test signal) has been received, the output signal S8 is set to H. The AND circuit 33 receives the output signal S8 of the delay setting end detection circuit 31 after being inverted and input by the inverter 32, and requests from the control circuit 16 in the transmission device of the transmission devices 11 and 12 that transmits the test signal. Signal and output signal S of the transmission path idle detection circuit 30
7 is input, and these ANDs are taken and output as a response signal. Therefore, when the request signal becomes H, this control circuit confirms that there is no transmission signal of all the lines 13 1 to 13 n of the transmission line 13 and sets the response signal to H, that is, the test signal. The response signal is set to H after preparation for reception. The response signal from the AND circuit 33 becomes L when the output signal S8 of the delay setting end detection circuit 31 becomes H. The response signal from the AND circuit 33 is transmitted via the control signal line to the control circuit 16 in the transmission device of the transmission devices 11 and 12 that transmits the test signal.

【0031】図5は伝送装置11,12のうち試験信号
を送信する側の伝送装置における信号伝送回路171
17nの一例を示す。この信号伝送回路171〜17
nは、それぞれアンド回路34,35、インバータ36
及びオア回路37を有し、端末機器から伝送路13へ送
出される信号と試験信号とを切り換えて伝送路13へ送
出する。
FIG. 5 shows the signal transmission circuits 17 1 to 17 1 -in the transmission device of the transmission devices 11 and 12 which transmits the test signal.
17 n shows an example. This signal transmission circuit 17 1 to 17
n is an AND circuit 34, 35 and an inverter 36, respectively.
It also has an OR circuit 37, and switches the signal sent from the terminal device to the transmission line 13 and the test signal and sends it to the transmission line 13.

【0032】即ち、端末機器から伝送路13へ送出され
る信号は、伝送装置11,12のうち試験信号を送信す
る側の伝送装置における制御回路16からの要求信号が
Lである時にインバータ36の出力信号によりアンド回
路34を通り、オア回路37を通って伝送路13へ送出
される。また、伝送装置11,12のうち試験信号を送
信する側の伝送装置における制御回路16からの要求信
号がHになった時には、インバータ36の出力信号がL
になって端末機器から伝送路13への信号がアンド回路
34で遮断される。同時に、伝送装置11,12のうち
試験信号を送信する側の伝送装置における制御回路16
からの試験信号は、伝送装置11,12のうち試験信号
を送信する側の伝送装置における制御回路16からの要
求信号によりアンド回路35を通り、オア回路37を通
って伝送路13へ送出される。
That is, the signal sent from the terminal device to the transmission line 13 is output from the inverter 36 when the request signal from the control circuit 16 in the transmission device of the transmission devices 11 and 12 that transmits the test signal is L. The output signal passes through the AND circuit 34 and the OR circuit 37 and is sent to the transmission path 13. Further, when the request signal from the control circuit 16 in the transmission device on the side transmitting the test signal of the transmission devices 11 and 12 becomes H, the output signal of the inverter 36 becomes L.
Then, the signal from the terminal device to the transmission path 13 is blocked by the AND circuit 34. At the same time, the control circuit 16 in the transmission device of the transmission devices 11 and 12 that transmits the test signal
From the control circuit 16 in the transmission device that transmits the test signal among the transmission devices 11 and 12, passes through the AND circuit 35, and is transmitted to the transmission path 13 through the OR circuit 37. .

【0033】図6は伝送装置11,12のうち試験信号
を受信する側の伝送装置における信号伝送回路171
17nの一例を示す。この信号伝送回路171〜17
nは、それぞれスキュー補正回路38、インバータ39
及びアンド回路40を有する。伝送装置11,12のう
ち試験信号を受信する側の伝送装置における制御回路1
6からの応答信号はスキュー補正回路38に入力される
と共に、インバータ39で反転されてアンド回路40に
入力される。伝送路13の回線131〜13nからの信号
(試験信号)はスキュー補正回路38により遅延され、
スキュー補正回路38は応答信号がHになると伝送路1
3からの信号に対する遅延量を段階的に増していく。そ
して、スキュー補正回路38は伝送路13からの信号に
対する遅延量を上記遅延設定終了検出回路31からの入
力信号S8がHになった時点の遅延量で固定する。応答
信号がLになると、伝送路13からの信号は、スキュー
補正回路38にてその固定した遅延量だけ遅延され、イ
ンバータ39の出力信号によりアンド回路40を通って
端末機器へ送出される。
FIG. 6 shows the signal transmission circuits 17 1 to 17 1 -in the transmission device on the side receiving the test signal among the transmission devices 11 and 12.
17 n shows an example. This signal transmission circuit 17 1 to 17
n is the skew correction circuit 38 and the inverter 39, respectively.
And AND circuit 40. Control circuit 1 in the transmission device of the transmission devices 11 and 12 that receives the test signal
The response signal from 6 is input to the skew correction circuit 38, inverted by the inverter 39, and input to the AND circuit 40. Signals (test signals) from the lines 13 1 to 13 n of the transmission line 13 are delayed by the skew correction circuit 38,
When the response signal becomes H, the skew correction circuit 38 transmits the transmission line 1
The delay amount with respect to the signal from 3 is gradually increased. Then, the skew correction circuit 38 fixes the delay amount for the signal from the transmission line 13 at the delay amount at the time when the input signal S8 from the delay setting end detection circuit 31 becomes H. When the response signal becomes L, the signal from the transmission line 13 is delayed by the fixed delay amount in the skew correction circuit 38, and is output to the terminal device through the AND circuit 40 by the output signal of the inverter 39.

【0034】図7は上記スキュー補正回路38の構成例
を示す。スキュー補正回路38はリセット回路41、カ
ウンタ42、シフトレジスタ43、デコーダ44及びマ
ルチプレクサ45からなる。リセット回路41は、伝送
装置11,12のうち試験信号を受信する側の伝送装置
における制御回路16からの応答信号を受信すると、一
時的に出力信号S10をHにする。カウンタ42は、リ
セット回路41からの入力信号S10がLのときに、伝
送路13からの信号の受信開始から上記遅延設定終了検
出回路31からの入力信号S8がHになるまでの間に入
力されたクロック信号をカウントすることで、試験信号
を受信した時点から伝送路13の全ての回線131〜1
nから試験信号を受信するまでの時間を測定して記憶
し、そのカウント値をmビットのバイナリデータS11
として出力する。また、カウンタ42は、リセット回路
41からの入力信号S10がHになると、リセットされ
て出力信号S11を全て0にする。
FIG. 7 shows a configuration example of the skew correction circuit 38. The skew correction circuit 38 includes a reset circuit 41, a counter 42, a shift register 43, a decoder 44, and a multiplexer 45. When the reset circuit 41 receives the response signal from the control circuit 16 in the transmission device of the transmission devices 11 and 12 which receives the test signal, the reset circuit 41 temporarily sets the output signal S10 to H. When the input signal S10 from the reset circuit 41 is L, the counter 42 is input from the start of receiving the signal from the transmission path 13 until the input signal S8 from the delay setting end detection circuit 31 becomes H. By counting the clock signals, all the lines 13 1 to 1 of the transmission line 13 from the time when the test signal is received.
The time from the reception of the test signal from 3 n is measured and stored, and the count value is stored as m-bit binary data S11.
Output as Further, the counter 42 is reset when the input signal S10 from the reset circuit 41 becomes H and resets all the output signals S11 to 0.

【0035】シフトレジスタ43は、伝送路13からの
信号をクロック信号に同期して順次に遅らせ、この順次
に遅らせた信号S12をpビット並列に出力する。デコ
ーダ44はカウンタ42からのバイナリデータS11を
デコードしてpビットの出力信号S13のうちバイナリ
データS11に相当するビットだけをHにする。マルチ
プレクサ45はシフトレジスタ43からのpビットの信
号S12のうちデコーダ44の出力信号S13のうちH
になったビットに対応するものを選択して出力信号S9
として出力する。
The shift register 43 sequentially delays the signal from the transmission path 13 in synchronization with the clock signal, and outputs the sequentially delayed signal S12 in p bits in parallel. The decoder 44 decodes the binary data S11 from the counter 42 and sets only the bit corresponding to the binary data S11 in the p-bit output signal S13 to H level. The multiplexer 45 outputs H of the output signal S13 of the decoder 44 out of the p-bit signal S12 from the shift register 43.
Output signal S9 by selecting the one corresponding to the bit
Output as

【0036】このシステムにおける伝送装置11,12
は、請求項1記載の発明の実施例であって、複数の信号
を並列に伝送路13を介して伝送する並列信号伝送装置
において、信号送信側にて試験信号を生成して該試験信
号を伝送路13の全ての回線131〜13nに同じタイミ
ングで送信する試験信号送信手段としての試験信号発生
回路28と、信号受信側にて伝送路13の各回線131
〜13n毎に試験信号を受信した時点から伝送路13の
全ての回線131〜13nから試験信号を受信するまでの
時間を測定して記憶し、伝送路13の各回線131〜1
nで伝送された複数の信号に対してそれぞれ記憶した
時間分だけ遅延をかけることにより、複数の信号の伝送
中に発生した信号間スキューを補正する信号間スキュー
補正手段としての信号伝送回路(リセット回路41、カ
ウンタ42、シフトレジスタ43、デコーダ44及びマ
ルチプレクサ45からなるスキュー補正回路38と、イ
ンバータ39と、アンド回路40とを有する信号伝送回
路)とを備えたので、伝送路の信号伝送方向が一方向の
みの場合にも適用できる。
Transmission devices 11, 12 in this system
Is an embodiment of the invention according to claim 1, wherein in a parallel signal transmission device for transmitting a plurality of signals in parallel via the transmission path 13, a test signal is generated at the signal transmission side to generate the test signal. A test signal generating circuit 28 as a test signal transmitting means for transmitting to all the lines 13 1 to 13 n of the transmission line 13 at the same timing, and each line 13 1 of the transmission line 13 at the signal receiving side.
Every 13 to 13 n , the time from the reception of the test signal to the reception of the test signal from all the lines 13 1 to 13 n of the transmission line 13 is measured and stored, and each line 13 1 to 1 of the transmission line 13 is stored.
A signal transmission circuit as an inter-signal skew correction means for correcting the inter-signal skew generated during the transmission of the plurality of signals by delaying each of the plurality of signals transmitted by 3 n by the stored time. Since the skew correction circuit 38 including the reset circuit 41, the counter 42, the shift register 43, the decoder 44, and the multiplexer 45, and the signal transmission circuit (including the inverter 39 and the AND circuit 40) are provided, the signal transmission direction of the transmission path. It can also be applied to the case where is only one direction.

【0037】また、このシステムにおける伝送装置1
1,12は、請求項2記載の発明の実施例であって、複
数の信号を並列に伝送路13を介して伝送する並列信号
伝送装置において、試験信号の送信側にて試験信号の受
信側に対して試験信号を送信する前に試験信号の送信を
知らせる要求信号を送信し、試験信号の受信側にて要求
信号を受信して試験信号を受信する準備をした後に応答
信号を試験信号の送信側に返送し、試験信号の送信側に
て応答信号の受信を確認してから試験信号を伝送路13
の全ての回線131〜13nに同じタイミングで送信する
信号間スキュー補正用信号送受信手段としての図3及び
図4に示す伝送装置11,12における制御回路16
と、試験信号の受信側にて伝送路13の各回線131
13n毎に試験信号を受信した時点から伝送路13の全
ての回線131〜13nから試験信号を受信するまでの時
間を測定して記憶し、伝送路13の各回線131〜13n
で伝送された複数の信号に対してそれぞれ記憶した時間
分だけ遅延をかけることにより、複数の信号の伝送中に
発生した信号間スキューを補正する信号間スキュー補正
手段としての信号伝送回路(リセット回路41、カウン
タ42、シフトレジスタ43、デコーダ44及びマルチ
プレクサ45からなるスキュー補正回路38と、インバ
ータ39と、アンド回路40とを有する信号伝送回路)
とを備えたので、試験信号の受信側にて要求信号を受信
して試験信号を受信する準備をした後に応答信号を試験
信号の送信側に返送することで誤動作を防止することが
できる。
Further, the transmission device 1 in this system
1 and 12 are embodiments of the invention according to claim 2, wherein in the parallel signal transmission device for transmitting a plurality of signals in parallel via the transmission line 13, the test signal transmission side is the test signal reception side. To the test signal before sending the test signal, the test signal receiving side receives the request signal and prepares to receive the test signal. The test signal is returned to the transmission side, and the test signal transmission side confirms the reception of the response signal before transmitting the test signal to the transmission line 13.
Control circuit 16 in the transmission devices 11 and 12 shown in FIGS. 3 and 4 as signal skew correction signal transmitting / receiving means for transmitting to all the lines 13 1 to 13 n at the same timing.
And each line 13 1 of the transmission line 13 on the receiving side of the test signal
The time from the reception of the test signal every 13 n to the reception of the test signal from all the lines 13 1 to 13 n of the transmission line 13 is measured and stored, and each line 13 1 to 13 n of the transmission line 13 is measured and stored.
The signal transmission circuit (reset circuit) as a signal-to-signal skew correction means for correcting the signal-to-signal skew that occurs during the transmission of the plurality of signals by delaying the plurality of signals transmitted in 41, a counter 42, a shift register 43, a decoder 44, and a skew correction circuit 38 composed of a multiplexer 45, an inverter 39, and a signal transmission circuit having an AND circuit 40).
Since the test signal receiving side receives the request signal and prepares to receive the test signal, the response signal is returned to the test signal transmitting side to prevent malfunction.

【0038】また、このシステムにおける伝送装置1
1,12は、請求項5記載の発明の実施例であって、信
号間スキューを補正するための一連の動作を少なくとも
電源投入時にバッファ20の出力信号がHに遷移するこ
とにより行うので、ユーザの手をわずらわせることなく
確実に信号間スキューを補正することができ、信頼性の
高い信号伝送を実現できる。
Further, the transmission device 1 in this system
1 and 12 are the embodiments of the invention described in claim 5, and perform a series of operations for correcting the skew between signals at least when the output signal of the buffer 20 transits to H at the time of turning on the power source. The signal-to-signal skew can be reliably corrected without shifting the hand, and highly reliable signal transmission can be realized.

【0039】また、このシステムにおける伝送装置1
1,12は、請求項6記載の発明の実施例であって、終
了検出回路29の出力信号S5がHになってタイマー2
1が起動してタイマー21の出力信号S6がインバータ
23を介して立ち上がり遷移検出回路24に入力される
ことで立ち上がり遷移検出回路24がリセットされるこ
とにより、信号間スキューを補正するための一連の動作
が所定時間毎に繰り返して行われるので、信号間スキュ
ーが環境温度や電源電圧の変動により経時的に変化して
も信号間スキューの発生を抑えることができ、耐環境性
に優れた信号伝送を実現できる。
Further, the transmission device 1 in this system
1 and 12 are the embodiments of the invention described in claim 6, in which the output signal S5 of the end detection circuit 29 becomes H and the timer 2
1 is activated and the output signal S6 of the timer 21 is input to the rising transition detection circuit 24 via the inverter 23, whereby the rising transition detection circuit 24 is reset and a series of signals for correcting the skew between signals is output. Since the operation is repeated every predetermined time, it is possible to suppress the occurrence of signal-to-signal skew even if the signal-to-signal skew changes over time due to environmental temperature and power supply voltage fluctuations, and signal transmission with excellent environmental resistance. Can be realized.

【0040】また、このシステムにおける伝送装置1
1,12は、請求項7記載の発明の実施例であって、上
記信号間スキュー補正用信号送受信手段または要求/応
答信号送受信手段としての伝送装置11,12における
制御回路16は伝送路が空き状態にあることを伝送路空
き検出回路25,30により確認して要求信号及び応答
信号の送信を開始するので、たとえ信号間スキュー補正
動作を開始する時間になったときに何らかの信号伝送が
ある場合にはそれが完全に終了するまで待つことがで
き、本来の信号伝送の効率を損なうことなく信号間スキ
ューを正しく補正することができる。
Further, the transmission device 1 in this system
Reference numerals 1 and 12 are embodiments of the invention described in claim 7, and the control circuit 16 in the transmission device 11 or 12 as the signal skew correction signal transmitting / receiving means or request / response signal transmitting / receiving means has a free transmission path. Since the transmission path vacancy detection circuits 25 and 30 confirm that the status is in the state and start transmitting the request signal and the response signal, even if some signal transmission occurs at the time to start the inter-signal skew correction operation. In addition, it is possible to wait until it is completely completed, and the signal-to-signal skew can be correctly corrected without impairing the original signal transmission efficiency.

【0041】また、このシステムにおける伝送装置1
1,12は、請求項8記載の発明の実施例であって、上
記信号間スキュー補正用信号送受信手段または上記要求
/応答信号送受信手段は要求信号を受信すると伝送路1
3からの試験信号をアンド回路34及びインバータ36
により遮断して外部に伝送しないようにしたので、試験
信号によってシステムに何らかの障害が発生するのを防
止することができ、システムの信頼性を確保することが
できる。
Further, the transmission device 1 in this system
Reference numerals 1 and 12 are the embodiments of the invention described in claim 8, wherein the inter-signal skew correction signal transmission / reception means or the request / response signal transmission / reception means receives the request signal, and the transmission line 1
AND circuit 34 and inverter 36
Therefore, it is possible to prevent the system from being damaged by the test signal and to secure the reliability of the system because the test signal prevents the system from transmitting to the outside.

【0042】図8は請求項3記載の発明の実施例の伝送
装置を用いたシステム構成の一例における制御回路を示
す。このシステムでは、ホストコンピュータ14とプリ
ンタ15との間で双方向に信号が伝送され、伝送路13
が半二重の構成となっている場合の例である。要求信号
を先に送信する方の伝送装置、例えば伝送装置11にお
ける信号伝送回路171〜17n、要求信号を後で送信す
る方の伝送装置12における信号伝送回路171〜17n
は、上記図5及び図6に示すものの両方がそれぞれ用い
られて互いに要求信号、試験信号、応答信号、端末機器
14,15からの信号の送受信を行って信号間スキュー
補正動作を行う。また、伝送装置11における制御回路
16には図3及び図4に示すものが用いられて伝送装置
12における制御回路16には図4及び図8に示すもの
が用いられ、伝送装置11,12が互いに要求信号、試
験信号の送受信を行う。
FIG. 8 shows a control circuit in an example of a system configuration using the transmission device according to the third embodiment of the invention. In this system, signals are bidirectionally transmitted between the host computer 14 and the printer 15, and the transmission line 13
This is an example of the case of a half-duplex configuration. Transmission device who transmits a request signal earlier, for example, the signal transmission circuit 17 1 to 17 n in a transmission device 11, a signal transmission circuit in the transmission apparatus 12 of the person who transmits a request signal later 17 1 to 17 n
5 and FIG. 6 are used respectively to perform transmission / reception of a request signal, a test signal, a response signal, and signals from the terminal devices 14 and 15 to perform inter-signal skew correction operation. 3 and 4 are used for the control circuit 16 in the transmission device 11, and those shown in FIGS. 4 and 8 are used for the control circuit 16 in the transmission device 12. The request signal and the test signal are exchanged with each other.

【0043】この伝送装置12における制御回路16で
は、図3に示す制御回路において、タイマー21、イン
バータ23、伝送路空き検出回路25、アンド回路2
2,26、バッファ20、抵抗18、コンデンサ19が
省略され、伝送装置11からの要求信号がインバータ4
6で反転されて立ち上がり遷移検出回路24に入力信号
S1として入力されて立ち上がり遷移検出回路24の出
力信号がそのまま要求信号として制御信号ラインを介し
て伝送装置11の制御回路16へ送信される。したがっ
て、伝送装置12における立ち上がり遷移検出回路24
からの要求信号は伝送装置11からの要求信号がLにな
った後にHになる。
In the control circuit 16 in this transmission device 12, in the control circuit shown in FIG. 3, the timer 21, the inverter 23, the transmission path idle detection circuit 25, and the AND circuit 2 are provided.
2, 26, the buffer 20, the resistor 18, and the capacitor 19 are omitted, and the request signal from the transmission device 11 is transmitted to the inverter 4
Inverted at 6, the signal is input to the rising transition detection circuit 24 as the input signal S1 and the output signal of the rising transition detection circuit 24 is transmitted as it is as a request signal to the control circuit 16 of the transmission device 11 via the control signal line. Therefore, the rising transition detection circuit 24 in the transmission device 12
The request signal from H becomes H after the request signal from the transmission device 11 becomes L.

【0044】このシステムにおける伝送装置11,12
は、請求項3記載の発明の実施例であって、伝送路13
の両側に設けられて相手側に対して試験信号の送信前に
試験信号の送信を知らせる要求信号を送信し、相手側か
らの要求信号を受信して応答信号を相手側に返送し、相
手側からの応答信号を受信する2つの要求/応答信号送
受信手段としての図3及び図8に示す立ち上がり遷移検
出回路24及び試験信号発生回路28を含む制御回路
と、伝送路13の両側に設けられて2つの要求/応答信
号送受信手段のうち伝送路13の同じ側に設けられた要
求/応答信号送受信手段の応答信号受信により試験信号
を伝送路13の全ての回線131〜13nに同じタイミン
グで送信し、伝送路13の各回線131〜13n毎に試験
信号を受信した時点から伝送路13の全ての回線131
〜13nから試験信号を受信するまでの時間を測定して
記憶し、伝送路13の各回線131〜13nで伝送されて
きた複数の信号に対してそれぞれ記憶した時間分だけ遅
延をかけることにより、複数の信号の伝送中に発生した
信号間スキューを補正する2つの信号間スキュー補正手
段としての信号伝送回路(リセット回路41、カウンタ
42、シフトレジスタ43、デコーダ44及びマルチプ
レクサ45からなるスキュー補正回路38と、インバー
タ39と、アンド回路40とを有する信号伝送回路)と
を備え、2つの要求/応答信号送受信手段及び2つの信
号間スキュー補正手段の動作順位を予め決めておくの
で、伝送路が半二重の構成になっている場合にも適用で
きる。
Transmission devices 11, 12 in this system
Is an embodiment of the invention as set forth in claim 3, wherein the transmission line 13
A request signal is provided on both sides of the device to notify the other party of the test signal transmission before the test signal is transmitted, the request signal from the other party is received, and a response signal is sent back to the other party. The control circuit including the rising transition detection circuit 24 and the test signal generation circuit 28 shown in FIGS. 3 and 8 as two request / response signal transmitting / receiving means for receiving the response signal from Of the two request / response signal transmission / reception means, the request signal is received by the request / response signal transmission / reception means provided on the same side of the transmission path 13, and the test signal is transmitted to all the lines 13 1 to 13 n of the transmission path 13 at the same timing. All the lines 13 1 of the transmission line 13 from the time when the test signal is transmitted and the test signal is received for each of the lines 13 1 to 13 n of the transmission line 13.
The time from the reception of the test signal up to 13 n is measured and stored, and the plurality of signals transmitted through the lines 13 1 to 13 n of the transmission line 13 are delayed by the stored time. As a result, a signal transmission circuit (a skew composed of a reset circuit 41, a counter 42, a shift register 43, a decoder 44, and a multiplexer 45) as two inter-signal skew correction means for correcting inter-signal skew generated during transmission of a plurality of signals. A signal transmission circuit including a correction circuit 38, an inverter 39, and an AND circuit 40), and the operation order of the two request / response signal transmission / reception means and the two signal skew correction means is determined in advance. It is also applicable when the road has a half-duplex configuration.

【0045】また、請求項4記載の発明の実施例の伝送
装置を用いたシステム構成の一例は、ホストコンピュー
タ14とプリンタ15との間で双方向に信号が伝送さ
れ、伝送路13が全二重の構成となっている場合の例で
ある。このシステムでは、伝送装置11における信号伝
送回路171〜17n、伝送装置12における信号伝送回
路171〜17nは、上記図5及び図6に示すものの両方
がそれぞれ用いられて互いに要求信号、試験信号、応答
信号、端末機器14,15からの信号の送受信を行って
信号間スキュー補正動作を行う。また、伝送装置11に
おける制御回路16には図3及び図4に示すものが用い
られ、伝送装置12における制御回路16には図4に示
すものと、図8に示すものにおいてインバータ46を省
略して伝送装置11からの要求信号をそのまま立ち上が
り遷移検出回路24に入力信号S1として入力するよう
にしたものが用いられる。従って、伝送装置12の制御
回路16は、伝送装置11からの要求信号を受信する
と、それに続いて自らも要求信号を伝送装置11へ送信
して信号間スキューを補正するための一連の動作を開始
する。
Further, in an example of a system configuration using the transmission device of the embodiment of the invention described in claim 4, a signal is transmitted bidirectionally between the host computer 14 and the printer 15, and the transmission line 13 has all two lines. This is an example in the case of a heavy structure. In this system, the signal transmission circuit 17 1 to 17 n in a transmission device 11, the signal transmission circuit 17 1 to 17 n in the transmission device 12, FIG. 5 and to each other request signal both are respectively used the one shown in FIG. 6, Test signals, response signals, and signals from the terminal devices 14 and 15 are transmitted and received to perform skew correction operation between signals. 3 and 4 are used for the control circuit 16 in the transmission device 11, and the inverter 46 is omitted in the control circuit 16 in the transmission device 12 shown in FIGS. 4 and 8. Then, the request signal from the transmission device 11 is directly input to the rising transition detection circuit 24 as the input signal S1. Therefore, when the control circuit 16 of the transmission device 12 receives the request signal from the transmission device 11, subsequently, the control circuit 16 itself also transmits the request signal to the transmission device 11 to start a series of operations for correcting the signal skew. To do.

【0046】このシステムにおける伝送装置11,12
は、請求項4記載の発明の実施例であって、伝送路13
の両側に設けられて相手側に対して試験信号の送信前に
試験信号の送信を知らせる要求信号を送信し、相手側か
らの要求信号を受信して応答信号を相手側に返送し、相
手側からの応答信号を受信する2つの要求/応答信号送
受信手段としての図3及び図8に示す立ち上がり遷移検
出回路24及び試験信号発生回路28を含む制御回路1
6と、伝送路13の両側に設けられて2つの要求/応答
信号送受信手段のうち伝送路13の同じ側に設けられた
要求/応答信号送受信手段の応答信号受信により試験信
号を伝送路13の全ての回線131〜13nに同じタイミ
ングで送信し、伝送路13の各回線131〜13n毎に試
験信号を受信した時点から伝送路13の全ての回線13
1〜13nから試験信号を受信するまでの時間を測定して
記憶し、伝送路13の各回線で伝送されてきた複数の信
号に対してそれぞれ記憶した時間分だけ遅延をかけるこ
とにより、複数の信号の伝送中に発生した信号間スキュ
ーを補正する2つの信号間スキュー補正手段としての信
号伝送回路(リセット回路41、カウンタ42、シフト
レジスタ43、デコーダ44及びマルチプレクサ45か
らなるスキュー補正回路38と、インバータ39と、ア
ンド回路40とを有する信号伝送回路)とを備え、2つ
の要求/応答信号送受信手段の一方が要求信号を送信し
た場合に2つの要求/応答信号送受信手段の他方も要求
信号を送信して2つの要求/応答信号送受信手段及び2
つの信号間スキュー補正手段が同時に双方向にて同じ一
連の動作を行うようにしたので、試験信号が伝送路を1
往復する時間で双方向の信号伝送に対する信号間スキュ
ーを補正することができ、本来の信号伝送の効率を損な
うことなく信号間スキューを補正することができる。
Transmission devices 11, 12 in this system
Is an embodiment of the invention as set forth in claim 4, wherein the transmission line 13
A request signal is provided on both sides of the device to notify the other party of the test signal transmission before the test signal is transmitted, the request signal from the other party is received, and a response signal is sent back to the other party. A control circuit 1 including a rising transition detection circuit 24 and a test signal generation circuit 28 shown in FIGS. 3 and 8 as two request / response signal transmitting / receiving means for receiving a response signal from
6 and the test signal of the transmission path 13 by receiving the response signal of the request / response signal transmission / reception means provided on the same side of the transmission path 13 among the two request / response signal transmission / reception means provided on both sides of the transmission path 13. All lines 13 1 to 13 n are transmitted at the same timing, and a test signal is received for each line 13 1 to 13 n of the transmission line 13 from the time when the test signal is received.
The time from 1 to 13 n until the test signal is received is measured and stored, and a plurality of signals transmitted by each line of the transmission line 13 are delayed by the stored time, respectively. A signal transmission circuit (a skew correction circuit 38 including a reset circuit 41, a counter 42, a shift register 43, a decoder 44, and a multiplexer 45) as two signal-to-signal skew correction means for correcting the signal-to-signal skew generated during the transmission of the signal. , An inverter 39 and a signal transmission circuit having an AND circuit 40), and when one of the two request / response signal transmitting / receiving means transmits the request signal, the other of the two request / response signal transmitting / receiving means also receives the request signal. To send and receive two request / response signal transmitting / receiving means and 2
Since the two signal skew correcting means perform the same series of operations in both directions at the same time, the test signal is transmitted through the transmission line in one direction.
The signal-to-signal skew for bidirectional signal transmission can be corrected by the round-trip time, and the signal-to-signal skew can be corrected without impairing the original signal transmission efficiency.

【0047】[0047]

【発明の効果】以上のように請求項1記載の発明によれ
ば、複数の信号を並列に伝送路を介して伝送する並列信
号伝送装置において、信号送信側にて試験信号を生成し
て該試験信号を前記伝送路の全ての回線に同じタイミン
グで送信する試験信号送信手段と、信号受信側にて前記
伝送路の各回線毎に前記試験信号を受信した時点から前
記伝送路の全ての回線から前記試験信号を受信するまで
の時間を測定して記憶し、前記伝送路の各回線で伝送さ
れた前記複数の信号に対してそれぞれ前記記憶した時間
分だけ遅延をかけることにより、前記複数の信号の伝送
中に発生した信号間スキューを補正する信号間スキュー
補正手段とを備えたので、伝送路の信号伝送方向が一方
向のみの場合にも適用できる。
As described above, according to the first aspect of the present invention, in the parallel signal transmission device for transmitting a plurality of signals in parallel through the transmission path, the test signal is generated on the signal transmission side and the test signal is generated. Test signal transmitting means for transmitting a test signal to all the lines of the transmission line at the same timing, and all lines of the transmission line from the time when the test signal is received for each line of the transmission line on the signal receiving side. To measure and store the time from the reception of the test signal to the plurality of signals transmitted by each line of the transmission path, and delaying each of the plurality of signals by the stored time. Since the inter-signal skew correction means for correcting inter-signal skew generated during signal transmission is provided, the present invention can be applied even when the signal transmission direction of the transmission path is only one direction.

【0048】請求項2記載の発明によれば、複数の信号
を並列に伝送路を介して伝送する並列信号伝送装置にお
いて、試験信号の送信側にて試験信号の受信側に対して
試験信号を送信する前に試験信号の送信を知らせる要求
信号を送信し、試験信号の受信側にて前記要求信号を受
信して試験信号を受信する準備をした後に応答信号を試
験信号の送信側に返送し、試験信号の送信側にて前記応
答信号の受信を確認してから試験信号を前記伝送路の全
ての回線に同じタイミングで送信する信号間スキュー補
正用信号送受信手段と、試験信号の受信側にて前記伝送
路の各回線毎に前記試験信号を受信した時点から前記伝
送路の全ての回線から前記試験信号を受信するまでの時
間を測定して記憶し、前記伝送路の各回線で伝送された
前記複数の信号に対してそれぞれ前記記憶した時間分だ
け遅延をかけることにより、前記複数の信号の伝送中に
発生した信号間スキューを補正する信号間スキュー補正
手段とを備えたので、試験信号の受信側にて要求信号を
受信して試験信号を受信する準備をした後に応答信号を
試験信号の送信側に返送することで誤動作を防止するこ
とができる。
According to the second aspect of the present invention, in the parallel signal transmission device for transmitting a plurality of signals in parallel via the transmission path, the test signal transmitting side transmits the test signal to the test signal receiving side. Send a request signal to notify the transmission of the test signal before transmitting, and then return the response signal to the test signal transmitting side after receiving the request signal at the test signal receiving side and preparing to receive the test signal. , Signal-to-signal skew correction signal transmitting / receiving means for transmitting the test signal to all lines of the transmission path at the same timing after confirming the reception of the response signal at the test signal transmitting side, and the test signal receiving side. Then, the time from when the test signal is received for each line of the transmission path to when the test signal is received from all the lines of the transmission path is measured and stored, and is transmitted by each line of the transmission path. To the multiple signals And a signal-to-signal skew correction means for correcting the signal-to-signal skew that occurs during transmission of the plurality of signals by delaying the stored time by the stored time. Malfunctions can be prevented by returning the response signal to the test signal transmission side after receiving the signal and preparing to receive the test signal.

【0049】請求項3記載の発明によれば、複数の信号
を並列に伝送路を介して伝送し、この伝送路が半二重で
ある並列信号伝送装置において、前記伝送路の両側に設
けられて相手側に対して試験信号の送信前に試験信号の
送信を知らせる要求信号を送信し、相手側からの要求信
号を受信して応答信号を相手側に返送し、相手側からの
応答信号を受信する2つの要求/応答信号送受信手段
と、前記伝送路の両側に設けられて前記2つの要求/応
答信号送受信手段のうち前記伝送路の同じ側に設けられ
た要求/応答信号送受信手段の応答信号受信により試験
信号を前記伝送路の全ての回線に同じタイミングで送信
し、前記伝送路の各回線毎に前記試験信号を受信した時
点から前記伝送路の全ての回線から前記試験信号を受信
するまでの時間を測定して記憶し、前記伝送路の各回線
で伝送されてきた前記複数の信号に対してそれぞれ前記
記憶した時間分だけ遅延をかけることにより、前記複数
の信号の伝送中に発生した信号間スキューを補正する2
つの信号間スキュー補正手段とを備え、前記2つの要求
/応答信号送受信手段及び前記2つの信号間スキュー補
正手段の動作順位を予め決めておくので、伝送路が半二
重の構成になっている場合にも適用できる。
According to the third aspect of the present invention, a plurality of signals are transmitted in parallel via a transmission line, and in a parallel signal transmission device in which the transmission line is half-duplex, it is provided on both sides of the transmission line. Send a request signal to the other side to notify it of the test signal transmission before sending the test signal, receive the request signal from the other side and send a response signal back to the other side, and send the response signal from the other side. Two request / response signal transmitting / receiving means for receiving and a response of the request / response signal transmitting / receiving means provided on both sides of the transmission line and provided on the same side of the transmission line among the two request / response signal transmitting / receiving means The test signal is transmitted to all the lines of the transmission line at the same timing by signal reception, and the test signal is received from all the lines of the transmission line from the time when the test signal is received for each line of the transmission line. Time to Then, the signal-to-signal skew generated during the transmission of the plurality of signals is delayed by delaying the plurality of signals transmitted by each line of the transmission path by the stored time. To correct 2
Since the two signal / skew correction means are provided and the order of operation of the two request / response signal transmission / reception means and the two signal skew correction means is determined in advance, the transmission line has a half-duplex configuration. It can also be applied in cases.

【0050】請求項4記載の発明によれば、複数の信号
を並列に伝送路を介して伝送し、この伝送路が全二重で
ある並列信号伝送装置において、前記伝送路の両側に設
けられて相手側に対して試験信号の送信前に試験信号の
送信を知らせる要求信号を送信し、相手側からの要求信
号を受信して応答信号を相手側に返送し、相手側からの
応答信号を受信する2つの要求/応答信号送受信手段
と、前記伝送路の両側に設けられて前記2つの要求/応
答信号送受信手段のうち前記伝送路の同じ側に設けられ
た要求/応答信号送受信手段の応答信号受信により試験
信号を前記伝送路の全ての回線に同じタイミングで送信
し、前記伝送路の各回線毎に前記試験信号を受信した時
点から前記伝送路の全ての回線から前記試験信号を受信
するまでの時間を測定して記憶し、前記伝送路の各回線
で伝送されてきた前記複数の信号に対してそれぞれ前記
記憶した時間分だけ遅延をかけることにより、前記複数
の信号の伝送中に発生した信号間スキューを補正する2
つの信号間スキュー補正手段とを備え、前記2つの要求
/応答信号送受信手段の一方が前記要求信号を送信した
場合に前記2つの要求/応答信号送受信手段の他方も前
記要求信号を送信して前記2つの要求/応答信号送受信
手段及び前記2つの信号間スキュー補正手段が同時に双
方向にて同じ一連の動作を行うようにしたので、試験信
号が伝送路を1往復する時間で双方向の信号伝送に対す
る信号間スキューを補正することができ、本来の信号伝
送の効率を損なうことなく信号間スキューを補正するこ
とができる。
According to the invention described in claim 4, in a parallel signal transmission device for transmitting a plurality of signals in parallel through a transmission line, and the transmission line is a full duplex, the parallel signal transmission device is provided on both sides of the transmission line. Send a request signal to the other side to notify it of the test signal transmission before sending the test signal, receive the request signal from the other side and send a response signal back to the other side, and send the response signal from the other side. Two request / response signal transmitting / receiving means for receiving and a response of the request / response signal transmitting / receiving means provided on both sides of the transmission line and provided on the same side of the transmission line among the two request / response signal transmitting / receiving means The test signal is transmitted to all the lines of the transmission line at the same timing by signal reception, and the test signal is received from all the lines of the transmission line from the time when the test signal is received for each line of the transmission line. Time to Then, the signal-to-signal skew generated during the transmission of the plurality of signals is delayed by delaying the plurality of signals transmitted by each line of the transmission path by the stored time. To correct 2
And one of the two request / response signal transmitting / receiving means transmits the request signal, and the other of the two request / response signal transmitting / receiving means transmits the request signal. Since the two request / response signal transmitting / receiving means and the two signal skew correcting means simultaneously perform the same series of operations in both directions, bidirectional signal transmission in a time period in which the test signal makes one round trip in the transmission path. The signal-to-signal skew can be corrected, and the signal-to-signal skew can be corrected without impairing the original signal transmission efficiency.

【0051】請求項5記載の発明によれば、請求項1,
2,3または4記載の並列信号伝送装置において、前記
手段が一連の動作を少なくとも電源投入時に行うので、
ユーザの手をわずらわせることなく確実に信号間スキュ
ーを補正することができ、信頼性の高い信号伝送を実現
できる。
According to the invention of claim 5, claim 1,
In the parallel signal transmission device according to 2, 3, or 4, since the means performs a series of operations at least when the power is turned on,
The signal-to-signal skew can be reliably corrected without the need for the user to move, and highly reliable signal transmission can be realized.

【0052】請求項6記載の発明によれば、請求項1,
2,3,4または5記載の並列信号伝送装置において、
前記手段が一連の動作を所定時間毎に繰り返して行うの
で、信号間スキューが環境温度や電源電圧の変動により
経時的に変化しても信号間スキューの発生を抑えること
ができ、耐環境性に優れた信号伝送を実現できる。
According to the invention described in claim 6,
In the parallel signal transmission device according to 2, 3, 4 or 5,
Since the means repeats a series of operations every predetermined time, it is possible to suppress the occurrence of the signal-to-signal skew even if the signal-to-signal skew changes over time due to changes in the environmental temperature and the power supply voltage, and it is possible to improve the environment resistance. Excellent signal transmission can be realized.

【0053】請求項7記載の発明によれば、請求項2,
3,4,5または6記載の並列信号伝送装置において、
前記信号間スキュー補正用信号送受信手段または前記要
求/応答信号送受信手段は前記伝送路が空き状態にある
ことを確認して要求信号及び応答信号の送信を開始する
ので、たとえ信号間スキュー補正動作を開始する時間に
なったときに何らかの信号伝送がある場合にはそれが完
全に終了するまで待つことができ、本来の信号伝送の効
率を損なうことなく信号間スキューを正しく補正するこ
とができる。
According to the invention of claim 7, claim 2,
In the parallel signal transmission device according to 3, 4, 5 or 6,
Since the signal-to-signal skew correction signal transmission / reception means or the request / response signal transmission / reception means starts transmission of the request signal and the response signal after confirming that the transmission path is in an empty state, even if the signal-to-signal skew correction operation is performed, When there is some signal transmission at the start time, it is possible to wait until it is completely finished, and the signal-to-signal skew can be corrected correctly without impairing the original signal transmission efficiency.

【0054】請求項8記載の発明によれば、請求項2,
3,4,5,6または7記載の並列信号伝送装置におい
て、前記信号間スキュー補正用信号送受信手段または前
記要求/応答信号送受信手段は前記要求信号を受信する
と前記伝送路からの試験信号を遮断して外部に伝送しな
いようにしたので、試験信号によってシステムに何らか
の障害が発生するのを防止することができ、システムの
信頼性を確保することができる。
According to the invention of claim 8, claim 2
In the parallel signal transmission device according to 3, 4, 5, 6 or 7, the signal transmission / reception means for signal skew correction or the request / response signal transmission / reception means cuts off a test signal from the transmission path when the request signal is received. Since it is not transmitted to the outside, it is possible to prevent the test signal from causing any trouble in the system, and it is possible to ensure the reliability of the system.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1,2,5〜8記載の発明の実施例の伝
送装置を用いたシステム構成の一例における伝送装置の
構成例を示すブロック図である。
FIG. 1 is a block diagram showing a configuration example of a transmission device in an example of a system configuration using the transmission device according to an embodiment of the present invention as defined in claims 1, 2, 5-8.

【図2】同システムの概略を示すブロック図である。FIG. 2 is a block diagram showing an outline of the system.

【図3】同システムにおける試験信号を送信する側の伝
送装置における制御回路の構成例を示すブロック図であ
る。
FIG. 3 is a block diagram showing a configuration example of a control circuit in a transmission device on the side of transmitting a test signal in the system.

【図4】同システムにおける試験信号を受信する側の伝
送装置における制御回路の構成例を示すブロック図であ
る。
FIG. 4 is a block diagram showing a configuration example of a control circuit in a transmission device on the side receiving a test signal in the system.

【図5】同システムにおける試験信号を送信する側の伝
送装置における信号伝送回路の一例を示すブロック図で
ある。
FIG. 5 is a block diagram showing an example of a signal transmission circuit in a transmission device on the side of transmitting a test signal in the system.

【図6】同システムにおける試験信号を受信する側の伝
送装置における信号伝送回路の一例を示すブロック図で
ある。
FIG. 6 is a block diagram showing an example of a signal transmission circuit in a transmission device on the side that receives a test signal in the system.

【図7】同信号伝送回路におけるスキュー補正回路の構
成例を示すブロック図である。
FIG. 7 is a block diagram showing a configuration example of a skew correction circuit in the signal transmission circuit.

【図8】請求項3記載の発明の実施例の伝送装置を用い
たシステム構成の一例における制御回路を示すブロック
図である。
FIG. 8 is a block diagram showing a control circuit in an example of a system configuration using the transmission device according to the third embodiment of the invention.

【符号の説明】[Explanation of symbols]

11,12 伝送装置 13 伝送路 131〜13n 回線 14,15 端末機器 16 制御回路 171〜17n 信号伝送回路 18 抵抗 19 コンデンサ 20 バッファ 21 タイマー 22,26,27,33〜35,40 アンド回路 23,32,36,39,46 インバータ 24 立ち上がり遷移検出回路 25,30 伝送路空き検出回路 28 試験信号発生回路 29 終了検出回路 31 遅延設定終了検出回路 37 オア回路 38 スキュー補正回路 41 リセット回路 42 カウンタ 43 シフトレジスタ 44 デコーダ 45 マルチプレクサ11,12 transmission device 13 transmission path 13 1 to 13 n lines 14, 15 the terminal device 16 the control circuit 17 1 to 17 n signal transmission circuit 18 resistor 19 capacitor 20 buffer 21 timer 22,26,27,33~35,40 and Circuit 23, 32, 36, 39, 46 Inverter 24 Rising transition detection circuit 25, 30 Transmission line idle detection circuit 28 Test signal generation circuit 29 End detection circuit 31 Delay setting end detection circuit 37 OR circuit 38 Skew correction circuit 41 Reset circuit 42 Counter 43 Shift Register 44 Decoder 45 Multiplexer

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】複数の信号を並列に伝送路を介して伝送す
る並列信号伝送装置において、信号送信側にて試験信号
を生成して該試験信号を前記伝送路の全ての回線に同じ
タイミングで送信する試験信号送信手段と、信号受信側
にて前記伝送路の各回線毎に前記試験信号を受信した時
点から前記伝送路の全ての回線から前記試験信号を受信
するまでの時間を測定して記憶し、前記伝送路の各回線
で伝送された前記複数の信号に対してそれぞれ前記記憶
した時間分だけ遅延をかけることにより、前記複数の信
号の伝送中に発生した信号間スキューを補正する信号間
スキュー補正手段とを備えたことを特徴とする並列信号
伝送装置。
1. A parallel signal transmission device for transmitting a plurality of signals in parallel via a transmission line, wherein a test signal is generated at a signal transmission side and the test signal is transmitted to all lines of the transmission line at the same timing. The test signal transmitting means for transmitting, and measuring the time from the time the test signal is received for each line of the transmission line at the signal receiving side to the reception of the test signal from all the lines of the transmission line. A signal for storing and correcting the signal-to-signal skew that has occurred during the transmission of the plurality of signals by delaying the plurality of signals transmitted by each line of the transmission path by the stored time. A parallel signal transmission device comprising inter-skew correction means.
【請求項2】複数の信号を並列に伝送路を介して伝送す
る並列信号伝送装置において、試験信号の送信側にて試
験信号の受信側に対して試験信号を送信する前に試験信
号の送信を知らせる要求信号を送信し、試験信号の受信
側にて前記要求信号を受信して試験信号を受信する準備
をした後に応答信号を試験信号の送信側に返送し、試験
信号の送信側にて前記応答信号の受信を確認してから試
験信号を前記伝送路の全ての回線に同じタイミングで送
信する信号間スキュー補正用信号送受信手段と、試験信
号の受信側にて前記伝送路の各回線毎に前記試験信号を
受信した時点から前記伝送路の全ての回線から前記試験
信号を受信するまでの時間を測定して記憶し、前記伝送
路の各回線で伝送された前記複数の信号に対してそれぞ
れ前記記憶した時間分だけ遅延をかけることにより、前
記複数の信号の伝送中に発生した信号間スキューを補正
する信号間スキュー補正手段とを備えたことを特徴とす
る並列信号伝送装置。
2. A parallel signal transmission apparatus for transmitting a plurality of signals in parallel via a transmission line, wherein a test signal transmitting side transmits a test signal before transmitting a test signal to a test signal receiving side. The test signal receiving side, the test signal receiving side receives the request signal and prepares to receive the test signal, and then returns a response signal to the test signal transmitting side. Signal transmission / reception means for inter-signal skew correction for transmitting the test signal to all the lines of the transmission line at the same timing after confirming the reception of the response signal, and for each line of the transmission line at the receiving side of the test signal The time from the time of receiving the test signal to the time of receiving the test signal from all the lines of the transmission line is measured and stored, and for the plurality of signals transmitted by each line of the transmission line. When each of the above is remembered By multiplying the amount corresponding delay, parallel signal transmission apparatus characterized by comprising a signal skew correcting means for correcting the signal skew occurring during the transmission of the plurality of signals.
【請求項3】複数の信号を並列に伝送路を介して伝送
し、この伝送路が半二重である並列信号伝送装置におい
て、前記伝送路の両側に設けられて相手側に対して試験
信号の送信前に試験信号の送信を知らせる要求信号を送
信し、相手側からの要求信号を受信して応答信号を相手
側に返送し、相手側からの応答信号を受信する2つの要
求/応答信号送受信手段と、前記伝送路の両側に設けら
れて前記2つの要求/応答信号送受信手段のうち前記伝
送路の同じ側に設けられた要求/応答信号送受信手段の
応答信号受信により試験信号を前記伝送路の全ての回線
に同じタイミングで送信し、前記伝送路の各回線毎に前
記試験信号を受信した時点から前記伝送路の全ての回線
から前記試験信号を受信するまでの時間を測定して記憶
し、前記伝送路の各回線で伝送されてきた前記複数の信
号に対してそれぞれ前記記憶した時間分だけ遅延をかけ
ることにより、前記複数の信号の伝送中に発生した信号
間スキューを補正する2つの信号間スキュー補正手段と
を備え、前記2つの要求/応答信号送受信手段及び前記
2つの信号間スキュー補正手段の動作順位を予め決めて
おくことを特徴とする並列信号伝送装置。
3. A parallel signal transmission device for transmitting a plurality of signals in parallel via a transmission line, wherein the transmission line is half-duplex, provided on both sides of the transmission line, and a test signal is transmitted to the other side. Two request / response signals that send a request signal to notify the transmission of the test signal before sending the request, receive the request signal from the other party, send back the response signal to the other party, and receive the response signal from the other party The test signal is transmitted by receiving a response signal from the transmission / reception means and the request / response signal transmission / reception means provided on the same side of the transmission path among the two request / response signal transmission / reception means provided on both sides of the transmission path. All the lines of the transmission path are transmitted at the same timing, and the time from the reception of the test signal for each line of the transmission path to the reception of the test signal from all the lines of the transmission path is measured and stored. Each of the transmission lines Two inter-signal skew correction means for correcting inter-signal skew generated during transmission of the plurality of signals by delaying each of the plurality of signals transmitted through the line by the stored time. A parallel signal transmission device comprising: the two request / response signal transmission / reception means and the two signal skew correction means.
【請求項4】複数の信号を並列に伝送路を介して伝送
し、この伝送路が全二重である並列信号伝送装置におい
て、前記伝送路の両側に設けられて相手側に対して試験
信号の送信前に試験信号の送信を知らせる要求信号を送
信し、相手側からの要求信号を受信して応答信号を相手
側に返送し、相手側からの応答信号を受信する2つの要
求/応答信号送受信手段と、前記伝送路の両側に設けら
れて前記2つの要求/応答信号送受信手段のうち前記伝
送路の同じ側に設けられた要求/応答信号送受信手段の
応答信号受信により試験信号を前記伝送路の全ての回線
に同じタイミングで送信し、前記伝送路の各回線毎に前
記試験信号を受信した時点から前記伝送路の全ての回線
から前記試験信号を受信するまでの時間を測定して記憶
し、前記伝送路の各回線で伝送されてきた前記複数の信
号に対してそれぞれ前記記憶した時間分だけ遅延をかけ
ることにより、前記複数の信号の伝送中に発生した信号
間スキューを補正する2つの信号間スキュー補正手段と
を備え、前記2つの要求/応答信号送受信手段の一方が
前記要求信号を送信した場合に前記2つの要求/応答信
号送受信手段の他方も前記要求信号を送信して前記2つ
の要求/応答信号送受信手段及び前記2つの信号間スキ
ュー補正手段が同時に双方向にて同じ一連の動作を行う
ようにしたことを特徴とする並列信号伝送装置。
4. A parallel signal transmission apparatus for transmitting a plurality of signals in parallel through a transmission line, wherein the transmission line is a full-duplex parallel signal transmission device. Two request / response signals that send a request signal to notify the transmission of the test signal before sending the request, receive the request signal from the other party, send back the response signal to the other party, and receive the response signal from the other party The test signal is transmitted by receiving a response signal from the transmission / reception means and the request / response signal transmission / reception means provided on the same side of the transmission path among the two request / response signal transmission / reception means provided on both sides of the transmission path. All the lines of the transmission path are transmitted at the same timing, and the time from the reception of the test signal for each line of the transmission path to the reception of the test signal from all the lines of the transmission path is measured and stored. Each of the transmission lines Two inter-signal skew correction means for correcting inter-signal skew generated during transmission of the plurality of signals by delaying each of the plurality of signals transmitted through the line by the stored time. And when one of the two request / response signal transmitting / receiving means transmits the request signal, the other of the two request / response signal transmitting / receiving means also transmits the request signal to transmit / receive the two request / response signal transmission / reception signals. A parallel signal transmission device, wherein the means and the skew correction means between the two signals simultaneously perform the same series of operations in both directions.
【請求項5】請求項1,2,3または4記載の並列信号
伝送装置において、前記手段が一連の動作を少なくとも
電源投入時に行うことを特徴とする並列信号伝送装置。
5. The parallel signal transmission device according to claim 1, 2, 3 or 4, wherein the means performs a series of operations at least when the power is turned on.
【請求項6】請求項1,2,3,4または5記載の並列
信号伝送装置において、前記手段が一連の動作を所定時
間毎に繰り返して行うことを特徴とする並列信号伝送装
置。
6. The parallel signal transmission device according to claim 1, 2, 3, 4 or 5, wherein said means repeats a series of operations at predetermined time intervals.
【請求項7】請求項2,3,4,5または6記載の並列
信号伝送装置において、前記信号間スキュー補正用信号
送受信手段または前記要求/応答信号送受信手段は前記
伝送路が空き状態にあることを確認して要求信号及び応
答信号の送信を開始することを特徴とする並列信号伝送
装置。
7. The parallel signal transmission device according to claim 2, 3, 4, 5, or 6, wherein the transmission line of said signal skew correction signal transmission / reception means or said request / response signal transmission / reception means is in an idle state. A parallel signal transmission device, characterized in that the transmission of a request signal and a response signal is started.
【請求項8】請求項2,3,4,5,6または7記載の
並列信号伝送装置において、前記信号間スキュー補正用
信号送受信手段または前記要求/応答信号送受信手段は
前記要求信号を受信すると前記伝送路からの試験信号を
遮断して外部に伝送しないようにしたことを特徴とする
並列信号伝送装置。
8. A parallel signal transmission apparatus according to claim 2, 3, 4, 5, 6 or 7, wherein said signal skew correction signal transmitting / receiving means or said request / response signal transmitting / receiving means receives said request signal. A parallel signal transmission device, characterized in that a test signal from the transmission line is blocked so as not to be transmitted to the outside.
JP01203195A 1995-01-27 1995-01-27 Parallel signal transmission device Expired - Fee Related JP3487458B2 (en)

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Application Number Priority Date Filing Date Title
JP01203195A JP3487458B2 (en) 1995-01-27 1995-01-27 Parallel signal transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01203195A JP3487458B2 (en) 1995-01-27 1995-01-27 Parallel signal transmission device

Publications (2)

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JPH08202653A true JPH08202653A (en) 1996-08-09
JP3487458B2 JP3487458B2 (en) 2004-01-19

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Publication number Priority date Publication date Assignee Title
JPH11161600A (en) * 1997-08-19 1999-06-18 Matsushita Electric Ind Co Ltd Adjustment device and adjustment method for delay time between plural transmission lens
WO1999046687A1 (en) * 1998-03-12 1999-09-16 Hitachi, Ltd. Data transmitter
WO2003010939A1 (en) * 2001-07-25 2003-02-06 Sony Corporation Interface apparatus
US8194087B2 (en) 2001-05-15 2012-06-05 Rambus Inc. Scalable unified memory architecture
US9053778B2 (en) 2001-04-24 2015-06-09 Rambus Inc. Memory controller that enforces strobe-to-strobe timing offset
US11457142B2 (en) 2017-06-09 2022-09-27 Sony Semiconductor Solutions Corporation Reception device, transmission device, control method, program, and transmission and reception system

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11161600A (en) * 1997-08-19 1999-06-18 Matsushita Electric Ind Co Ltd Adjustment device and adjustment method for delay time between plural transmission lens
JP4634605B2 (en) * 1998-03-12 2011-02-16 エルピーダメモリ株式会社 Data transmission system
WO1999046687A1 (en) * 1998-03-12 1999-09-16 Hitachi, Ltd. Data transmitter
US9741424B2 (en) 2001-04-24 2017-08-22 Rambus Inc. Memory controller
US9053778B2 (en) 2001-04-24 2015-06-09 Rambus Inc. Memory controller that enforces strobe-to-strobe timing offset
US9311976B2 (en) 2001-04-24 2016-04-12 Rambus Inc. Memory module
US9472262B2 (en) 2001-04-24 2016-10-18 Rambus Inc. Memory controller
US10236051B2 (en) 2001-04-24 2019-03-19 Rambus Inc. Memory controller
US10706910B2 (en) 2001-04-24 2020-07-07 Rambus Inc. Memory controller
US8194087B2 (en) 2001-05-15 2012-06-05 Rambus Inc. Scalable unified memory architecture
US7277973B2 (en) 2001-07-25 2007-10-02 Sony Corporation Interface apparatus
WO2003010939A1 (en) * 2001-07-25 2003-02-06 Sony Corporation Interface apparatus
US11457142B2 (en) 2017-06-09 2022-09-27 Sony Semiconductor Solutions Corporation Reception device, transmission device, control method, program, and transmission and reception system

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