JPH08202580A - Emulator - Google Patents

Abstract

PURPOSE: To execute emulation in the application system of a multi-CPU system by using one emulator. CONSTITUTION: The emulator which executes the emulation in the application system of a 2-CPU system and is divided into an emulator unit not to be concerned with making into AS such as a part to support the CPU core of a microcomputer, etc., and a target probe 3b to vary in accordance with the making into AS such as the artificial circuit of a peripheral function, etc., is provided with a slave microcomputer 4 to execute substitutionally the function of the target microcomputer of one side between two microcomputers and the slave microcomputer 5 to execute substitionally the funciton of the target microcomputer 5 of the other side. Since the target probe 3b is provided with these slave microcomputers 4, 5, the emulation of the two-CPU system can be executed by using one emulator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator,
In particular, the present invention relates to a technique effectively applied to system debugging in an application system in which two or more microcomputers are used.

[0002]

2. Description of the Related Art According to a study made by the present inventor, a so-called multi-C in which two or more microcomputers are used in an application system under development by a user
For example, in the case of an application system in which two microcomputers are used, debugging in the PU system application system is performed using two emulators.

Incidentally, as an example in which an emulator of this kind is described in detail, Hitachi, Ltd., 1993
Issued in July 2012, "E7000 SH7032 SH703
4 emulator user's manual ”.

[0004]

However, the present inventors have found that the debugging of the emulator in the application system of the multi-CPU system as described above has the following problems.

That is, when an application system in the multi-CPU system is emulated by a plurality of emulators, since the same bus is used, the capacitive load increases during high speed operation, which makes high speed operation difficult. There is a tendency that the delay becomes long.

Further, by using a plurality of emulators, it becomes difficult to share the built-in functions of the emulators with a simple interface.

An object of the present invention is to provide an emulator capable of performing emulation in a multi-CPU type application system in which a plurality of microcomputers are used by a single emulator.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In other words, the emulator of the present invention is provided with a multi-CPU type application system in which one emulator is provided with as many slave microcomputers as the substitutes for the functions of the microcomputers provided in the application system in a number corresponding to the plurality of microcomputers. Is for debugging.

In addition, the emulator of the present invention selects either the first clock signal output from the application system or the second clock signal output from the emulator based on the first control signal, and outputs a plurality of signals. The clock selecting and supplying means for supplying the clock signal synchronized with the slave microcomputer is provided.

Further, the emulator of the present invention generates the first reset signal based on the second control signal to reset the plurality of slave microcomputers.
Second reset signal or second output from the application system
The reset signal output means for selecting any one of the reset signals and outputting the reset signals to the reset signal input sections of the plurality of slave microcomputers to reset the plurality of slave microcomputers is provided.

In the emulator of the present invention, the trace data and the coverage data are input by inputting the data acquisition signal synchronized with the trace means for sampling various data and the status signal for tracing and the coverage means for displaying the execution address. Is provided with data acquisition signal means for simultaneously acquiring data.

[0014]

According to the above-described emulator of the present invention, a plurality of slave microcomputers that substitute the functions of the microcomputers provided in the application system for one emulator are provided in a number corresponding to the plurality of microcomputers. Since a plurality of emulators suitable for a microcomputer are unnecessary, the user interface and the transmission line can be reduced, and the capacitive load can be reduced, so that high-speed operation emulation can be realized.

According to the emulator of the present invention described above, either the first clock signal output from the application system or the second clock signal output from the emulator is selected based on the first control signal. However, the clock selecting and supplying means for supplying the clock signals to the plurality of slave microcomputers can supply the synchronized clock signals from the emulator itself to the plurality of slave microcomputers with a simple circuit configuration.

Further, according to the above-mentioned emulator of the present invention, the first reset signal is generated based on the second control signal and is output from the first reset signal for resetting a plurality of slave microcomputers or the application system. The reset signal output means for selecting any one of the second reset signals to be output to the reset signal input sections of the plurality of slave microcomputers and resetting the reset signals synchronized from the emulator itself. Can be output to.

Further, according to the emulator of the present invention described above, a data acquisition signal for inputting a data acquisition signal synchronized with a trace means for sampling various data or status signals and tracing and a coverage means for displaying an execution address. By the means, data acquisition of trace data and coverage data can be performed simultaneously in series.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a connection diagram between an emulator and an application system according to Embodiment 1 of the present invention, and FIG.
1 is a block diagram of a main part of an emulator according to a first embodiment of the present invention, and FIG. 3 is a circuit diagram of a clock oscillation circuit and a reset circuit in an emulator according to a first embodiment of the present invention.

In the first embodiment, an application system 1 provided with a plurality of microcomputers under development by the user.
An emulator 3 for debugging software and hardware is provided between the computer and a personal computer 2 which is a parent computer for software development by using a predetermined cable C.
It is connected by A1 and CA2.

Here, in the present embodiment, the application system 1 is a 2 CPU system in which two microcomputers (not shown) are provided.

Further, the emulator 3 includes an AS for supporting a CPU core of a microcomputer.
Emulator unit 3a not related to (Application Specific), and target probe 3 that changes due to AS of pseudo circuits of peripheral functions
and the emulator unit 3a and the target probe 3b are also connected by a predetermined cable CA3.

Further, the emulator unit 3a is a master microcomputer for controlling the emulator,
It is configured by a circuit (not shown) such as a serial interface section for performing data communication with the personal computer 2, a program execution, a breakpoint stop condition for setting a trace stop condition and stopping the program or trace when the condition is satisfied.

The target probe 3b is, as shown in FIG. 2, a slave microcomputer (hereinafter, slave microcomputer) 4 which substitutes the function of a target microcomputer, which is one of the two microcomputers, and the other. The slave microcomputer 5 which substitutes the function of the target microcomputer, which is the microcomputer, is provided.

Further, the target probe 3b has a socket (not shown) for a target microcomputer in the control circuit 6 and the application system 1 (shown in FIG. 1) for realizing an emulation memory which is a lending memory, emulation and various debug functions. The user interface 7 and the like to which the cable CA2 having the end) is connected are provided.

In the target probe 3b,
The slave microcomputers 4, 5, the control circuit 6, and the user interface 7 are connected by a common data bus 8 and address bus 9.

Further, the slave microcomputer 4, the control circuit 6
Input / output of control signals between the user interface 7 and the user interface 7 is performed via a dedicated control signal bus 10. Input / output of control signals between the slave microcomputer 5, the control circuit 6 and the user interface 7 is also performed by the dedicated control. This is done via the signal bus 11.

Further, between the control circuit 6 and the slave microcomputers 4, 5 and the user interface 7, there are a data bus buffer 12 and an address bus buffer 13 for timing the operating speed of each signal input / output. A control signal bus buffer 14 and a control signal bus buffer 15 are provided.

A user interface 7 is provided between the target probe 3b and the application system 1 (shown in FIG. 1).
A control signal, an address signal and a data signal are input and output via the.

The software and hardware of the application system 1 are debugged by the connection shown in FIG. 1. When the application system 1 of the 2CPU system in this embodiment is emulated, the target probe 3b is connected to the target microcomputer. By providing the slave microcomputers 4 and 5 which substitute the function of (1), emulation can be performed by one emulator 3.

Further, the data bus 8 and the address bus 9
Since only one user interface 7 is required since all of them can be used in common, the transmission line can be shortened, so that high-speed operation emulation can be realized.

Further, the target probe 3b includes
The number of slave microcomputers 4 and 5 corresponding to the number of microcomputers (not shown) provided in the application system 1 is provided. For example, although three microcomputers are provided, an application system (not shown) of 3CPU system is provided. If so, three slave microcomputers will be provided in the target probe (not shown).

Further, as shown in FIG. 3, a clock oscillation circuit (clock selection supply means) 16 for outputting a second clock signal for operating the slave microcomputers 4 and 5 and the slave microcomputer 4 are provided to the target probe 3b. , 5 are reset, a reset circuit (reset signal output means) 17 for outputting a first reset signal is provided.

The clock oscillation circuit 16 is an oscillator 16a which outputs a second clock signal having a predetermined frequency, an inverter Iv1 which inverts the signal, and an AND circuit A.
It is composed of ND circuits 16b and 16c and an OR circuit 16d which is a logical sum circuit.

The oscillator 16a has an inverter Iv1.
Of the inverter Iv1 connected to the input part of
The D circuit 16b is connected to one input of the D circuit 16b, and the other uses the second clock signal output from the oscillator 16a in the control circuit 6 or from an oscillator (not shown) provided in the application system 1. It is connected to a selection signal output unit (not shown) that outputs a first control signal indicating whether to use the output first clock signal.

Further, the selection signal output section is the AND circuit 16
The first clock signal output from the oscillator provided in the application system 1 described above is input to the other input.

Further, the output parts of the AND circuits 16b and 16c are respectively connected to the input parts of the OR circuit 16d, and the outputs of the OR circuit 16d are connected to the respective clock input terminals Ck of the slave microcomputers 4 and 5. Has been done.

Here, the case where the oscillator provided in the application system 1 is used in the clock oscillation circuit 16 will be described.

To use the oscillator provided in the application system 1 (shown in FIG. 1), for example, the user inputs a command for selecting the oscillator provided in the application system 1 by the personal computer 2.

A predetermined signal is output from the personal computer 2 in response to the command, and the selection signal output section provided in the control circuit 6 outputs the first signal based on the signal.
The Hi signal, which is the control signal of, is output.

The Hi signal is input to the input portion of the inverter Iv1 and one input portion of the AND circuit 16c, respectively, and the Hi signal input to the inverter Iv1 is inverted and becomes a Lo signal, which is input to the other input portion of the AND circuit 16b. Is entered.

Therefore, the oscillator 16 provided in the target probe 3b is provided at one input portion of the AND circuit 16b.
Since the second clock signal output from a is input and the Lo signal is input to the other input section, the AND circuit 16
The output of b becomes the Lo signal.

On the other hand, the Hi signal is input to one input section of the AND circuit 16c, and the first clock signal output from the oscillator provided in the application system 1 is input to the other input section of the AND circuit 16c. A signal synchronized with the clock signal 1 is output from the output section of the AND circuit 16c.

The AND circuits 16b and 16c are connected to one input of the OR circuit 16d provided in the subsequent stage.
Since the respective outputs are input, the first clock signal output from the oscillator provided in the application system 1 is supplied to the clock input terminals Ck of the slave microcomputers 4 and 5.

To supply the second clock signal output from the oscillator 16a, similarly, the user inputs a command to use the oscillator 16a by the personal computer 2, and the personal computer 2 outputs a predetermined signal. Then, the Lo signal is output from the selection signal output section provided in the control circuit 6 based on the signal.

The signal inverted by the inverter Iv1 causes the other input portion of the AND circuit 16b to go high.
The i signal is output, and a signal synchronized with the oscillator 16a is output from the output section of the AND circuit 16b.

Further, the AND circuit 16c has the Lo signal at one input portion thereof, and thus the output thereof is the Lo signal.

Since the outputs of the AND circuits 16b and 16c are input to the OR circuit 16d, the oscillator 16 is connected to the clock input terminals Ck of the slave microcomputers 4 and 5.
The second clock signal output from a will be supplied.

As a result, not only the first clock signal output from the oscillator provided in the application system 1 but also the oscillator 16a provided in the target probe 3b.
A second clock signal output from can also be provided.

Next, the reset circuit 17 is composed of inverters Iv2 to Iv7 for inverting signals and OR circuits 16e and 16f which are logical sum circuits.

Then, the input parts of the inverters Iv3 and Iv5 are connected so that the second reset signal output from the application system 1 (shown in FIG. 1) is input, and the input parts of the inverters Iv2 and Iv4 are connected. Are connected so that, for example, the second control signal output from the control circuit 6 is input.

The output parts of the inverters Iv2 and Iv3 are connected to the respective input parts of the OR circuit 16e, the output parts of the inverters Iv4 and Iv5 are connected to the respective input parts of the OR circuit 16f, and the OR circuits 16e and 16f. Is connected to the input parts of the inverters Iv6 and IV7,
The output part is connected to the reset signal input terminal R of the slave microcomputers 4 and 5.

Further, in the present embodiment, the slave microcomputers 4 and 5 are reset by the Lo signal, so-called active "L".

Here, the case where the slave microcomputers 4 and 5 are reset by the second reset signal output from the application system 1 will be described.

First, the user inputs a command for resetting the slave microcomputers 4 and 5 by the second reset signal output from the application system 1 by the personal computer 2.

In response to the command, the personal computer 2 outputs a second control signal to the control circuit 6, and based on this signal, the control circuit 6 outputs a Hi signal as the second control signal when the slave microcomputers 4 and 5 are reset. Output.

When the slave microcomputers 4 and 5 are reset, when the Lo signal which is the second reset signal output from the application system 1 is input to the input parts of the inverters Iv3 and IV5, the Lo signal is inverted. Been hi
It becomes a signal and is input to each input part of OR circuit 16e, 16f.

Further, a Hi signal which is the second control signal output from the control signal 6 is input to the inverters Iv2 and Iv4 input sections, and the signal is inverted and ORed.
It is input to one input section of the circuits 16e and 16f.

As a result, one of the input portions of the OR circuits 16e and 16f becomes the Lo signal and the other input portion becomes the Hi signal, so that the output becomes the Hi signal. However, the inverters Iv6 and Iv7 connected in the subsequent stages cause the outputs to become the Hi signal. The signal is inverted and L
The o signal is output and the second reset signal is input to the reset signal input terminals R of the slave microcomputers 4 and 5.

Next, the case where the slave microcomputers 4 and 5 are reset by the first reset signal output from the reset circuit 17 will be described.

First, the user inputs a command to reset the slave microcomputers 4 and 5 by the first reset signal output from the reset circuit 17 by the personal computer 2.

In response to the command, the personal computer 2 outputs a predetermined signal to the control circuit 6, and based on the signal, the control circuit 6 outputs the Lo signal as the second control signal when the slave microcomputers 4 and 5 are reset. .

When the slave microcomputers 4 and 5 are reset, the control circuit 6 outputs a second control signal Lo.
When the signal is input to the input sections of the inverters Iv3 and IV5, the Lo signal is inverted and becomes a Hi signal, which is input to the respective input sections of the OR circuits 16e and 16f.

Here, a Hi signal which is a second reset signal output from the application system is input to the inverters Iv2 and Iv4 input sections, and the signal is inverted and the other of the OR circuits 16e and 16f is inverted. It is input to the input section.

As a result, one of the input portions of the OR circuits 16e and 16f becomes the Hi signal, and the other input portion becomes the Lo signal, so that the output becomes the Hi signal. However, the inverters Iv6 and Iv7 connected in the subsequent stage output the Hi signal. The signal is inverted and L
The o signal is output and the first reset signal is input to the reset signal input terminals R of the slave microcomputers 4 and 5.

Therefore, the first reset signal synchronized with the reset signal input terminals R of the slave microcomputers 4 and 5 can be input from the emulator 3.

As a result, in the first embodiment, the target probe 3b is provided with the slave microcomputers 4 and 5 acting on behalf of the target microcomputer, so that the capacitive load can be reduced and high-speed operation emulation can be realized.

Further, the clock oscillator 16a is provided by the clock oscillator circuit 16 provided in the target probe 3b.
The second clock signal output from the slave microcomputer 4 and 5 can be shared with the slave microcomputer 4 and 5, and the program can be easily debugged without connecting the application system 1.

Furthermore, the slave microcomputer 4, by the reset circuit 17 provided in the target probe 3b.
The reset signal input to 5 can be output as the first reset signal from the emulator 3 with a simple circuit configuration, and emulation at the reset start in the application system 1 can be performed.

(Embodiment 2) FIG. 4 is a block diagram of essential parts of an emulator provided with a trace function and a coverage function according to Embodiment 2 of the present invention.

In the second embodiment, a trace circuit (trace means) for sampling various data and status signals provided in the control circuit 6 and tracing them.
6a and a coverage circuit (coverage means) 6b for displaying execution addresses of the slave microcomputers 4 and 5, for example.
Further, a data acquisition signal circuit (data acquisition signal means) 18 for outputting a data acquisition signal capable of simultaneously acquiring data is provided.

The trace circuit 6a is connected to the data bus 8 and the address bus 9. Predetermined data is acquired via the data bus buffer 12 and the address bus buffer 13, and the coverage circuit 6b is connected to the address bus 9. The predetermined data is acquired via the address bus buffer 13.

The data acquisition signal circuit 18 is composed of an OR circuit 18a which is a logical sum circuit and inverters Iv8 to Iv10 which invert the signals.

The input parts of the inverters Iv8 and Iv9 of the data acquisition signal circuit 18 are connected to the trace signal output parts for acquiring the trace acquisition signals of the slave microcomputers 4 and 5, respectively.

The outputs of the inverters Iv8 and IV9 are connected to the input section of the OR circuit 18a, the output of which is connected to the input section of the inverter Iv10. The output section of the inverter Iv10 is connected to the trace circuit 6a and the coverage circuit. 6b is connected to the data acquisition signal input section.

Therefore, the trace acquisition signal of the Hi signal output from the trace signal output units of the slave microcomputers 4 and 5 is inverted by the inverters Iv8 and IV9 and Lo.
Since it becomes a signal, the output of the OR circuit 18a also becomes a Lo signal, but it is inverted by the inverter Iv10 provided in the subsequent stage and becomes a Hi signal of the data acquisition signal, and the data acquisition signal input section of the trace circuit 6a and the coverage circuit 6b. Is input, and predetermined data is acquired.

As a result, in the second embodiment, since the data acquisition signals are input to the trace circuit 6a and the coverage circuit 6b at the same time, the trace data and the coverage data can be acquired simultaneously, so that the debugging efficiency is improved. Can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, although the clock oscillation circuit 16 and the reset circuit 17 and the data acquisition signal circuit 18 are provided separately in the first and second embodiments, the clock oscillation circuit 16, the reset circuit 17 and the data acquisition signal circuit are provided. All 18 may be provided on the target probe (not shown).

As a result, the emulation of the multi-CPU system application system (not shown) can be performed more efficiently.

[0081]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the number of user interfaces and transmission lines can be reduced by providing the slave microcomputers in one emulator in the number corresponding to the plurality of microcomputers provided in the application system. Since the sexual load can be reduced, high-speed operation emulation can be realized.

(2) Further, in the present invention, since the clock selection supply means provided in the emulator main body can supply the clock signals synchronized with the plurality of slave microcomputers, the program can be executed without connecting the application system. Can be debugged.

(3) Further, in the present invention, the clock selection and supply means for supplying the clock signal to the plurality of slave microcomputers provided in the emulator main body enables the emulation at the reset start.

(4) Further, according to the present invention, by providing the data acquisition signal means, the data acquisition of the trace data and the coverage data can be performed simultaneously.

(5) Further, in the present invention, the above (1) to
By (4), it is possible to significantly improve the debugging efficiency in the multi-CPU system application system provided with a plurality of microcomputers.

[Brief description of drawings]

FIG. 1 is a connection diagram between an emulator and an application system according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a main part of the emulator according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a clock oscillator circuit and a reset circuit in the emulator according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a main part of a trace function and a coverage function in an emulator according to a second embodiment of the present invention.

[Explanation of symbols]

 1 Application System 2 Personal Computer 3 Emulator 3a Emulator Unit 3b Target Probe 4 Slave Microcomputer 5 Slave Microcomputer 6 Control Circuit 6a Trace Circuit (Trace Means) 6b Coverage Circuit (Coverage Means) 7 User Interface 8 Data Bus 9 Address Bus 10 Control Signal bus 11 Control signal bus 12 Data bus buffer 13 Address bus buffer 14 Control signal bus buffer 15 Control signal bus buffer 16 Clock oscillation circuit (clock selection supply means) 16a Oscillator 16b AND circuit 16c AND circuit 16d to 16f OR circuit 17 Reset circuit (Reset signal output means) 18 Data acquisition signal circuit (data acquisition signal means) 18a OR circuit Iv1 to Iv10 Inverter CA1 to CA3 Cable Ck Clock input terminal R Reset signal input terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Sasaki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (4)

[Claims] 1. An emulator for debugging a multi-CPU type application system provided with a plurality of microcomputers, wherein a plurality of slave microcomputers provided on the application system are slave microcomputers acting on behalf of the functions of the microcomputers. An emulator characterized in that the emulator is characterized in that it is provided in a number commensurate with a microcomputer to debug the multi-CPU system application system. 2. The emulator according to claim 1, wherein
Selecting either a first clock signal output from the application system or a second clock signal output from the emulator based on a first control signal;
An emulator characterized in that a clock selecting and supplying means for supplying the plurality of slave microcomputers is provided. 3. The emulator according to claim 1, wherein a first reset signal that resets the plurality of slave microcomputers is generated based on a second control signal, and the first reset signal or An emulator provided with reset signal output means for selecting one of the second reset signals output from the application system and outputting the selected reset signal to a reset signal input unit in the plurality of slave microcomputers. 4. The emulator according to claim 1, 2 or 3, wherein a data acquisition signal synchronized with a trace means for sampling and tracing various data and status signals and a coverage means for displaying an execution address is input. An emulator characterized by being provided with data acquisition signal means for simultaneously acquiring trace data and coverage data in sequence.