JPH08202505A - Array type storage device - Google Patents

Abstract

PURPOSE: To provide the array type storage device which can write data at a high speed and can be constituted at low cost. CONSTITUTION: The array type storage device 11 is provided internally with a parity generation part 16 having a function which performs exclusive OR operation between internally stored data and inputted data and rewrites the contents of registers according to the operation result and a function which rewrites the internally stored data. Then the array type storage device is so constituted that when data are written to each disk device in block units, the same data are supplied even to the parity generation part 16, the data in the parity generation part 16 are cleared before the data blocks are written to the disk device 151 , and the result of operation regarding the data blocks to the disk device 151 that the parity generation part 16 performs is supplied to a disk controller 14P.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array type storage device, and more particularly to an array type storage device for storing data in a redundant configuration.

[0002]

2. Description of the Related Art In an array type storage device, in order to cope with a failure of each disk device forming the array type storage device,
RAID for UC Berkeley Papers
Although the system is constructed by the architecture using (Redundant Arrays of Inexpensive Disks), RA
In an array-type storage device that uses an architecture called ID3 (striping is performed in byte units and parity is stored in one specific disk device), the disk device for parity storage is always driven when data is written. Therefore, there is a problem that the response speed to the data write request is slow.

As a means for dealing with such a problem, a bus control unit 41 such as an array type storage device (FIG. 12) disclosed in Japanese Patent Laid-Open No. 3-225416 is used.
The data striped by is stored in each data buffer 42, and the parity generation unit 45
It is known that parity is generated based on the striped data, the parity data is stored in the data buffer 42 _P , and simultaneously written in the disk device 44.

[0004]

However, in the above-mentioned array type disk device, the data buffers for stored data are required for the number of disk devices for data storage in order to suppress the performance deterioration at the time of writing data.
Since the parity data buffer is also required, the system is expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide an array type storage device capable of high speed data writing and inexpensive construction.

[0006]

According to the first aspect of the present invention,
(A) N data storage disk devices for storing data, and (b) one parity storage disk device for storing the parity of data stored in these N disk devices, (C) A calculation means for performing an exclusive OR operation of the data stored inside and the input data and rewriting the data stored inside with the calculation result, and (d) data of a predetermined size to be written. When is input, clearing means for clearing the data stored in the computing means to zero, and (e) dividing means for dividing data of a predetermined size into N data blocks,
(F) Data supply means for sequentially supplying the N data blocks divided by the dividing means to the N data storage disk devices and the arithmetic means, and (g) N data blocks by the data supplying means. And a parity writing unit for writing the calculation result of the calculation unit to the parity storage disk device when the supply of the data is completed.

That is, according to the first aspect of the invention, an exclusive OR operation of the data internally stored and the input data is performed in the array type storage device, and the result is stored internally. The arithmetic unit for rewriting the existing data is provided, and the array type storage device is configured so that the same data is supplied to the arithmetic unit when writing the data in units of blocks to the data storage disk device.

According to a second aspect of the present invention, (a) N data storage disk devices for storing data,
(B) One parity storage disk device for storing the parity of the data stored in these N disk devices, (c) the first and second data block registers, and the first and second Equipped with a calculation result register,
When data is being written to the second data block register, an exclusive OR operation of the data stored in the first data block register and the data stored in the first operation result register Is performed, the operation result is stored in the second operation result register, and when data is being written in the first data block register,
Arithmetic means for performing an exclusive OR operation of the data stored in the second data block register and the data stored in the second operation result register, and storing the operation result in the first operation result register; (D) Clear means for clearing the data stored in the arithmetic register in the arithmetic means to zero when data of a prescribed size to be written is input, and (e) N data blocks for the prescribed size of data. And (f) N data blocks divided by this dividing means are sequentially supplied to N data storage disk devices, and for the first or second data block in the computing means. The data supply means for writing in the register and the operation result of the (g) operation means for the Nth data block are written in the disk device for parity storage. ; And a utility writing means.

That is, according to the second aspect of the invention, the array type storage device is provided with the first and second data block registers and the first and second operation result registers, and the second data block register. When data is being written to, the exclusive OR operation of the data stored in the first data block register and the data stored in the first operation result register is performed. Is stored in the second operation result register, and when data is being written in the first data block register, the data stored in the second data block register and the second operation result register are stored. And a data storage disk for performing an exclusive OR operation with the stored data and storing the operation result in the first operation result register. The location, when writing data in block units, also the same data constitute the array type storage device so as to be supplied to the computing means.

[0010]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a schematic structure of an array type memory device according to an embodiment of the present invention. As shown in the figure, the array type storage device 11 of the embodiment comprises a processor 12, a data transfer control unit 13, four sets of disk controllers 14 and disk devices 15, a parity generation unit 16, and an interface 17. Interface 1
An external device 31 such as a host computer is connected via 7.

In the array type storage device of the embodiment, as schematically shown in FIG. 2, among the four disk devices, three are data (“bloc”) divided into blocks.
k 1 ”,“ block 2 ”, ...) Used to store parity (“ parity 1 ”,
It is used to store "parity 2", ...).

The processor 12 realizes such a data storage mode. The processor 12 interprets the content of the command input from the external device 31 and gives an operation instruction to each section according to the content. By outputting, the array type storage device 11 is controlled so that it can be regarded as one disk device from the external device 31. The program defining the operation procedure is stored in a read only memory (ROM) (not shown).

The data transfer control unit 13 includes a processor 12
Is a circuit that transfers data supplied from the external device 31 to each disk device and data read from each disk device to the external device 31 in accordance with an instruction from the disk controller 14 ₁ by the bus 18. Through 14 ₃ and the parity generator 16.

The disk controller 14 is a control circuit for controlling the disk device 15. For example, at the time of writing data, it receives data in word units (bus width) from the data transfer control unit 13 and data for one sector. The disk device 1
Store in 5. A control signal line (not shown) is provided between the disk controller 14 and the data transfer control unit 13, and data transfer between the two is performed by so-called REQ / ACK handshake. ing.

FIG. 3 shows a schematic configuration of the parity generator. The parity generation unit 16 is a circuit that creates a parity, and as shown in the figure, the parity generation unit 16 includes:
Three registers 21 to 23 for temporarily storing data in word units and two data (word units)
And an XOR operation unit 25 that performs an exclusive OR operation of. In addition to these circuits, the parity generation unit 16 is provided with a control circuit (not shown) that outputs an operation instruction signal to each data storage / processing circuit.

A control signal provided to the disk controllers 14 ₁ to 14 ₃ is branched and input from the data transfer control unit 13 to the control circuit provided in the parity generation unit 16, and the control circuit controls the data transfer control. When the unit 13 detects that the ACK signal has been supplied to the disk controllers 14 ₁ to 14 ₃ , it sends the bus 1 to the register 21.
8 and the data stored in the register 23 are loaded into the register 22.

Then, the register 21 and the register 22
Register 21 and register 2 after the contents of
The exclusive OR operation of the two data stored in 2 is output to the XOR operation unit 25, and the operation result is stored in the register 23. It should be noted that the series of processing performed after the ACK signal is detected (processing up to the storage of the calculation result output by the XOR calculation unit 25 in the register 23) is performed by
It can be completed by the time the CK signal is detected.

The overall operation of the array type memory device of the embodiment will be described below with reference to FIGS. 2 and 4 to 10. It should be noted that FIG. 4 shows that when a data write request is received,
6 is a flowchart showing an operation procedure of a processor and a data transfer control unit. 5 to 10 are diagrams schematically showing the data processing procedure in the parity generation unit.

As shown in FIG. 2, the array type memory device of the embodiment is configured as a memory device accessed in units of 3 sectors, and when writing data, data of 3 sectors is stored in an external device. From the disk device 15 ₁ to 15 ₃ (“disk # 1” to “disk # 3”) by dividing the transferred data from the word unit block data (“block 1” to “block N”) ). At that time, "block 1", "block 2",
Parity is calculated based on three block data corresponding to the position within one sector of data to be stored in each disk device, such as "parity 1" is created from "block 3". The calculated parity is stored in the disk device 15 _P (“disk #P”).

In the array type storage device of the embodiment, data storage in such a form is realized by the following procedure.

As shown in FIG. 4, the array-type storage device (processor) that has received a data write request from an external device interprets the request content and sends it to the data transfer control unit and each disk controller. , A data transfer command corresponding to the request content is set (step S101).

For example, when the write request is for instructing to write data for 3 sectors, the processor designates the four disk controllers in the data write request. The data transfer control unit by instructing to write data for one sector to the address (logical address of the disk device) determined according to the address (logical address of the array type storage device). In this case, it is instructed to repeat the processing of steps 102 to 106 until the transfer of data for 3 sectors is completed.

After that, the data transfer control unit first instructs the parity generation unit to clear the register 0 to "0" (step S102), and then sequentially to the three disk controllers # 1 to # 3. The block data is transferred (steps S103 to S105). At the time of data transfer in each of these steps S103 to S105, the data transfer control unit performs an AC operation to the disk controllers # 1 to # 3, respectively.
Since the K signal is output, the block data is also fetched by the parity generation unit having the above-mentioned configuration.

For example, when the data transfer control unit transfers "block 1" to the disk controller # 1, it is connected to the XOR operation unit in the parity generation unit as schematically shown in FIG. One of the registered registers 21
Data "block 1" is written to the other register 22
The register 2 cleared to "0" in step 103.
The contents of 3 will be written. Further, thereafter, the parity generation unit performs an exclusive OR operation of the contents of the registers 21 and 22 as schematically shown in FIG. 6, so that “block 1” is stored in the register 23 after all. Will be done.

Therefore, when "block 2" is transferred to the disk controller # 2, as shown in FIG.
Register 21 is "block 2" and register 22 is "bloc".
k 1 ”will be stored, and as shown in FIG.
The exclusive OR of “block 1” and “block 2” is stored in the register 23. In addition, “block 3”
Is transferred to the disk controller # 3, as shown in FIG.
10, the register 21 stores “block 3” and the register 22 stores the exclusive OR of “block 1” and “block 2”. After a predetermined time, as shown in FIG.
The exclusive OR of the three block data is output on the bus from the OR operation unit.

In this state, the ACK signal is supplied from the data transfer control circuit to the disk controller #P (step S106), so that the disk controller #P receives the input of one word of parity. That is, the disk controller #P acquires the parity data for one block almost at the same time when the disk controller # 3 acquires the block data, and when the parity data for one sector is prepared, the disk controller #P sends the data to the disk device. Execute writing.

As described above, the array type memory device of the embodiment has a structure that can be manufactured at a lower cost as compared with the conventional technique, but can execute the parity writing at the same time as the data writing.

In the array type storage device of the embodiment, the parity generating unit is configured such that the exclusive OR operation is completed while the disk controller receives the transfer of one block of data. You may comprise a parity production | generation part as shown.

That is, the data on the bus 18 is ACK
In synchronization with the signal, the two registers 21 ₁ and 21 ₂ are alternately stored, and the operation result is also alternately stored in the _two registers 22 ₁ and 22 ₂ , and is written. XOR operation unit 25 performs the exclusive OR operation between the data in register 21 which is completed, for example, in register 21 ₁ and register 22 ₁ , and the operation result is stored in register 22 ₂ . Be prepared to do so. With such a configuration, the parity generation unit can be configured using an element that does not operate at high speed.

[0031]

As described above, in the present invention, the parity is calculated by sequentially using the data in block units supplied to each disk device for the calculation, and therefore, the performance at the time of writing data is improved. An array type storage device that does not deteriorate can be constructed at a lower cost than conventional devices.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an array type storage device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a data storage form in the array-type storage device of the embodiment.

FIG. 3 is a block diagram showing a configuration of a parity generation unit provided in the array-type storage device of the embodiment.

FIG. 4 is a flowchart showing an operation procedure of the array type storage device of the embodiment.

FIG. 5 is a first schematic diagram for explaining the operation of the parity generation unit in the array storage device of the embodiment.

FIG. 6 is a second schematic diagram for explaining the operation of the parity generation unit in the array storage device of the embodiment.

FIG. 7 is a third schematic diagram for explaining the operation of the parity generation unit in the array-type storage device of the embodiment.

FIG. 8 is a fourth schematic diagram for explaining the operation of the parity generation unit in the array-type storage device of the embodiment.

FIG. 9 is a fifth schematic diagram for explaining the operation of the parity generation unit in the array storage device of the embodiment.

FIG. 10 is a sixth schematic diagram for explaining the operation of the parity generation unit in the array storage device of the embodiment.

FIG. 11 is a block diagram showing a schematic configuration of another parity generation unit that can be used in the array-type storage device of the embodiment.

FIG. 12 is a schematic configuration diagram of a conventional array type storage device. 11 ... Array type storage device, 12 ... Processor, 13
... data transfer control circuit, 14 ... disk controller,
15 ... Disk device, 16 ... Parity generation unit, 21, 2
2, 23 ... Register, 25 ... XOR operation unit

Claims (2)

[Claims] 1. N data storage disk devices for storing data, one parity storage disk device for storing the parity of data stored in these N disk devices, and An exclusive OR operation of the data stored in and the input data and the operation means for rewriting the internally stored data with the operation result, and when the data of a predetermined size to be written are input,
Clearing means for clearing the data stored in the computing means to zero, dividing means for dividing the data of the predetermined size into N data blocks, and N data blocks divided by the dividing means, The N data storage disk devices and the data supplying means for supplying the arithmetic means, and when the supply of N data blocks by the data supplying means is completed, the arithmetic result of the arithmetic means is used for the parity memory. An array type storage device comprising: parity writing means for writing to a disk device. 2. N data storage disk devices for storing data, one parity storage disk device for storing the parity of data stored in these N disk devices, When the first and second data block registers and the first and second operation result registers are provided and data is being written to the second data block register,
An exclusive OR operation is performed on the data stored in the first data block register and the data stored in the first operation result register, and the operation result is stored in the second operation result register, When data is being written to the data block register, an exclusive OR operation is performed on the data stored in the second data block register and the data stored in the second operation result register. An operation means for storing the operation result in the first operation result register, and when data of a predetermined size to be written is input,
Clear means for clearing the data stored in the arithmetic register in the arithmetic means to zero, dividing means for dividing the data of the predetermined size into N data blocks, and N data divided by the dividing means. Data supply means for sequentially supplying blocks to the N data storage disk devices and writing to the first or second data block register in the operation means, and operation for the Nth data block of the operation means An array type storage device, comprising: a parity writing means for writing a result to the parity storage disk device.