JPH08190486A - Signal change detecting processor - Google Patents

Abstract

PURPOSE: To obtain a signal change detecting processor which reduces the overhead of software and can recognize state change of a generated event without any omission. CONSTITUTION: This signal change detecting processor is equipped with a buffer 3 for an external interface for periodically inputting external data, a previous value holding memory 7 which holds last external data gathered in the external interface buffer 3 as previous value data, and a data change detecting circuit 9 which informs the software of an interruption when the contents of the both are compared with each other and a difference is detected and generates a signal for instructing the previous value holding memory 7 to fetch the external data held in the external interface buffer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal change detection processing device for simplifying software interrupt processing when a state change is detected.

[0002]

2. Description of the Related Art Conventionally, when a state change is detected, the hardware notifies the software by an interrupt when the state change occurs, and when the state change occurs in the interrupt acceptance procedure of the software that receives the state change. There are an interrupt method for executing a corresponding process and a look-in method for executing a process when the event periodically occurs when the software inquires whether a state change has occurred.

FIG. 6 is a block diagram showing a system in which conventional software interrupt processing is realized when such a state change is detected. In the figure, 1 is a central processing unit (hereinafter, CPU) that controls the entire system according to software stored in an internal memory.
2 is external data sent from the outside to the system, and 3 is an external interface buffer for interfacing with the outside and periodically taking in the external data 2. Reference numeral 4 is a data collection signal sent from the software of the CPU device 1 to the external interface buffer 3 at a fixed cycle and instructing the transfer of the external data 2. Reference numeral 5 is the external interface buffer 3 receiving this data collection signal 4. The data is transferred to the CPU device 1.

Next, the operation will be described. Here, FIG.
9 is a flowchart showing a process of a software control unit in the CPU device 1, FIG. 8 is a flowchart showing an asynchronous event processing procedure executed each time an asynchronous event occurs, and FIG.
Is a flowchart showing an interrupt signal look-in processing procedure, FIG. 10 is a flowchart showing an interrupt signal receiving procedure, and FIG. 11 is a flowchart showing a look-in procedure.

First, in FIG. 7, when the program is started, the interrupt signal look-in initialization procedure is called as an argument at the entry address of the asynchronous event processing procedure (step ST1). Next, it is determined whether or not the loop has ended (step ST2), and this program ends when the loop ends. On the other hand, when the loop is not completed, the look-in procedure is called (step ST3), and after the loop processing is executed (step ST4), the process returns to step ST2 and the loop end is determined again.

When the interrupt signal look-in initialization procedure is called in step ST1 of FIG.
As shown in, first, the interrupt counter (CNT) provided inside is cleared to "0" (step ST21).
Next, the entry address (Proc) of the asynchronous event processing procedure given as a call argument is set in the internally provided processing procedure registration work (IntP) (step ST22), and the software is notified by specifying the asynchronous event and interrupt at the time of occurrence. The notification of the procedure to be received and the notification of the interrupt signal reception procedure is set (step ST23), and a series of processing is ended.

When an asynchronous event is designated in step ST23 of FIG. 9, the software calls an interrupt signal reception procedure by an interrupt as an operation for which notification is set, as shown in FIG. 10, and is described in step ST23. The process is executed again (step ST31). Next, "1" is added to the value of the interrupt counter to record the occurrence of one asynchronous event (step ST32), and this series of procedures is completed.

When the look-in procedure is called in step ST3 of FIG. 7, it is determined whether the value of the interrupt counter is "0" as shown in FIG. 11 (step ST41). In the case of "0", it is determined that an asynchronous event has not occurred, and the procedure ends. If it is other than "0", it is determined that the asynchronous event has occurred the number of times of this value, "1" is subtracted from the value of the interrupt counter (step ST42), and the processing procedure registration work is performed. The procedure of the set entry address is called (step ST43). After that, returning to step ST41, the value of the interrupt counter is judged again, and this is "0".
Repeat this procedure until.

As a document describing a technique related to the conventional software interrupt processing at the time of detecting such a state change, for example, Japanese Patent Application Laid-Open No. 4-1122 is available.
No. 34 publication and the like.

[0010]

Since the conventional software interrupt processing at the time of detecting a state change is executed as described above, the software processing is complicated and the software interrupt processing is performed when the state changes occur frequently. In addition to the increase in the processing overhead, there is a problem in that if the status change of the same event occurs frequently, it is not always possible to recognize all the status changes.

The present invention has been made in order to solve the above-mentioned problems, and the software overhead does not increase when the status changes frequently and the interrupt notifications to the software increase. It is another object of the present invention to provide a signal change detection processing device capable of recognizing the state change of an event that has occurred without omission.

[0012]

According to a first aspect of the present invention, there is provided a signal change detection processing device, the contents of an external interface buffer for periodically receiving external data input from the outside, and the external interface. The previous external data collected in the buffer for data is compared with the contents of the previous value holding memory that holds the previous value data, and if a difference is detected between the two, an interrupt is sent to the software and A data change detection circuit for generating a signal for instructing the previous value holding memory to take in the external data held by the external interface buffer is provided.

Further, the signal change detection processing device according to the invention of claim 2 is provided with a counter for counting the signal for notifying the software of the interrupt, and the software is provided when the counted value reaches a specified value. To generate an interrupt for.

Further, the signal change detection processing device according to the invention of claim 3 further comprises a software interface buffer which is accessed by software when an interrupt occurs so that the external data and the previous value data are different from each other. The state change data generated by the data change detection circuit is held.

Further, the signal change detection processing device according to the invention of claim 4 further comprises a timer for monitoring the elapsed time from the generation of the signal for notifying the software of the interrupt, and When the elapsed time reaches a predetermined time, the software interrupt is generated even if the count value of the counter is equal to or less than the specified value.

Further, the signal change detection processing device according to the invention of claim 5 is provided with a state detection circuit for temporarily holding the signal for notifying the software of the interrupt and detecting the load state of the software. After detecting that the software load has decreased, an interrupt to the software is generated.

Further, the signal change detection processing device according to the present invention further comprises a timer for monitoring the signal holding time by the state detection circuit, and when the holding time reaches a predetermined time. Is forcibly generating an interrupt to software.

[0018]

In the data change detection circuit according to the present invention, the external data held by the external interface buffer is compared with the previous value data held by the previous value holding memory to detect a difference between the two. Then, when an interrupt to the software is notified by generating a signal for instructing the interrupt to the software and the fetching of the external data held by the external interface buffer to the previous value holding memory, The overhead is reduced by shifting the processing performed by software up to now to hardware, and letting the software perform only the simple processing of processing the data of the state change.

The counter according to the second aspect of the present invention counts the signal for notifying the software of the interrupt, so that the state change is constant in the system in which the interrupt notification to the software frequently occurs. The interrupt to the software is generated only when the number of occurrences exceeds the limit.

Further, in the signal change detection processing device according to the present invention, the software interface buffer stores the state change data generated by the data change detection circuit when the external data differs from the previous value data. The software holds the buffer for the software interface when an interrupt occurs, so that the software can recognize all the state changes of the occurred event without omission.

Further, the timer according to the invention as set forth in claim 4 measures the elapsed time from the generation of the signal notifying the software of the interrupt so that the number of state changes is less than the specified value. Also, when a predetermined time elapses, an interrupt to the software is generated so that the immediacy from the occurrence event is not impaired.

According to the fifth aspect of the present invention, the state detection circuit temporarily holds the signal generated by the data change detection circuit and detects the load state of the software so that the software does nothing. The idle time can be utilized to process the interrupt, further reducing the software overhead.

Further, the timer according to the invention as set forth in claim 6 measures the signal holding time by the state detection circuit to interrupt the software when the software processing continues and the idle time cannot be detected. Are forced to occur so that the immediacy from the occurrence event is not impaired.

[0024]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a hardware configuration of a signal change detection processing device according to a first embodiment of the present invention.
In the figure, 1 is a CPU device, 2 is external data, 3 is an external interface buffer, 4 is a data collection signal, and 5 is a data collection signal.
Is data sent to the CPU device 1 and is the same as or equivalent to those of the conventional device denoted by the same reference numeral in FIG.

Reference numeral 6 denotes external data output from the external interface buffer 3 which receives the data collection signal 4 from the CPU device 1. Reference numeral 7 denotes the external interface buffer 3 which receives a data rewriting signal described later. The previous value holding memory that holds the sent external data 6 as the previous value data, and 8 is the previous value data that is output from the previous value holding memory 7 that receives the data collection signal 4 from the CPU device 1. 9
Compares the external data 6 output from the external interface buffer 3 with the previous value data output from the previous value holding memory 7, and if it is detected that there is a difference between them, the software of the CPU device 1 Interrupt to
A data change detection circuit for generating a signal (hereinafter referred to as a change detection signal) for instructing the previous value holding memory 7 to fetch the external data 6 sent from the external interface buffer 3, and 10 is the change detection signal. is there.

Reference numeral 11 is based on this change detection signal 10.
An interrupt signal for notifying the software of the CPU device 1 of an interrupt and the data rewriting signal for instructing the fetching of the external data 6 sent from the external interface buffer 3 to the previous value holding memory 7 are generated. Reference numeral 12 is an interrupt generation circuit, and 12 is its interrupt signal and 13 is a data rewriting signal. Reference numeral 14 is state change data which indicates a state change of an event generated when the external data 6 and the previous value data 8 are different from each other by the data change detection circuit 9. Reference numeral 15 holds the state change data 14 and the CPU device 1 is a buffer for a software interface for making the state change data 14 accessible when an interrupt for software is received. Note that, here, the data transferred from the software interface buffer 15 to the CPU device 1 by the access is described as data 5 corresponding to the conventional case.

Next, the operation will be described. The external interface buffer 3 for receiving the external data 2 from the outside is activated at a fixed cycle by the data collection signal 4 from the software of the CPU device 1, and holds the external data 6 held therein with the previous value holding memory 7 and the data change detection circuit. Output to 9. Further, the previous value holding memory 7 holding the previous external data 6 as the previous value data is also activated by the same data collection signal 4 at a constant cycle, and the accumulated previous value data 8 is sent to the data change detection circuit 9. Output. The data change detection circuit 9 compares the input external data 6 with the previous value data 8 to determine whether there is a state change. The result of the data comparison,
If the external data 6 and the previous value data 8 are the same, it is determined that the state has not changed, and the data change detection circuit 9 changes the detection signal 1
0 and the state change data 14 are not output.

On the other hand, if there is a difference between the external data 6 and the previous value data 8, the data change detection circuit 9 judges that there is a state change and sends a change detection signal 10 to the interrupt generation circuit 11. , Sends the status change data 14 to the software interface buffer 15 and holds it. The interrupt generation circuit 11 receiving the change detection signal 10 sends an interrupt signal 12 to the CPU device 1 to notify the software of an interrupt, and also sends a data rewrite signal 13 to the previous value holding memory 7. The previous value holding memory 7 which has received the data rewriting signal 13 discards the previous value data currently held, newly fetches the external data 6 from the external interface buffer 3, and holds it as the previous value data. . Further, the software of the CPU device 1 which has received the interrupt signal 12 from the interrupt generation circuit 11 accesses the software interface buffer 15 and fetches the state change data held therein as data 5.

As described above, the above operation is repeatedly executed, and the complicated processing by the software when the external data 2 is changed is processed by the hardware instead, thereby reducing the software overhead.

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a hardware configuration of a signal change detection processing device according to another embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 1 and their description is omitted. In the figure, 16 counts the interrupt signal 12 for notifying the software generated by the interrupt generation circuit 11 of an interrupt based on the change detection signal 10 from the data change detection circuit 9, and the counted value is This is a counter that generates an interrupt signal 17 to the software of the CPU device 1 when a predetermined specified value is reached.

Next, the operation will be described. Since the basic operation is the same as that of the first embodiment, the description thereof is omitted here. The data change detection circuit 9 sends a change detection signal 10 to the interrupt generation circuit 11 each time a difference between the external data 6 and the previous value data 8 is detected, and the state change data 14 is sent to the buffer 15 for software interface. To send. The software interface buffer 15 holds the sent state change data 14 until it is accessed by the software of the CPU device 1. on the other hand,
Upon receiving the change detection signal 10, the interrupt generation circuit 11 sends a data rewrite signal 13 to the previous value holding memory 7 and at the same time, C
An interrupt signal 12 for notifying an interrupt to the software of the PU device 1 is generated.

The interrupt signal 12 is not directly sent to the CPU device 1, but is once input to the counter 16. The counter 16 counts the interrupt signal 12 and generates an interrupt signal 17 when the count value reaches a preset specified value to notify the software of the CPU device 1 of an interrupt. Upon receiving the interrupt signal 17 generated by the counter 16, the software of the CPU device 1 accesses the software interface buffer 15 and fetches all the state change data held up to that point as the data 5.

As described above, in the first embodiment described above, the processing in which the software overhead is apt to be large when the state changes occur frequently, and in the second embodiment, the counter 16 causes the state change to occur a certain number of times or more. When it is detected, the software overhead is further reduced by notifying the software of the interrupt notification for several times at one time. In addition, a buffer 16 for software interface is provided, and the state change data 1 for several times
Since 4 is stored without omission, the software can recognize all occurrence events by receiving only one interrupt.

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing a hardware configuration of a signal change detection processing device according to still another embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 2 and their explanations are omitted. In the figure, reference numeral 18 indicates that the interrupt generation circuit 11 is a change detection signal 10 from the data change detection circuit 9.
Based on the above, the elapsed time from generation of the interrupt signal 12 for notifying the software to the software is measured, and when the predetermined time has elapsed, the CPU device is 1 is a timer for generating an interrupt signal 17 to the software of 1.

Next, the operation will be described. Since the basic operation is the same as that of the second embodiment, its explanation is omitted here. An interrupt signal 12 sent from the interrupt generation circuit 11 for notifying an interrupt to the software is sent to a counter 16 and a timer 18. The counter 16 counts the interrupt signal 12, and when the count value reaches a specified value, the interrupt signal 17 is generated and the CPU device 1
Notify the software of the interrupt. On the other hand, the timer 18 is reset by the generation of the interrupt signal 17,
After that, when the interrupt signal 12 is input from the interrupt generation circuit 11, time counting is started, and when a predetermined predetermined time elapses and a time-out occurs, an interrupt signal 17 to the software of the CPU device 1 is generated.

Therefore, when the count value of the counter 16 reaches the specified value within a predetermined time after the timer 18 starts counting time, as in the case of the second embodiment,
An interrupt signal 17 is sent from the counter 16 to the CPU device 1, and the timer 18 is reset by this interrupt signal. On the other hand, if the count value of the counter 16 does not reach the specified value even after a predetermined time has elapsed since the timer 18 started counting time, the timer 18 sends an interrupt signal 17 to the CPU device 1, The counter 16 is cleared to "0" and the timer 18 is also reset. Upon receiving the interrupt signal 17, the software of the CPU device 1 accesses the software interface buffer 15 and fetches all the state change data held up to that point as the data 5.

In the second embodiment, the interrupt is not notified to the software unless the state change occurs a certain number of times or more, but in the third embodiment, the timer 18 is used.
Even if the number of occurrences of state change is less than a certain number of times, it is possible to notify the software of an interrupt by the elapsed time from the first occurrence of state change, and prevent the immediacy from being impaired. ing.

Example 4. Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing a hardware configuration of a signal change detection processing device according to still another embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 1 and their description is omitted. In the figure, 19 receives an interrupt signal 12 for notifying software of an interrupt generated by an interrupt generation circuit 11 based on a change detection signal 10 from a data change detection circuit 9, and temporarily suspends it. Then, the load state of the software of the CPU device 1 is detected, and when the load is reduced, for example, when the software enters an idle state in which no processing is performed,
A state detection circuit for generating an interrupt signal 17 to the software. Reference numeral 20 is a status signal sent from the CPU device 1 to the status detection circuit 19 for notifying a software load status, for example, a busy / idle status.

Next, the operation will be described. Since the basic operation is the same as that of the first embodiment, the description thereof is omitted here. The interrupt generation circuit 11, which has received the change detection signal 10 from the data change detection circuit 9, sends out the data rewrite signal 13 to the previous value holding memory 7, and at the same time, the CPU
An interrupt signal 12 for notifying the software of the device 1 of an interrupt is generated. This interrupt signal 12 is directly C
It is not input to the PU device 1 but is sent to the state detection circuit 19 and temporarily held. The state detection circuit 19 discriminates from the state signal 20 sent from the CPU device 1 whether the software is busy performing some processing or idle without any processing. If you are busy,
Continue to hold the interrupt signal 12 from the interrupt generation circuit 11,
When it detects that the idle state is entered, it generates an interrupt signal 17 to notify the software of the CPU device 1 of an interrupt. Upon receiving the interrupt signal 17 generated by the state detection circuit 19, the software of the CPU device 1 accesses the software interface buffer 15,
The state change data held therein is fetched as data 5.

In the first to third embodiments described above, regardless of the processing state of the software, if the conditions are satisfied, the software is notified of the interrupt, and the software interrupts the processing currently being performed and processes the interrupt. However, in the fourth embodiment, by providing the state detection circuit 19,
Since the interrupt is notified only when the software is not processing, the software can finish the processing being executed without interruption. Further, since the interrupt processing is performed by utilizing the idle time of the software, it leads to the speedup of the system, and the overhead of the software can be further reduced.

Example 5. Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a hardware configuration of a signal change detection processing apparatus according to still another embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 4 and their explanations are omitted. In the figure, reference numeral 21 indicates that an interrupt signal 12 generated by an interrupt generation circuit 11 based on a change detection signal 10 from a data change detection circuit 9 for notifying an interrupt to software is held in a state detection circuit 19. The time is measured, and when the predetermined time has elapsed, the CPU
It is a timer for forcibly generating an interrupt signal 17 to the software of the device 1.

Next, the operation will be described. Since the basic operation is the same as that of the fourth embodiment, the description thereof is omitted here. An interrupt signal 12 sent from the interrupt generation circuit 11 for notifying an interrupt to the software is sent to a state detection circuit 19 and a timer 21,
The state detection circuit 19 holds the interrupt signal 12 until the software becomes idle. On the other hand, timer 2
1 is reset by the generation of the interrupt signal 17, and then the interrupt signal 12 is input from the interrupt generation circuit 11 to start timing, and forcibly interrupt when the predetermined time elapses and a timeout occurs. Generate signal 17,
An interrupt is notified to the software of the CPU device 1.

Therefore, if the idle state of the software is detected by the state detection circuit 19 between the time when the timer 21 starts counting the time and the predetermined time elapses, as in the case of the fourth embodiment, the interrupt is performed. The interrupt signal 17 is sent from the state detection circuit 19 to the CPU device 1, and the timer 21 is reset by the interrupt signal 17. On the other hand, the timer 21
If the idle state of the software is not detected even after the lapse of a predetermined time after the timer starts counting, the timer 21 forcibly outputs the interrupt signal 17 to the CPU device 1. The timer 21 is also reset by 17. The software of the CPU 1 which receives the interrupt signal 17 is the software interface buffer 1
5 is accessed and the state change data held therein is fetched as data 5.

In the fourth embodiment described above, if the software processing is continuously processed and the software does not enter the idle state, the immediacy from the occurrence event may be impaired. By providing the timer 21, it is possible to compulsorily notify the software of the interrupt when the idle state of the software cannot be detected, thereby preventing the immediacy from being impaired.

[0045]

As described above, according to the invention described in claim 1, the data change detection circuit for comparing the external data and the previous value data to detect the difference therebetween is provided, and the difference is detected. When this occurs, it is configured to notify the software of an interrupt and generate a signal for instructing the previous value holding memory to fetch the external data held by the external interface buffer. When an interrupt is notified, the processing that was previously performed by software is performed by hardware, so software only needs to perform simple processing that processes state change data, and complicated processing is required. Signal change detection processor that can reduce the software overhead much more than ever before. There is an effect.

According to the second aspect of the present invention, a counter for counting the signal for notifying the software of the interrupt is provided, and the software interrupt is generated when the count value reaches a specified value. Since it is configured such that it is possible to convert an interrupt due to several state changes into one interrupt, there is an effect that the software overhead can be further reduced.

According to the third aspect of the invention, a software interface buffer that is accessed by software when an interrupt occurs is further provided,
Since the state change data indicating the state change of the event sent by the data change detection circuit is held when the external data and the previous value data are different from each other, the software does not need to execute once even if the state changes occur frequently. The effect of making it possible to recognize all occurrence events without omission by simply receiving the interrupt of.

Further, according to the invention described in claim 4, a timer is further provided for monitoring the elapsed time from the generation of the signal for notifying the software of the interrupt, and the elapsed time is set to a predetermined value. When the time is reached, it is configured to generate an interrupt to software even if the count value of the counter is less than the specified value, so if the time elapsed from the occurrence of a state change exceeds a predetermined time, a certain number of times or more Even if the state change has not occurred, the software is forcibly interrupted, so that it is possible to prevent the immediacy from being impaired.

According to the fifth aspect of the present invention, the signal for notifying the software of the interrupt is temporarily held, and a state detection circuit for detecting the load state of the software is provided so that the load of the software is reduced. Since it is configured to generate an interrupt to the software after it detects that the size has decreased, it becomes possible to execute the interrupt processing by using the idle time of the software, which can speed up the entire system. Therefore, there is an effect that the software overhead can be further reduced.

Further, according to the invention described in claim 6, a timer for monitoring the signal holding time by the state detection circuit is further provided, and when the holding time reaches a predetermined time, an interrupt to the software is forcibly made. Since it is configured to generate, even if the software is continuously executing the processing and the idle time cannot be detected, the interruption to the software is forcibly generated when the predetermined time elapses, so the immediacy is impaired. There is an effect that can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal change detection processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a signal change detection processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a signal change detection processing device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a signal change detection processing device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a signal change detection processing device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a system in which conventional software interrupt processing is realized.

FIG. 7 is a flowchart showing a process of a control unit of conventional software.

FIG. 8 is a flowchart showing an asynchronous event processing procedure in the conventional method.

FIG. 9 is a flowchart showing an interrupt signal look-in processing procedure in a conventional method.

FIG. 10 is a flowchart showing an interrupt signal receiving procedure in the conventional method.

FIG. 11 is a flowchart showing a look-in procedure in the conventional method.

[Explanation of symbols]

3 external interface buffer, 7 previous value holding memory, 9 data change detection circuit, 15 software interface buffer, 16 counter, 18, 21
Timer, 19 status detection circuit.

Claims (6)

[Claims] 1. An external interface buffer for periodically capturing external data input from the outside, and a previous value holding memory for holding the previous external data collected by the external interface buffer as previous value data. Comparing the contents of the external interface buffer with the contents of the previous value holding memory, when it is detected that there is a difference between the two, an interrupt is notified to software and the previous value holding memory And a data change detecting circuit for generating a signal for instructing the fetching of the external data held by the external interface buffer. 2. A counter is provided, which counts a signal for notifying an interrupt to the software and generates an interrupt to the software when the count value reaches a specified value. The signal change detection processing device according to claim 1. 3. A buffer for a software interface, which holds status change data indicating a status change of an event generated when the external data and the previous value data are different from each other by the data change detection circuit, and which is accessed by software when an interrupt occurs. The signal change detection processing device according to claim 2, further comprising: 4. The elapsed time from generation of a signal for notifying an interrupt to the software is measured,
4. The signal change detection processing device according to claim 2, further comprising a timer for generating an interrupt to the software even when the count value of the counter is equal to or less than the specified value when a predetermined time has elapsed. . 5. When a signal for notifying the software of an interrupt is received, the signal is temporarily held to detect the load state of the software, and an interrupt to the software is generated when the load becomes small. 2. A state detection circuit for controlling the state is provided.
A signal change detection processing device according to item 1. 6. A timer is provided, which measures a holding time of a signal for notifying an interrupt to the software by the state detection circuit, and forcibly generates an interrupt to the software when a predetermined time elapses. The signal change detection processing device according to claim 5.