JPH08186547A - Device and method for scramble and device and method for descramble - Google Patents

Abstract

PURPOSE: To improve the privacy of scramble. CONSTITUTION: Real data to be recorded in the data part of a packet composed of the header of 4 bytes and the data part of 184 bytes are scrambled by adding pseudo random sequences. An initial value for generating these pseudo random sequences is changed before and after the bits (512 bits) expressed by the first 10 bits, for example.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for scrambling or descrambling digital data in a digital broadcasting system for transmitting digital data such as video and audio through a broadcasting satellite, a communication satellite or the like. The present invention relates to a scramble apparatus and method, and a descramble apparatus and method.

[0002]

2. Description of the Related Art In contract broadcasting, a broadcasting system called scramble broadcasting is often used. In this scrambled broadcasting, the broadcasting station side intentionally disturbs the original signal by a predetermined method so that normal images and audio data are used even if a person who does not have a contract with the broadcasting station receives the broadcasting. It is something that you can't do. A decoder is given to a person who has a contract with the broadcasting station, and the scrambled data is descrambled to the original form so that normal image and audio data can be obtained.

[0003] In scrambled broadcasting, even if the broadcast is received by a person who does not have a contract, the scrambled broadcasting is scrambled by a method that is difficult to descramble as much as possible so that the content is not known. Is desirable.

Scramble systems are roughly classified into two types. One is a stream cipher, and the other is a block cipher.

The stream cipher is a method of scrambling the original signal by generating a pseudo random signal and adding the pseudo random signal to the original signal by modulo 2.

On the other hand, the block cipher is a DES
(Data Encryption Standard)
As described above, the original signal is divided in block units, and complicated processing is repeated in each block.

The stream cipher has an advantage that the hardware configuration is simple, but has a drawback that it is easily decoded. On the other hand, block cipher
While it has the advantage of being difficult to decipher, it has the disadvantage of a complicated hardware configuration.

ISO (International O)
rganization for Standarddiz
ation) / IEC (International
Electro-technjcal Comiss
Ion) 13818-1 (MPEG2 System)
In s), it is standardized to multiplex and transmit multimedia data in units of transport packets. This packet has a length of 188 bytes, and digital video, digital audio, and data signals are
It is multiplexed in packet units. In order to flexibly perform the multiplexing, it is preferable that the scrambling be completed in units of packets because the packets can be freely edited in the subsequent transmission system. In addition, this also has less effect on packet loss and the like.

By the way, as a device for scrambling data to be transmitted through a broadcasting satellite, "Telecommunication Technology Council Report" of June 21, 1993, "Consultation No. 53", "Technology concerning data broadcasting by broadcasting satellite" Among the "conditions," the scramble device shown in FIG. 7 has been proposed as "a transmission control system, a pay system, and a technical condition of each signal of facsimile, telesoftware, still image, character (basic), and time".

The scramble key has a 32-bit initial value and a 4-bit modification control value. The initial value is loaded into the initial value register 1, and the modification control value is loaded into the modification control register 5. This loading is performed when the key update timing flag SCT is a packet of 1.

The initial value register 1 is composed of 32 stages of feedback shift registers. The data loaded in the initial value register 1 is shifted from the lower bit to the upper bit in accordance with the shift signal.

When the value of the continuity index CI of the previous packet (which takes any value from 0 to 15) is 15 and the CI value of the packet is 0, the carry of the CI is set to 1. In other cases of CI carry (continuity index is 1
It is 0 when the change is other than the change from the packet of 5 to the packet of 0). When the value of this CI is 1 and the output f3 of the modification control register 5 is 1, the AND gate 1
0 outputs a logic 1. The logic 1 is input to the initial value register 1 as a shift signal via the AND gate 6 when the scramble key update timing flag SCT is 0, that is, except when the initial value register 1 is loaded. The initial value register 1 performs a shift operation in response to this logic 1 shift signal.

The 32-bit initial value output from the initial value register 1 is input to the initial value adjusting circuit 2 and adjusted. This modification is performed by the outputs f0 to f of the modification control register 5.
2 and the logical channel identifications LCI1 and LCI2 for identifying the logical channel for transmitting digital data and the continuity index CI are ANDed by AND gates 7 to 9 to obtain the initial value modification data.

The modified initial value output from the initial value modification circuit 2 is PRPS (Pseudo-random bibi).
(ary sequence: pseudo-random binary signal sequence), which is input to the generation circuit 3. PRBS generation circuit 3
When the predetermined load signal is input, the modified initial value is loaded, and when the predetermined shift signal is input through the AND gate 11, the modified initial value is shifted to generate the PN signal. (Pseudo random signal) is generated.
When the scramble identification flag SCF is 1, this PN signal passes through the AND gate 4 and is input to the adder 12. The adder 12 adds the PN signal input from the AND gate 4 to the packet data supplied from a circuit (not shown), and outputs it as encrypted packet data.

This apparatus is based on the above-mentioned MPEG2 Sys.
It can be considered to be used for scrambling transport packets of tems.

[0016]

However, in the device proposed by the above report, since the initial value modification data is generated from the logical channel identification and the continuity index, scrambled data can be relatively easily created. There was a risk of being descrambled.

The present invention has been made in view of the above circumstances, and is intended to reduce the risk of descrambling and further enhance confidentiality.

[0018]

A scrambling device according to claim 1 is a scrambling device for scrambling digital data transmitted in packet units in packet units, and initial value generating means for generating a predetermined initial value. Based on the initial value register 1 in FIG. 1, initial value modifying means for modifying the initial value based on the initial value modification data (for example, the initial value modification circuit 2 in FIG. 1), and the modified initial value. Pseudo-random sequence generation means (for example, PRBS generation circuit 3 in FIG. 1) that generates a random sequence, addition means (for example, adder 12 in FIG. 1) that adds the pseudo-random sequence to digital data, and an initial value in the middle of the packet. And a changing means (for example, the key switching circuit 21 in FIG. 1) for changing at the change point.

A changing means (for example, the bit detecting section 22C in FIG. 1) for changing the change point of the initial value can be further provided, and the change point can be changed corresponding to the actual data included in the packet.

The initial value is composed of two 32-bit keys, and the changing means can change from one key to the other key at one change point in the packet. .

In order to generate the initial value modification data, the packet ID or the continuation counter included in the header of the packet is detected by the detection means (eg, FIG. 1).
ID detector 22A, CC detector 22B) can be further provided.

A scramble method according to a sixth aspect is a scramble method in which digital data transmitted in packet units is scrambled in packet units, and a predetermined initial value is generated, and the initial value is adjusted based on the initial value modification data. It is characterized in that a pseudo random sequence is generated based on the modified and modified initial value, the pseudo random sequence is added to the digital data, and the initial value is changed in the middle of the packet.

The descrambling apparatus and method can be realized with the same configuration. $

In the scrambling device according to the first aspect and the scrambling method according to the sixth aspect, the initial value is modified based on the initial value modification data, and the pseudo-random sequence is generated based on the modified initial value. To be done. Then, the pseudo random sequence is added to the digital data and scrambled. Also, this initial value is changed in the middle of the packet. As a result, the number of bits in the key is increased due to the scrambling that can be used in one packet, the scrambling becomes more complicated, and the risk of unauthorized descrambling is reduced.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the above-mentioned ISO / IEC 1381.
8-1 is a block diagram showing a configuration example of a scrambling device of the present invention that scrambles a transport packet specified by 8-1 (MPEG2 Systems), and the same reference numerals are given to parts corresponding to the case in FIG. 7.
That is, also in this embodiment, the configurations of the initial value register 1 to the adder 12 are similar to those in FIG.
However, in this embodiment, the key switching circuit 21 is provided in the preceding stage of the initial value register 1, and the AND gates 7 to 10 are supplied with the signal from the modification control register 5 and output from the detection circuit 22. Signal is input. The detection circuit 22 also outputs a select signal to the key switching circuit 21.

The detection circuit 22 includes an ID detection unit 22A for detecting a packet ID contained in the packet header, and a continuity-co contained in the packet header.
CC detection unit 22 for detecting unter (continuation counter)
B, a bit detection unit 22 that detects a reference bit for generating a select signal to be output to the key switching circuit 21.
C, SCF detection section 22D for detecting the scramble identification flag SCF.

The other structure is the same as that shown in FIG.

FIG. 2 shows a configuration example of the key switching circuit 21. In this example, the key register 61 and the key register 62 store keys each having a 32-bit initial value. The selector 63 selects the 32-bit key stored in the key register 61 or the key register 62 in response to the select signal from the detection circuit 22, and the 32-bit initial value a0 as a scramble key.
To a31 are output to the initial value register 1. The initial value register 1 outputs the input initial values a0 to a31 as initial values b0 to b31.

The initial value adjustment circuit 2 is constructed, for example, as shown in FIG. In this embodiment, a total of 15-bit data g0 to g14 input from the AND gates 7 to 9 are converted into 32-bit data h0 to h31 in the connection matrix 31, respectively (h0,
h1), (h2, h3) ... (h28, h29),
As shown in (h30, h31), data is divided into units of 2 bits, and the adders 32-1 to 32-1 respectively.
6. In the adders 32-1 to 32-16,
The 32-bit initial value data b0 to b31 supplied from the initial value register 1 are (b0, b1), (b2, b
3) ... (b28, b29), (b30, b31) are divided into 2 bits each, and each is added by an adder 32.
-1 to 32-16.

Each of the adders 32-1 to 32-16 receives 2-bit data (c0, c1), (c2, c3), ... (C28, c) from the input 4-bit data.
29) and (c30, c31) are generated, and these are output to the PRBS generation circuit 3 as modified initial values.

The PRBS generation circuit 3 is constructed, for example, as shown in FIG. In this embodiment, a feedback shift register in which c0 to c7 of the modified initial values c0 to c31 output from the adders 32-1 to 32-16 of the initial value modification circuit 2 are composed of 8 stages of shift registers 41 has been input. Also, c8 to c18
Are supplied to the feedback shift register 42 configured by the 11-stage shift register. Furthermore c19
To c31 are supplied to the feedback shift register 43 composed of 13 stages of shift registers.

The feedback shift register 41 generates data d0 to d7 from the inputs c0 to c7 and outputs d0 to d5 of them to the non-linear logic 44.
The feedback shift register 42 generates data d8 to d18 from the data c8 to c18, of which d
8 to d13 are output to the non-linear logic 45. The feedback shift register 43 has data c19 to c3.
Data d19 to d31 are generated from 1, and d
19 to d24 are supplied to the non-linear logic 46, and d31
Is output to the adder 48.

The non-linear logic 44 uses the data d0 to d.
The non-linear logic 45 generates the data p2 from the data d8 to d13, and the non-linear logic 46 generates the data p3 from the data d19 to d24.

When the data p2 output from the non-linear logic 45 is 0, the switch 47 is switched to the left side in the drawing to select the output p1 of the non-linear logic 44 and adder 4
Output to 8. When the output p2 of the non-linear logic 45 is 1, the output p3 of the non-linear logic 46 is selected and output to the adder 48 by switching to the right side in the drawing. The adder 48 calculates the exclusive OR of the output p1 of the non-linear logic 44 or the output p3 of the non-linear logic 46 and the data d31 output from the feedback shift register 43, and outputs it to the AND gate 4 as a 1-bit PN signal p. Output.

The detection circuit 22 extracts the header from the input packet data. That is, the input packet data has a format as shown in FIG. The length of one packet is 188 bytes, the first 4 bytes are the header, and the remaining 184 bytes are the data part, and the actual data is arranged there.

In the header, an 8-bit synchronization byte is arranged at the head of the header, and the following 3 bits are sandwiched between the 13 bits, which are packet IDs (PID0 to PID13) for identifying video data, audio data, and the like. ing. And the last 4 bits are conti
It is assumed to be 4-bit data CCT0 to CCT3 of a numeric-counter (continuation counter).

The ID detection section 22A of the detection circuit 22 is shown in FIG.
13-bit packet ID PID0 to PID shown in
13 is detected, and 5 bits of PID0 to PID4 are output to the AND gate 7, and 6 bits of PID5 to PID10 are output to the AND gate 8. And PID11 to PID
13 and 4 bits of CCT0 of the continuation counter data CCT0 to CCT3 detected by the CC detector 22B are output to the AND gate 9.

Further, as shown in FIG. 6, the bit detector 22C detects a value of 10 bits from the head of the actual data following the header, and outputs a select signal at a timing corresponding to the detected value. For example, the first 10 bits are "10"
In the case of 00000000 "(= 512), the select signal is output at the timing 512 bits after the beginning of the actual data.

When the SCF detector 22D detects the scramble identification flag SCF of the packet header, it outputs 1 to the AND gate 4 (of course, from another circuit not shown,
It is also possible to receive the scramble instruction signal and output it to the AND gate 4. The detection circuit 22 is
The key update timing of the packet header is detected, and the key update timing flag SCT is output to the AND gate 6.

Further, the detection circuit 22 outputs a load signal at the head of the data section and outputs it to the AND gate 11 and the PRBS generation circuit 3. Further, the shift signal is output to the AND gate 11 except at the beginning of the data section.

Next, the operation will be described. The bit detection unit 22C generates a first select signal and outputs it to the key switching circuit 21 at a predetermined timing before the PN signal added to the head data of the data section is output from the PRBS circuit 3. The selector 63 of the key switching circuit 21, when the first select signal is input,
For example, the key stored in the key register 61 is selected and output to the initial value register 1 as 32-bit initial values a0 to a31.

After that, or at the same time when the initial value is input, the scramble key update timing flag SCT is input to the initial value register 1 and the 32-bit initial values a0 to a31 are loaded to the initial value register 1. .

When the scramble key update timing flag SCT is 1, the modification control register 5 loads 4-bit modification control values e0 to e3 supplied from a circuit (not shown). Then, the 4-bit data is output as it is as 4-bit outputs f0 to f3.

That is, the modification control register 5 performs the following calculation at the time of loading.

[0044]

[Equation 1]

The AND gate 10 selects the CCT1 of the 4-bit value of the continuation counter detected by the CC detector 22B.
Is 1 and the output f3 of the modification control register 5 is 1, a shift signal of 1 is output. This shift signal passes through the AND gate 6 and is input to the initial value register 1 when the key update timing flag SCT is 0 (other than at the beginning). When this shift signal is input, the initial value register 1 shifts the data from the lower bit to the upper bit bit by bit. The most significant bit is shifted to the least significant bit. The generator polynomial of the 32-stage feedback shift register forming the initial value register 1 is represented by the following equation.

G1 (x) = x ³² + x ²² + x ² + x + 1

When the outputs are b0 to b31 with respect to the input initial values a0 to a31, the initial value register 1 performs the following calculation at the time of loading and at the time of shifting.

[0048]

[Equation 2]

On the other hand, the AND gate 7 has an ID detector 22A.
Of the 13-bit packet ID detected by the CPU and the logical product of the 5-bit PID0 to PID4 and the output f0 of the correction control register 5 to calculate g10 to g14 of the 15-bit initial value correction data g0 to g14. To generate. The AND gate 8 outputs P output by the ID detection unit 22A.
The logical product of ID5 to PID10 and the modification control register f1 is calculated to generate g4 to g9. Further, the AND gate 9 has the PID 11 detected by the ID detection unit 22A.
To PID13 and C detected by the CC detector 22B
The logical product of 4-bit data of CT0 and the output f2 of the modification control register 5 is calculated to generate g0 to g3.

Connection matrix 31 of the initial value modifying circuit 2
Generates the 32-bit data h0 to h31 from the 15-bit initial value modification data g0 to g14 input from the AND gates 7 to 9 according to the table shown in Table 1 below.

[0051]

[Table 1]

The adders 32-1 to 32-16 use the outputs h0 to h31 of the connection matrix 31 and the outputs b0 to b31 of the initial value register 1 as a unit of 2 bits.
The block is divided into 6 blocks, the addition operation shown in the following equation is performed, and the obtained results are output to the PRBS generation circuit 3 as c0 to c31.

[0053]

(Equation 3)

The PRBS generation circuit 3 includes an initial value correction circuit 2
Of the 32-bit modified initial values c0 to c31 output from the adders 32-1 to 32-16 of
In the feedback shift register 41, c8 to c1
8 to the feedback shift register 42, and c1
9 to c31 to the feedback shift register 43,
Load each.

The feedback shift register 41 has eight
Comprising shift registers of stages, data d0 to d7 are generated for inputs c0 to c7 according to a generator polynomial G2 (x) represented by the following equation.

G2 (x) = x ⁸ + x ⁴ + x ³ + x ² +1

The feedback register 42 is composed of an 11-stage shift register, and uses the generator polynomial G3 (x) represented by the following equation to generate the data d8 to d18 for the inputs c8 to c18.

G3 (x) = x ¹¹ + x ² +1

The feedback shift register 43 has 1
Data d19 to d31 are generated for inputs c19 to c31 by using a generator polynomial G4 (x) represented by the following equation, which is composed of a shift register of three stages.

G4 (x) = x ¹³ + x ⁴ + x ³ + x + 1

The data shift is performed from the lower bit to the upper bit using the clock corresponding to the data of each packet.

The above feedback shift register 41
The load and shift operations in Nos. 43 through 43 can be summarized by the following equation.

[0063]

[Equation 4]

The 6-bit data d0 to d5 among the data d0 to d7 generated by the feedback shift register 41 are input to the non-linear logic 44. The non-linear logic 44 receives the data d0 to d5 and generates 1-bit data p1.

Similarly, the non-linear logic 45 has data d8 to d generated by the feedback shift register 42.
Of the 17, 17, d8 to b13 are input, and the non-linear logic 45 generates 1-bit data p2 from the data d8 to d13.

The non-linear logic 46 is supplied with d19 to d24 of the data d19 to d31 generated by the feedback shift register 43, and the non-linear logic 46 generates 1-bit data p3 from the data d19 to d24. To do.

6-bit inputs (d _{l + 5} , d _{i + 4} , d _{i + 3} , d _{i + 2} , d _{i + i} , d _i ) at i = 0, 8, 19 (0,
0,0,0,0,0), (0,0,0,0,0,1),
(0,0,0,0,1,0), ..., (1,1,1,
1-bit output p corresponding to (1, 1, 1),
(P (0,0,0,0,0,0), (p (0,0,0,
0,0,1), ..., p (0,1,1,1,1,
1), (p (1,0,0,0,0,0), (p (1,
0,0,0,0,1), ..., p (1,1,1,1,
, 1)), the outputs of the non-linear logics 44 to 46 can be expressed as follows.

Nonlinear Logic 44 (0,0,0,0,1,1,1,0,0,1,1,1,
0,0,1,1,0,0,1,1,0,1,0,0,
1,0,0,1,0,1,1,0,1,1,1,1,
0,0,0,1,0,1,1,0,1,0,0,0,
1,0,0,0,1,0,1,1,0,0,1,1,
1,1,0,1)

Nonlinear logic 45 (0,1,1,0,0,1,1,0,1,0,0,1,
1,0,1,1,0,1,1,0,1,0,0,1,
0,0,1,1,0,1,0,0,0,0,0,1,
1,1,1,1,1,0,0,0,0,1,1,1,
1,1,1,0,0,0,1,1,0,1,0,1,
0,0,0,0)

Nonlinear logic 46 (1,0,1,0,1,1,0,1,0,1,1,0,
0,0,0,1,1,1,0,1,0,0,0,0,
1,0,1,1,1,0,1,1,0,1,0,1,
0,0,1,1,1,0,1,1,1,1,1,0,
0,1,1,0,1,0,0,1,0,0,0,0,
0,0,0,1)

When the output p2 of the non-linear logic 45 is 0, the switch 47 selects the output p1 of the non-linear logic 44 and outputs it to the adder 48. When the output p2 of the non-linear logic 45 is 1, the switch 47
Outputs the output p3 of the non-linear logic 46 to the adder 48.

The adder 48 performs an exclusive OR operation on the output p1 of the non-linear logic 44 or the output p3 of the non-linear logic 46 and the output d31 of the feedback shift register 43 to generate a 1-bit PN signal p. To do.

That is, the following calculation is performed by the switch 47 and the adder 48.

[0074]

(Equation 5)

Data p output from the PRBS generation circuit 3
Is supplied to the adder 12 via the AND gate 4 when the scramble identification flag SCF is 1 (when the packet is to be scrambled), the exclusive OR with the packet data is calculated, and encryption is performed. And output as packetized data.

When the bit detector 22C detects a bit at a predetermined timing before outputting the PN signal for the 512th bit of the actual data and outputs the second select signal, the key switching circuit 21 is detected. The selector 63 selects the key register 62 in place of the key register 61 and outputs the 32-bit key stored therein to the initial value register 1 as an initial value. After that, at a predetermined timing, the key update timing flag SCT is also set to 1, a new 32-bit initial value is loaded into the initial value register 1, and similar processing is executed.

As described above, for example, the data up to the first 511 bits of the actual data is scrambled by the first initial value, and the data after the 512th bit is
Scrambling is performed with the second initial value. The change of the initial value is variable for each packet corresponding to the data. Therefore, it becomes possible to increase the confidentiality.

In the above embodiment, the initial value correction data is generated from PID0 to PID13 and CCT0 and CCT1, but in addition to this, CCT2,
It is also possible to use CCT3.

As described above, 6 packets per packet
If you prepare a 4-bit key and use 32 bits of each for the first load and the second load, the encryption (scramble) algorithm becomes 6
Since it is often designed to handle 4-bit length data, the algorithm can be used as it is without designing a special algorithm.

In the above embodiment, the initial value is changed only once in one packet, but it may be changed twice or more. Further, although the change point of the initial value is made variable by using a part of the actual data, it is also possible to fix it at a predetermined position without using the actual data.

The actual data recorded in the data section includes video data, audio data, other data,
It can be any data.

Although the scrambler has been described in the above embodiment, a descrambler can be realized with the same configuration.

[0083]

As described above, according to the scrambler according to the first aspect and the scramble method according to the sixth aspect, the initial value is modified, and based on the modified initial value,
When a pseudo-random sequence is generated and this pseudo-random sequence is added to digital data to scramble the digital data, the initial value was changed in the middle of the packet, so the key bits that can be used for one packet The number can be increased and the confidentiality can be further improved.

Further, according to the descrambler of the seventh aspect and the descrambling method of the twelfth aspect, it is possible to surely descramble scrambled data with high confidentiality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a scramble device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a key switching circuit 21 of FIG.

3 is a block diagram showing a configuration example of an initial value modification circuit 2 in FIG.

FIG. 4 is a block diagram showing a configuration example of a PRBS generation circuit 3 in FIG.

FIG. 5 is a diagram illustrating a format of a transport packet.

FIG. 6 is a diagram illustrating changes in initial values.

FIG. 7 is a block diagram showing a configuration example of a conventional scramble device.

[Explanation of symbols]

 1 Initial Value Register 2 Initial Value Adjustment Circuit 3 PRBS Generation Circuit 5 Adjustment Control Register 21 Key Switching Circuit 22 Detection Circuit 22A ID Detection Section 22B CC Detection Section 22C Bit Detection Section 22D SCF Detection Section 31 Connection Matrix 32-1 to 32-16 Adder 41 to 43 Feedback shift register 44 to 46 Non-linear logic 47 Switch 48 Adder 61, 62 Key register 63 Selector

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04L 9/18 H04N 7/167

Claims (12)

[Claims] 1. A scrambler for scrambling digital data transmitted in packet units in packet units, wherein an initial value generating means for generating a predetermined initial value and the initial value modification data are modified based on the initial value modification data. Initial value modifying means, based on the modified initial value, pseudo-random sequence generating means for generating a pseudo-random sequence, adding means for adding the pseudo-random sequence to the digital data, the initial value A scrambler comprising: a changing unit that changes at a change point in the middle of a packet. 2. The scrambler according to claim 1, further comprising a varying unit that varies the change point of the initial value. 3. The scrambler according to claim 2, wherein the changing unit changes the change point in accordance with the actual data included in the packet. 4. The initial value is 2 of 32 bits each.
4. The key is configured by one key, and the changing unit changes one of the keys from the one key to the other key at the change point with one change point in the packet.
Alternatively, the scrambler according to item 3. 5. The detection means for detecting the packet ID or the continuation counter included in the header of the packet, in order to generate the initial value modification data, according to any one of claims 1 to 4. Scrambler. 6. A scramble method for scrambling digital data transmitted in packet units in packet units, wherein a predetermined initial value is generated, and the initial value is modified based on the initial value modification data and modified. A scrambling method comprising: generating a pseudo-random sequence based on the initial value, adding the pseudo-random sequence to the digital data, and changing the initial value in the middle of the packet. 7. A descrambling device that descrambles digital data transmitted in packet units and scrambled in packet units, based on initial value generation means for generating a predetermined initial value and initial value modification data. An initial value modifying means for modifying the initial value, a pseudo random sequence generating means for generating a pseudo random sequence based on the modified initial value, and an adding means for adding the pseudo random sequence to the digital data. And a changing means for changing the initial value at a change point in the middle of the packet. 8. The descrambling device according to claim 7, further comprising a varying unit that varies the change point of the initial value. 9. The descrambling device according to claim 8, wherein the pre-variable means varies the change point in correspondence with the actual data included in the packet. 10. The initial value is configured by two keys each having 32 bits, and the changing unit sets one of the change points in the packet as one, and at the change point, one of the keys to the other of the keys. 9. The key according to claim 7, wherein the key is changed to a key.
Alternatively, the descrambling device according to Item 9. 11. The method according to claim 7, further comprising detection means for detecting a packet ID or a continuation counter included in the header of the packet in order to generate the initial value modification data. The descrambler described. 12. A descrambling method for descrambling digital data transmitted in packet units and scrambled in packet units, wherein a predetermined initial value is generated, and the initial value is modified based on initial value modification data. And generating a pseudo random sequence based on the modified initial value, adding the pseudo random sequence to the digital data, and changing the initial value at a change point in the middle of the packet. And the descramble method.