JPH08181617A - Digital signal transmitter - Google Patents

Abstract

PURPOSE: To obtain high sound quality by decreasing quantization noise through different bit shift for each block. CONSTITUTION: A bit shift circuit 7 shifts bits of digital data based on a bit shift level S4 from a maximum value detection circuit 6 and a dither circuit 8 reduce low-order 8-bits of 24-bits, for example to obtain 16-bit dither data S6. The dither data S6 are distributed to M sets of frequency areas by a division filter 9 comprising sub band coding circuits and fed to a bit allocation 10. A quantization level (ALLOC) is allocated to the bit allocation 10 so that the entire block has a prescribed data amount and the data are quantized by a quantization device 11. In a bit stream format processing circuit, quantized data, normalization coefficient (SF), quantization level (ALLOC) and bit shift value S4 are coded and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission device using, for example, digital audio data, which uses a data dithering process when the data is divided into blocks and handled.

[0002]

2. Description of the Related Art The number of input data bits is N bits,
The number of recorded data bits is R, and the number of data bits output from the D / A converter is M. When the bit number N of input data is larger than the bit number R of recording data, it is necessary to reduce N bits to R bits. At this time, as one method for reducing the number of bits, data rounding (dithering) has been conventionally well used (for example, see Japanese Patent Laid-Open No. 62-183627).

This dither processing will be briefly described with reference to FIG. First, assuming that 10 pieces of data are one block and N = 24 bits, R = 16 bits, and M = 24 bits, the lower 8 bits of the input data shown in FIG. It becomes data. When this recording data (FIG. 13B) is read out and output from the D / A converter, `0 'is added to the lower 8 bits as shown in FIG. 13C and is output as 24-bit data. As described above, in the digital signal transmission device for recording 24-bit input data in 16 bits, the random sequence is added to the LSB side of the input data, and then the dither processing for rounding to 16 bits is performed.

Here, in an actual digital transmission medium, digital data is transmitted with error correction information added. Therefore, in order to perform error correction, it is necessary to make the data into blocks of a certain length. Further, when the transmission (recording) medium is of the helical scan type, there is at least a block called a helical track. In the case of a disk medium, since there is a minimum read unit called a sector, it is desirable to block at least that data. As described above, it is quite common to handle the transmission data as a block, and in addition to this block, information for synchronization and additional information indicating the content are added. One block is configured.

FIG. 14 shows an example of conventional dither processing. Input data S21 of 24 bits is supplied from the input terminal indicated by 41 to the dither circuit 42, and the dither circuit 42 converts the 24-bit input data S21 into 16-bit data S24. The random sequence is added to the lower 8 bits of the input data S21 supplied to the dither circuit 42, and the upper 16 bits of the random sequence are added to the data S.
24 is supplied to the ECC encoding circuit 43. For example, an M sequence is used as the random sequence. ECC
The encoding circuit 43 performs encoding such as predetermined error correction, and records the redundant code of the error correction code together with the data on the recording medium 44. The data reproduced from the recording medium 44 is supplied to the ECC decoding circuit 45, is subjected to decoding such as predetermined error correction, and the data is taken out from the output terminal 46 as 16-bit data.

FIG. 15 shows an example of data transition when the dither process is performed. S21 represents input data, which is data of 24 bits [0000 0000
0001 0110 0111 0000].
S22 is an 8-bit random sequence [0100
0111], and the dither circuit 42 adds the lower 8 bits of the input data S21. The addition result is [00000000 0001 0110].
1011 0111] is shown in S23. And
By truncating the lower 8 bits as shown in the data S24, the data is recorded in the recording medium 44 as 16-bit data. The recorded 16-bit data is reproduced, and as shown in S25, 8 bits of `0 '
Data added to the lower side [0000 0000 00
01 0110 0000 0000] is taken out.

FIG. 16 shows a case of sub-band coding as an example of a method of frequency-decomposing and coding audio data. FIG. 16 shows an example of the configuration of a subband coding method for M division. First, on the encoding side, audio data is supplied from an input terminal indicated by 51, and the supplied audio data is divided by a division filter 52.
Supplied to The division filter 52 is composed of a bandpass filter 53 and a down subsampling 54, and the supplied audio data is divided by the bandpass filter 53 into M frequency regions. At this time, the quantization level (ALLOC) is assigned according to the data amount of each subband so that the total data amount is constant.

The M-divided data is supplied to the down subsampling 54, and the down subsampling 5
In 4, for example, 24-bit data is converted into 16-bit data. The data converted into 16 bits is supplied from the division filter 52 to the quantizer 55, and the quantizer 5
In 5, the data of each subband is normalized with a value corresponding to the maximum value of each subband and then quantized with this assigned quantization level. The quantized data is rearranged in the bit stream format in the packing circuit 56. The normalization coefficient (SF) and the quantization level (ALLOC) of each subband are also recorded on this bitstream.

On the decoding side, the packing decomposition circuit 57 rearranges the data stream of each subband from the state of the bitstream, and according to the recorded quantization level and normalization coefficient, the original subband is reconstructed. The data is rearranged into a data string and converted into the original subband data according to the recorded quantization level and the normalization coefficient. The data is requantized in the dequantizer 58 and supplied to the synthesis filter 59. The synthesizing filter 59 includes an up subsampling 60 and a bandpass filter 61.
The bit data is converted into 24-bit data. In the bandpass filter 61, the original audio data is decoded and taken out from the output terminal 62.

FIG. 1 shows an example of a configuration in which the above-mentioned conventional dither processing, subband coding, and decoding are combined.
7 shows. This configuration is controlled by a signal supplied through a system computer interface indicated by 71 and a timing generation circuit 72. At the time of encoding, audio data is supplied to the dither circuit 74 via the input terminal 73, and the dither circuit 74 converts the supplied audio data from, for example, 24 bits to 16 bits. That is, the number of bits of the supplied audio data is reduced in this dither circuit 74, and the audio data is supplied to the division filter 75.

The division filter 75 divides the supplied data into M subbands and supplies the divided data to the bit allocation 76. In the bit allocation 76, the quantization level (ALLOC) is assigned according to the data amount of each subband so that the total data amount is constant. The data of each subband is quantized by the quantizer 77 at this assigned quantization level, and is supplied to the bitstream formatting circuit 78.
In the bitstream formatting circuit 78, the quantized data of each subband is rearranged into a bitstream format. The normalization coefficient (SF) and the quantization level (ALLOC) of each subband are also recorded on this bit stream, and are supplied to an ECC encoding circuit (not shown) via the output terminal 79.

At the time of decoding, E (not shown) is used as described above.
Bitstream data is supplied from the CC decoding circuit to the bitstream format division circuit 82 via the input terminal 81. In the bit stream format division circuit 82, the supplied bit stream data is rearranged into sub band data and supplied to the bit allocation decoder 83. The bit allocation decoder 83 converts the recorded quantization level into data of each subband and supplies the data to the inverse quantizer 84. In the inverse quantizer 84, the inversely quantized data is taken out from the output terminal 86 as audio data via the synthesis filter 85.

An example of implementing the above-mentioned dither circuit 74 by software processing is shown in the flowchart of FIG. When this flow chart is started, the control starts from the data input in step 91. In step 91 (data input), random series is added to the input data in the random series addition in step 92.
As a random sequence, M sequence (polynomial x ¹⁹ + x ⁵ + x
² + x + 1) is used. In this step 92 (random sequence addition), the lower 8 bits of the random sequence,
The input data composed of 24 bits and the value of the 23rd bit of the input data are added, and the calculated data of 25 bits is output.

In the overflow detection of step 93,
Whether or not the data calculated in step 92 (random sequence addition) has overflowed is detected. If no overflow is detected, the control proceeds to step 94. If an overflow is detected, the control proceeds to step 95. In the data output of step 94, the 8th to 23rd bits of the 24-bit data calculated in step 92 (random sequence addition), that is, the data that has been subjected to the dither (rounding) processing, are output. In the overflow operation of step 95, the value of the 23rd bit of the 24-bit data calculated in step 92 (random sequence addition) is arranged for 16 bits and output as dithered data.

[0015]

However, in the conventional processing, since the lower 8 bits of information of the original input data is always lost, the quantization noise generated when the dither processing is performed is It is generated in the audible area as wave noise. When the input signal has a large amplitude, it cannot be heard due to the masking effect, but when the input signal has a small amplitude, the masking effect is weakened, and this quantization noise is perceived.

Further, it is difficult to secure the accuracy of the number of bits of the input signal with respect to the input signal of 24 bits due to the problem of the internal calculation accuracy of the filter and the like, and conversely, the accuracy up to the input bit length is required. In order to secure it, it is necessary to improve the precision of the internal calculation, which causes a problem that the amount of hardware becomes very large.

Therefore, an object of the present invention is to detect the maximum value in a block at the time of encoding in view of these points, and uniformly perform bit shift (increase gain) on all data in the block according to the detected value. , The bit shift information is also transmitted along with the block, and at the time of decoding, all data is uniformly bit-shifted (the gain is lowered) by the amount corresponding to the bit shift information transmitted together with the block. Without increasing the number of bits of
An object of the present invention is to provide a digital signal transmission device capable of enhancing the accuracy of small amplitude and enhancing the sound quality.

[0018]

SUMMARY OF THE INVENTION The present invention is directed to a block dividing means for dividing input digital data into blocks, a maximum value detecting means for detecting a maximum value for each block, and a detected maximum value. Bit shift means for performing a rounding process on the digital data based on the above, and transmitting the shift process performed by the bit shifting means as bit shift information together with the digital data subjected to the shift process and the rounding process. It is a digital signal transmission device comprising:

[0019]

As an example, 10 pieces of data are set as one block, and dither processing is performed for each block. In this case, the shift processing is adaptively switched according to the signal level of each block. This makes it possible to suppress noise when the rounding process is performed. Furthermore, when encoding and decoding the block on which the dither processing has been performed, high sound quality can be obtained by using the block of interest and the block adjacent to the block of interest.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital signal transmission device according to the present invention will be described below with reference to the drawings.
First, in the case of a code with 2's complement, if the amplitude of the audio data is small in the upper bits of the digital sampling data after A / D conversion, the
0's are continuous, and in negative data, '1' are continuous. In this state, it can be said that the redundancy of information is large,
The range in which 1'is continuous is called headroom. Therefore, when handling data in units of a certain block, bit shift (increase gain) is performed according to the maximum value (minimum headroom) data in the block, and the bit shift information is transmitted for each block. This allows more detailed information to be sent with the same recording capacity.

The dither processing of this embodiment will be described. FIG. 1 shows an example in which the shift amount during recording is 0 (that is, when the shift is not performed). First, to handle 10 data as one block,
In FIG. 1A, ten pieces of input data numbered 0 to 9 are shown. From the headroom of FIG. 1A, it can be said that this block has a large amplitude. Therefore, the shift amount of this block is set to zero. That is, when converting from 24 bits to 16 bits, 10 pieces of data in which 8 bits are reduced from the LSB side as shown in FIG. 1B,
A bit shift value (3-bit code) `000` indicating that the shift amount is 0 is recorded (transmitted). When this recorded data is reproduced (received), 8-bit `0` is added to the LSB side as shown in FIG. 1C.

Similarly, FIG. 2, which is an example of this embodiment, shows an example in which the shift amount during recording is 4. In FIG. 2A, 1
Zero input data are shown. Since the input data (FIG. 2A) has a small amplitude (large headroom), the shift amount of this block is 4. That is,
When converting from 24 bits to 16 bits, after the bit shift of 4 bits to the MSB side as shown in FIG. 2B, the lower 8 bits are reduced, and 10 pieces of data having 16 bits and the shift amount are 4 Bit shift value indicating that
"100" is recorded. When reproducing the recorded data, as shown in FIG. 2C, the MSB bit, that is, the value of the 0th bit, is added to the MSB side by 4 bits,
By adding "0" to the lower 4 bits, it is output as reproduced data consisting of 24 bits.

The bit shift value recorded together with the 10 pieces of dither-processed 16-bit data is represented by `000` when the shift amount is 0, and the gain becomes 1 time. When the shift amount is 1, the bit shift value is represented by `001` and the gain is doubled. When the shift amount is 2, the bit shift value is represented by` 010` and the gain is 4 times. Furthermore, when the shift amount is 3, the bit shift value is `0.
11 ', the gain becomes 8 times, when the shift amount is 4, the bit shift value is shown as'100' and the gain is 1
It will be 6 times. Since this bit shift value is transmitted for each block, the data amount increases by the bit shift value.
However, when 16-bit data is divided into blocks every 160 samples, the increment is 3 / (160 × 16) = 0.1 because the bit shift value is composed of 3 bits.
It is a very small amount of 17%. Similarly, the shift amounts may be 5, 6, and 7 below. Further, if the bit shift value is represented by 4 bits, the shift amount can be set to 8.

Next, FIG. 3 shows a block diagram of an embodiment of a digital signal transmission apparatus to which the present invention is applied. This digital signal transmission apparatus is controlled by a signal supplied through a system computer interface shown by 1 and a timing generation circuit 2. Input data S1 is supplied to the block delay circuit 5 and the maximum value detection circuit 6 via the input terminal 3. In the block delay circuit 5, the block is delayed for the time when the maximum value detection circuit 6 detects the maximum value of the block. In the maximum value detection circuit 6, the block clock S2 supplied from the input terminal 4
Based on the above, the maximum value detected for each block is supplied to the bit shift circuit 7 and the bit stream formatting circuit 12 as a bit shift value S4.

In the bit shift circuit 7, the delay data S5 supplied from the block delay circuit 5 is shifted according to the bit shift value S4. The shifted shift data S11 is supplied to the dither circuit 8. The dither circuit 8 performs addition and rounding of the M series on the shift data S11, and supplies the dither data S6 to the division filter 9. The division filter 9 divides the supplied dither data S6 into M frequency regions,
In the bit allocation 10, the divided dither data S6 is assigned a quantization level (ALLOC) so that the entire block has a constant data amount.
Based on the assigned quantization level, the quantizer 11
Then, the data is quantized. In the bit stream formatting circuit 12, the quantized data, the normalization coefficient (SF), and the quantization level (ALLOC)
Then, the bit shift value S4 is formatted in the form of a bit stream and supplied as encoded data S7 to an ECC encoding circuit (not shown) or the like via the output terminal 13.

Decoded data S8 is supplied to a bit stream format division circuit 22 from an ECC decoding circuit (not shown) via an input terminal 21. The bit stream format division circuit 22 separates the data S8 and the bit shift value S9 from the supplied decoded data S8, and the bit shift value S9 is supplied to the bit shift circuit 26.
The data is supplied to the bit allocation decoder 23. The bit allocation decoder 23 detects the quantization level of the supplied data, and the dequantizer 24 dequantizes the supplied data. In the synthesis filter 25, the dequantized data is synthesized on the frequency, and in the bit shift circuit 26, the synthesized data is based on the bit shift value S9 supplied from the bit stream format division circuit 22. The output terminal 2 is shifted and output as output data S10.
Taken from 7.

Here, an example of a timing chart of the digital signal transmission apparatus of the present invention is shown in FIG. S1 is
The input data input from the input terminal 3 is shown, and it can be seen that the data is supplied for each block. The block clock S2 indicates the falling clock supplied from the input terminal 4. This clock falls for each block. The maximum value detection circuit 6 detects the maximum value S3, and the maximum value detection circuit 6 outputs the bit shift value S4 based on the detected maximum value S3. As will be described later, in this embodiment, the maximum value S3 detects the number of bits (headroom) in which "0" or "1" continues from the next upper bit of the MSB.

Further, the maximum value detection circuit 6 delays the block delay circuit 5 for the time required to detect the maximum value, and the delay signal S5 is generated. Dither processing is performed on the supplied delay data S5, and dither data S6 is output to the subband encoding circuit. The reproduced data as shown in S8 is supplied for each block from the sub-band signal decoding circuit, and the bit shift value S9 separated from the bit stream format division circuit 22 is supplied. The reproduced data is output as output data S10.

An example of signal processing performed in this embodiment is shown in FIG. At the time of encoding, the maximum value (headroom) of the input data S1 is detected, and the shift is performed based on the shift amount determined by the detected maximum value. here,
The shift amount is 0. The random sequence S12 for performing the dither process is added to the lower 8 bits of the shift data S11 that has been subjected to the shift process, and the lower 8 bits of the added shift data S11 is reduced to generate the dither data S6. It The 15th bit Z of the dither data S6 is determined by carrying it up by the dither processing. When decoding, the reproduced signal S13
The output data S10 is output by adding "0" to the lower 8 bits.

FIG. 6 shows an example of the signal processing performed in this embodiment. At the time of encoding, the maximum value (headroom) of the input data S1 is detected, and the shift is performed based on the shift amount determined by the detected maximum value. here,
The shift amount is 2. The random sequence S12 for performing the dither process is added to the lower 8 bits of the shift data S11 that has been subjected to the shift process, and the lower 8 bits of the added shift data S11 is reduced to generate the dither data S6. It The 15th bit Z of the dither data S6 is determined by carrying it up by the dither processing. When decoding, the reproduced signal S13
2 bits are bit-shifted to the lower side, 6 bits of `0 'are added to the lower side, and the value of the 0th bit, that is,` 0', is added to the upper side of 2 bits. It is output as output data S10.

FIG. 7 shows an example of the signal processing performed in this embodiment. At the time of encoding, the maximum value (headroom) of the input data S1 is detected, and the shift is performed based on the shift amount determined by the detected maximum value. here,
The shift amount is 2. The random sequence S12 for performing the dither process is added to the lower 8 bits of the shift data S11 that has been subjected to the shift process, and the lower 8 bits of the added shift data S11 is reduced to generate the dither data S6. It At this time, since the shift data S11 is shifted to the upper 4 bits, the values of the lower 8 bits are all "0", and the value of the 15th bit does not change even if any random sequence S12 is added. The dither data S6 in FIG. 8 is not Z. At the time of decoding, the reproduced signal S13 is bit-shifted by 4 bits in the lower order, and further 4 bits in the lower order.
Bits of "0" are added, and the value of the 0th bit, that is, "0", of 4 bits is added to the higher order and output as output data S10.

Next, an example of how to obtain the maximum value in the maximum value detection circuit 6 will be described with reference to FIG. FIG. 8A shows M
Since SB (the value of the 0th bit) is "0", the data is positive. In the case of positive data, a range (referred to as headroom) where `0 'continues from the second most significant bit is obtained. In the example of FIG. 8, this headroom is 10 bits. In FIG. 8B, since the MSB (the value of the 0th bit) is `1`, the data is negative and the headroom is calculated as 3 bits. Further, when the data is negative, all bits are inverted and represented as shown in FIG. 8C. Also in FIG. 8C, the headroom is composed of 3 bits, which is the same as in FIG. 8B. Then, when the headroom of all the data in the block is obtained, the minimum headroom is detected from all the data. The data with the smallest detected headroom becomes the maximum for that block. This headroom corresponds to the bit shift value. That is, when the minimum value of the headroom of the block is detected as 3, the shift amount is also 3
This is because

FIG. 9 shows a configuration example of a bit stream in the case where the number of divisions is 32 and the code length is 320 samples in one embodiment of the present invention using subband coding. In this example, an audio signal accompanying a 625/50 system television signal is subband-encoded. Figure 9A
, F0, F1, F2, ... Are audio data generated in each frame of the video frame. Figure 9
As shown in B, one frame has 6 samples every 320 samples.
Will be divided. In this 320 samples, 32 sub-band data are 10 samples and constitute 1920 samples.

Further, as shown in FIG. 9C, each block has information (ALLO) indicating a quantization level at the time of encoding.
C) and information (SF) indicating the maximum value of data in each subband block are recorded at the same time. Further, ancillary (ANC) data is also recorded as additional information of the block. This ALLOC consists of 4 bits, and SF consists of 6 bits. The ANC data shown in FIG. 9E is composed of 8 bits, gain information is recorded in 3 bits of the 8 bits, and the remaining 5 bits are for storage. At the time of reproduction, data is reproduced by bit-shifting based on this gain information.

FIG. 10 shows an example of the relationship between the amplitude of audio data and the shift amount according to the present invention. Figure 10A
Indicates the amplitude of the input audio data. Figure 10
In B, the amplitude of each block is represented by diagonal lines. Figure 10C
Shows the relationship between the detected maximum value and a preset threshold value. Block numbers B0, B1, B2,
B9, B10, and B12 have a large amplitude and do not exceed the double threshold value, and thus the shift amount is set to 0. Since the block numbers B3, B4, B8, and B11 exceed the threshold value of 4 times, the shift amount is set to 2. Furthermore, block number B
Since 5, B6, and B7 exceed 16 times the amplitude, the shift amount is set to 4. FIG. 10D shows the bit shift value and its gain for each block.

Here, FIG. 1 shows an example of processing of a division filter used for sub-band coding which is frequency-decomposed and coded.
It is shown in FIG. In order to process one block, this division filter uses the data of the preceding and following blocks as shown in FIG. 11A. In this example, the filtering process is performed by the configuration shown in FIG. 11B. Data is input through the input terminal 1 and is supplied to the sample delay element, the D flip-flop 32, and the multiplier 33 ₀ that multiplies the predetermined filter coefficient h ₀ . Data supplied to the D flip-flop 32 _0, D from D flip-flop 32 ₀ at each clock
It is transmitted to the flip-flop 32 ₅₁₀ . 512 extracted from the D flip-flops 32 _{0 to} 32 ₅₁₀
Against tap is multiplied 32 _{0-32 511} filter coefficients h ₀ to h ₅₁₁ respectively connected, these multipliers outputs are all added in adder 34, it is taken out from an output terminal 35.

As described above, in the coding affected by the adjacent blocks, it is necessary to determine the gain while considering the maximum value of the related blocks at the time of coding. At the time of sub-band coding, bit shift is performed to make the shift amount of all coded blocks constant. That is, in this example, the smallest shift amount is detected from the three blocks of the target block and the adjacent block, and the shift amount different from the detected shift amount is the shift amount of the three blocks. Blocks with quantities do bit shifting. At the time of decoding, in order to match the shift amount of the block of interest, processing is performed so that the shift amounts of the preceding and following blocks are relatively the same, and decoding is performed. The decoded block of interest is bit-shifted bit by bit on the LSB side in accordance with the shift amount and output.

FIG. 12 shows the encoding and decoding processing when the data subjected to the bit shift processing shown in FIG. 10 is supplied to the subband encoding circuit (division filter) for each block. First, as shown in FIG. 12A, the block B2 is input to the encoding circuit, and the block B1 noticed at this time is encoded. This attention block B
Since 1 does not exceed the double threshold value as described above, the shift amount is 0, and the shift amounts of the adjacent blocks B0 and B2 used at the time of encoding are also 0, and thus are encoded. The shift amount of the block b1 is also set to 0.

The block noticed when the coded block b1 is input to the decoding circuit (synthesis filter) is b0. At this time, since the shift amounts of the adjacent blocks b-1 and b1 are 0, which is the same as the shift amount of the target block b0, decoding is performed in that state, and the block B0 is decoded. The decoded block B0 is supplied to the bit shift circuit. The gain at that time is 1, and output data can be obtained without performing bit shift.

Next, as shown in FIG. 12B, when the block B3 having a shift amount of 2 is input to the subband coding circuit (division filter), the block of interest B2 is coded. At the time of this encoding, since the shift amounts of the blocks B1 and B2 are 0, the shift amount of the block B3 is converted from 2 to 0. That is, the data of the block B3 is bit-shifted so that the shift amount is 0 (gain is 1). After the bit shift is performed, encoding is performed. Therefore, the shift amount of the encoded block b2 is
It becomes 0. The block noticed when this encoded block b2 is input to the decoding circuit (synthesis filter) is b1. At this time, since the shift amounts of the blocks b0 and b2 are 0, which is the same as the shift amount of the target block b1, the decoding is performed in that state, and the block B1 is decoded. The decoded block B1 is supplied to the bit shift circuit. The gain at that time is 1, and output data can be obtained without performing bit shift.

Further, as shown in FIG. 12C, when the block B4 having the shift amount of 2 is input to the subband coding circuit (division filter), the target block B3 is coded. At the time of this encoding, since the shift amount of the block B2 is 0, the shift amounts of the blocks B3 and B4 are 2 to 0.
Is converted to. That is, the data of the blocks B3 and B4 are bit-shifted so that the shift amount becomes 0 (gain is 1). After the bit shift is performed, encoding is performed. Therefore, the shift amount of the encoded block b3 becomes 0. The block noticed when the coded block b3 is input to the decoding circuit (synthesis filter) is b2. At this time, since the shift amounts of the blocks b1 and b3 are 0, which is the same as the shift amount of the target block b2, decoding is performed in that state, and the block B2 is decoded. The decoded block B2 is supplied to the bit shift circuit. The gain at that time is 1, and output data can be obtained without performing bit shift.

Then, as shown in FIG. 12D, when the block B5 having the shift amount of 4 is input to the subband coding circuit (division filter), the target block B4 is coded. At the time of this encoding, since the shift amounts of blocks B3 and B4 are 2, the shift amount of block B5 is 4 to 2
Is converted to. That is, the data of the block B5 is bit-shifted so that the shift amount is 2 (gain is 4). After the bit shift is performed, encoding is performed. Therefore, the shift amount of the encoded block b4 is 2.

The block noticed when the coded block b4 is input to the decoding circuit (synthesis filter) is b3. At this time, the shift amount of the block b2 is
The shift amount of the block b4 is 0, which is the same as the shift amount of the block b3 of interest, and the shift amount of the block b4 is different from the shift amount of the block b3 of interest.
Converted to 0, which is the same as the shift amount of 3. That is, as in the case of encoding, the data of the block b4 is bit-shifted so that the shift amount is 0 (gain is 1) and then decoded. The amount of shift of the decoded block B3 is 0. The decoded block B2 is supplied to the bit shift circuit. The gain at that time is 1, and output data can be obtained without performing bit shift.

Next, as shown in FIG. 12E, when the block B6 having a shift amount of 4 is input to the subband coding circuit (division filter), the block of interest B5 is coded. At the time of this encoding, since the shift amount of the block B4 is 2, the shift amount of the blocks B5 and B6 is converted from 4 to 2. That is, the data of the blocks B5 and B6 are bit-shifted so that the shift amount is 2 (gain is 4). After the bit shift is performed, encoding is performed. Therefore, the shift amount of the encoded block b5 is 2.

The block noticed when the coded block b5 is input to the decoding circuit (synthesis filter) is b4. At this time, the shift amount of the block b5 is
The shift amount of the target block b4 is 0, which is the same as the shift amount of the target block b4, and the shift amount of the block b3 is different from the shift amount of the target block b4. Therefore, the shift amount of this block b3 is converted from 0 to 2. That is, as in the case of encoding, the data of the block b3 is bit-shifted so that the shift amount is 2 (gain is 4) and then decoded. The decoded block B4 having the shift amount of 2 is bit-shifted by 2 bits to the LSB side by the bit shift circuit, that is, the gain is 1
It is output after being set to / 4.

Then, as shown in FIG. 12F, block B
7 is input to the sub-band encoding circuit (division filter), and the block B6 noticed at this time is encoded.
The target block B6 has a shift amount of 4, and the adjacent blocks B5 and B7 used at the time of encoding also have a shift amount of 4. Therefore, the encoded block b6 also has a shift amount of 4. The block noted when this encoded block b6 is input to the decoding circuit (synthesis filter) is b5. The block to be noticed when this encoded block b6 is input to the decoding circuit is b5. At this time, the shift amount of the block b4 is 2 which is the same as the shift amount of the target block b5, and the shift amount of the block b6 is different from the shift amount of the target block b5. Therefore, the shift amount of this block b6 is converted from 4 to 2. To do. That is, as in the case of encoding, the data of the block b6 is bit-shifted so that the shift amount is 2 (gain is 4) and then decoded. The decoded block B5 having a shift amount of 2 is subjected to 2-bit bit shift to the LSB side by the bit shift circuit, that is, the gain is set to 1/4, and then output.

Further, as shown in FIG. 12G, when the block B8 having the shift amount of 2 is input to the subband coding circuit (division filter), the target block B7 is coded. At the time of this encoding, since the shift amount of the block B8 is 2, the shift amount of the blocks B6 and B7 is 4 to 2
Is converted to. That is, the data of the blocks B6 and B7 are bit-shifted so that the shift amount is 2 (gain is 4). After the bit shift is performed, encoding is performed. Therefore, the shift amount of the encoded block b7 is 2.

The block noticed when the coded block b7 is input to the decoding circuit (synthesis filter) is b6. At this time, since the shift amounts of the blocks b5 and b7 are different from the shift amount of the target block b6, the shift amounts of the blocks b5 and b7 are converted from 2 to 4.
That is, as in the case of encoding, the data of the blocks b5 and b7 are bit-shifted so that the shift amount is 4 (gain is 16) and then decoded. The block B6 having the decoded shift amount of 4 is LSB in the bit shift circuit.
4 bits are bit-shifted to the side, that is, the gain is set to 1/16 and then output.

Then, as shown in FIG. 12H, when the block B9 having a shift amount of 0 is input to the subband coding circuit (division filter), the target block B8 is coded. At the time of this encoding, since the shift amount of the block B9 is 0, the shift amount of the block B7 is converted from 4 to 0, and the shift amount of the block B8 is converted from 2 to 0. That is, the data of the blocks B7 and B8 are bit-shifted so that the shift amount is 0 (gain is 1). After the bit shift is performed, encoding is performed. Therefore, the shift amount of the encoded block b8 is
It becomes 0.

The block noticed when the coded block b8 is input to the decoding circuit (synthesis filter) is b7. At this time, the blocks b6 and b8 are converted into the same shift amount as the target block b7 whose shift amount is 2. That is, the bit shift is performed so that the shift amount of the block b6 is 4 to 2 (gain is 16 to 4), and the shift amount of the block b8 is 0 to 2 (gain is 1 to 4). Is done. After these bit shifts are performed, decoding is performed, and the target block B7 having a shift amount of 2 is bit-shifted by 2 bits to the LSB side by the bit shift circuit, that is, a gain of 1 is obtained.
It is output after being set to / 4.

Although only the digital audio data has been described in this embodiment, the digital audio data may be used in addition to the digital audio data.

[0052]

According to the present invention, the maximum value (headroom) is detected for each block, and the dither processing according to the block is performed, so that the dither processing according to the magnitude of the amplitude of the data is performed. You can

Further, according to the present invention, by reducing the number of bits to be processed, it is possible to use the internal calculation accuracy without any change. In other words, it can be used without increasing the hardware.

[Brief description of drawings]

FIG. 1 is used to explain a dither process of an embodiment according to the present invention.

FIG. 2 is used to explain a dither process of an embodiment according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a digital signal transmission device of the present invention.

FIG. 4 is a timing chart of an example of a digital signal transmission device of the present invention.

FIG. 5 is a schematic diagram used to describe a dither process according to an embodiment of the present invention.

FIG. 6 is a schematic diagram used to describe a dither process according to an embodiment of the present invention.

FIG. 7 is a schematic diagram used to describe a dither process according to an embodiment of the present invention.

FIG. 8 is a schematic diagram used to describe an example headroom according to the present invention.

FIG. 9 is a schematic diagram showing an example of a bit stream according to the present invention.

FIG. 10 is a schematic diagram showing an example of the relationship between the amplitude of audio data and the shift amount according to the present invention.

FIG. 11 is a schematic diagram showing one embodiment of subband coding according to the present invention.

FIG. 12 is a schematic diagram showing an example for explaining encoding and decoding for each block according to the present invention.

FIG. 13 is used for explaining a conventional example of dither processing.

FIG. 14 is a block diagram showing an example of conventional dither processing.

FIG. 15 is a schematic diagram used to describe conventional dither processing.

FIG. 16 is a block diagram showing an example of conventional subband decoding.

FIG. 17 is a block diagram showing an example of a conventional digital signal transmission device.

FIG. 18 is a flowchart showing an example of conventional dither processing.

[Explanation of symbols]

 1 system computer interface 2 timing generation circuit 5 block delay circuit 6 maximum value detection circuit 7 bit shift circuit 8 dither circuit 9 division filter 10 bit allocation 11 quantizer 12 bit stream formatting circuit 22 bit stream format division circuit 23 bit allocation decoder 24 inverse quantizer 25 synthesis filter 26 bit shift circuit

Claims (6)

[Claims] 1. A block dividing means for dividing input digital data into blocks, a maximum value detecting means for detecting a maximum value for each block, and the digital data based on the detected maximum value. A bit shift means for performing a shift process and a round process on the same, and a means for transmitting the shift process performed by the bit shift means as bit shift information together with the digital data subjected to the shift process and the round process. A digital signal transmission device comprising: 2. The digital signal transmission device according to claim 1, further comprising means for randomizing a plurality of lower bits of the digital data that has been subjected to the shift processing and the rounding processing. Digital signal transmission equipment. 3. In a digital signal transmission device, when the value of input digital data is large, a shift process is performed in a direction toward the MSB side of the digital data, and the bit on the LSB side of the digital data subjected to the shift process. A digital signal transmission device, characterized in that 4. A block dividing means for dividing input digital data into blocks, a maximum value detecting means for detecting a maximum value for each block, and the digital data based on the detected maximum value. Bit shift means for performing shift processing and rounding processing, compression encoding means to which the shifted or rounded digital data is supplied, output data of the compression encoding means, and A digital signal transmission device, which transmits bit shift information instructing a shift process. 5. A compression code decoding means for decoding the received digital data, a bit shift information separating means for separating bit shift information from the received digital data, and based on the separated bit shift information. And a bit shift means for adding a predetermined bit to the MSB side and / or the LSB side of the output data of the encoding means. 6. The digital signal receiving apparatus according to claim 5, wherein when the value of the received digital data is small, the bit shift information recorded together with the digital data is separated, and the bit shift information is recorded according to the bit shift information. The shift processing is performed on the digital data, and a value of "0" is added to the LSB side of the digital data to obtain the MSB.
A digital signal transmission device characterized in that the MSB value of the digital data is added to the side.