JPH08179270A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE: To remarkably reduce the incidence of a failure in markets by essentially dissolving the failure of the operations of a driver, etc., at the time of applying a main power source and making the reliability of a liquid crystal display device to be of very high as a result. CONSTITUTION: A switching circuit 3 is provided in between a polarity inversion circuit 2 generating a polarity inversion signal POL and a gradation voltage generation circuit 1 generating a gradation voltage V0 based on the level change of the polarity inversion signal POL and is controlled by a control circuit 4 so that the supplying of the polarity inversion signal POL to the gradation voltage generating circuit 1 is interrupted while a specified period has elapsed from a time when the power source was applied and thereafter the interruption is released.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a liquid crystal display device, and more particularly to a drive circuit for AC driving the liquid crystal display device.

[0002]

2. Description of the Related Art In a conventional liquid crystal display device, there is a possibility that the driver may make various unexpected malfunctions immediately after the drive circuit is powered on because the power supply voltage is not stable.
For this reason, in the conventional drive circuit of the liquid crystal display device, for example, + 5V of the power supply voltage for logic and -24V of the power supply voltage for drive are used.
When turning on the power source of the control circuit, as shown in FIG. 9, the logic power source is first turned on, and the driving power source is turned on after the time TON has passed after the logic power source voltage is fixed. Thus, the logic circuit can operate normally when the driving power source is turned on. When the power supply is cut off, the drive power supply is cut off first, and when the time TOFF elapses after the drive power supply voltage is attenuated, the logic power supply is cut off.

In some cases, the inconvenience may not be completely eliminated only by controlling the power-on timings of the logic power supply voltage and the driving power supply voltage as described above. For example, in a simple matrix type liquid crystal display device, as shown in FIG. 10, a reference voltage generation circuit is used to supply reference voltages V10 to V15 of a plurality of voltage levels used in the voltage averaging drive method to the drive circuit. There is.

This reference voltage generating circuit divides the voltage difference between the + 5V logic power supply voltage and the -24V driving power supply voltage by resistors R11 to R15 connected in series to generate 6
This is to obtain various kinds of reference voltages V10 to V15. And
The reference voltages V11 to V14 divided by the resistors R11 to R15 are supplied to the driver through a buffer circuit configured to obtain high input impedance and low output impedance by connecting the operational amplifiers 31 to 34 in a negative feedback manner. There is. However, the operational amplifier 31, which outputs the reference voltages V11 and V14,
Regarding No. 34, resistors R16 and R17 are interposed in the feedback paths, respectively, and a correction voltage for correcting the waveform distortion is inputted to the inverting input via capacitors C17 and C18 and resistors R18 and R19, respectively. It is configured as a differential amplifier.

A series circuit of resistors R11 to R15 for dividing voltage has one end connected to a + 5V logic power supply voltage line via a diode D1 and the other end used as a base input for a brightness adjustment voltage. Through transistor T-2
By connecting to the drive power supply line of 4V,
The brightness of the liquid crystal display can be adjusted. Further, capacitors C11 to C16 are connected between the + 5V logic power supply voltage line and the output lines of the reference voltages V10 to V15, respectively, so that voltage fluctuations generated in the driver can be absorbed.

In the case of this reference voltage generating circuit, when the driving power supply of -24V is turned on, the capacities of the capacitors C11 to C16 are different, so that the rise times of the reference voltages V10 to V15 are different. Then, the reference voltage V15 becomes higher than the reference voltage V13 and the reference voltage V14, and the relationship between the voltage levels is temporarily inverted, so that the driver CM
There is an inconvenience that the OS transistor may cause latch-up.

Therefore, as shown in FIG. 10, the diodes D2 and D3 are connected in reverse directions between the output line of the reference voltage V15 and the output lines of the reference voltages V13 and V14, respectively, whereby the voltage levels are reversed. In such a case, there has been conventionally proposed a method of short-circuiting these output lines to prevent latch-up of the CMOS transistor of the driver (Japanese Patent Laid-Open No. 5-150748).

[0008]

However, in the conventional drive circuit of the liquid crystal display device, as shown in FIG. 10, in the reference voltage generation circuit, the output line of the reference voltage of the reference voltages V11 to V15 having the closer potential level is used. In between, diode D
2 and D3 are inserted, and this is merely to eliminate the inconvenience caused by the reversal of the relationship of the voltage level when the power is turned on.

That is, even in the reference power supply generation circuit using the diode as described above, when the power is turned on, the supply of current to the pixel capacitances of the liquid crystal panel is simultaneously started, and this pixel capacitance is Since it is a capacitive load, a large inrush current transiently reaches several tens mA to several hundreds mA. That is, in a circuit having a large number of picture element capacities as its load such as the reference voltage generating circuit, the sum of the currents supplied to the individual picture element capacities flows.

Under these circumstances, when AC driving is performed on the load (liquid crystal panel) that further increases the potential fluctuation in the reference voltage generating circuit, the reference voltage is no longer increased by the diode. In the above example, it takes a certain amount of time for the driving power supply voltage to fall to -24V after turning on and to stabilize, and the effect of preventing the reversal of the height from occurring can be prevented. Since the operation is not guaranteed, there is a problem that the inrush current may damage the reference voltage generation circuit and the drive power supply voltage generation circuit.

Further, in the liquid crystal display device shipped as a product, the liquid crystal display device which is accidentally operated on the mounting substrate even though one of the cathode and anode terminals of the diode is released due to a disconnection or the like. Therefore, as a countermeasure against the malfunction in the transient operating state when the power is turned on using the diode as described above, a liquid crystal display device that can be used reliably, and in particular, a liquid crystal display device that performs AC drive of a liquid crystal panel is provided. It was impossible.

In Japanese Patent Laid-Open No. 6-118124, in the power supply circuit that supplies currents to a plurality of loads (elements) as described above, the loads are operated at the same time, which causes noise in the output of the power supply circuit. (Steep spike voltage)
There is disclosed a problem in which the problem of causing a breakdown due to latch-up in an element or the like having a CMOS structure as a trigger due to the occurrence of the above is solved by shifting the input timing of a signal applied to each element for each block. There is. The technique disclosed in this publication is not directly related to the drive circuit of the liquid crystal display device, but as a device having a power supply circuit having a plurality of loads, a problem occurs when a plurality of loads operate simultaneously. It has a common problem with liquid crystal display devices.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to essentially eliminate the inconvenience caused by a malfunction of a driver or the like when the main power source is turned on. It is an object of the present invention to provide a drive circuit for a liquid crystal display device, which has extremely high reliability and can significantly reduce the occurrence rate of defects in the market.

[0014]

A drive circuit for a liquid crystal display device according to the present invention includes a polarity inversion signal generation circuit for generating a polarity inversion signal synchronized with a synchronizing signal of an image signal, and a level change of the polarity inversion signal. An inversion voltage generating circuit for generating a voltage for driving a display pixel, the polarity of which is inverted on the basis of the polarity, and a switch means connected between the output of the polarity inversion signal generating circuit and the input of the inversion voltage generating circuit. The supply of the polarity inversion signal to the inversion voltage generation circuit is interrupted until a certain period of time elapses after the power is turned on, or until a predetermined signal is input after the power is turned on. And switch control means for controlling the switch means so as to be released, thereby achieving the above object.

A drive circuit of a liquid crystal display device according to the present invention, a polarity inversion signal generating circuit for generating a polarity inversion signal synchronized with a synchronizing signal of an image signal, and a polarity inversion based on a level change of the polarity inversion signal. , An inversion voltage generation circuit that generates a voltage for driving display pixels, and polarity inversion from when the power is turned on until a certain period of time elapses, or from when the power is turned on until a predetermined signal is input. And a potential fixing means for forcibly fixing the signal to a constant level, whereby the above object is achieved.

The drive circuit of the liquid crystal display device according to the present invention is connected to the output of the gradation voltage generation circuit and the gradation voltage generation circuit for generating the gradation voltage whose polarity is inverted every predetermined period, and is connected to the output of the gradation voltage generation circuit. And a driver circuit for applying a regulated voltage to picture element electrodes forming picture elements. The gradation voltage generating circuit outputs the output in a high impedance state or at a constant potential until a certain period elapses after the power is turned on, or until a predetermined signal is input after the power is turned on. It has a control means by which the above-mentioned object is achieved.

A drive circuit of a liquid crystal display device according to the present invention is connected to an opposed voltage generating circuit for generating an opposed voltage whose polarity is inverted every predetermined period and an output of the opposed voltage generating circuit, And a driver circuit for applying to a counter electrode which constitutes a picture element. The counter voltage generation circuit described above is an output control that keeps its output in a high impedance state or at a constant potential from a time when the power is turned on until a certain period elapses, or a time when a predetermined signal is input from the time the power is turned on. Means are provided by which the above-mentioned object is achieved.

A drive circuit of a liquid crystal display device according to the present invention is connected to an opposed voltage generating circuit for generating an opposed voltage whose polarity is inverted every predetermined period and an output of the opposed voltage generating circuit. And a driver circuit for applying to the counter electrode of the auxiliary capacitance added to the capacitance forming the picture element. The counter voltage generation circuit described above is an output control that keeps its output in a high impedance state or at a constant potential from a time when the power is turned on until a certain period elapses, or a time when a predetermined signal is input from the time the power is turned on. Means are provided by which the above-mentioned object is achieved.

[0019]

In the present invention (Claim 1), the switch control means shuts off the switch means and inverts the polarity for a certain period of time after the power is turned on or until a predetermined signal is input. Since the signal is not supplied to the inversion voltage generation circuit, this inversion voltage generation circuit keeps the voltage applied to the pixel capacitance and the auxiliary capacitance of the liquid crystal at a constant voltage or a high impedance state for a certain period after the power is turned on. The polarity will not be inverted. As a result,
The AC drive of the liquid crystal panel is not performed for a certain period after the power is turned on, and thus the malfunction of the driver or the like when the main power is turned on can be essentially eliminated.

In the present invention (claim 2), the potential fixing means forcibly keeps the polarity inversion signal constant for a certain period of time after the power is turned on or until a predetermined signal is input. Since I fixed it to the level,
Even in this case, the voltage applied from the inversion voltage generation circuit to the picture element capacitance and the auxiliary capacitance of the liquid crystal becomes a constant voltage for a certain period after the power is turned on, and the polarity is not inverted. It is possible to essentially eliminate the malfunction of the driver or the like when the main power is turned on.

According to the present invention (claims 3 to 5), the picture element of the picture element capacity of the liquid crystal is maintained for a certain period of time after the power is turned on or until a predetermined signal is input. The voltage applied to the electrodes, the counter electrodes, or the counter electrodes of the auxiliary capacitors is set to a constant voltage, or these electrodes are set to the high impedance state, so the malfunction of the driver etc. when the main power is turned on is essentially eliminated. can do.

[0022]

Embodiments of the present invention will be described below.

(Embodiment 1) FIGS. 1 to 4 are views for explaining a drive circuit of a liquid crystal display device according to a first embodiment of the present invention, and FIG. 1 shows an example of a drive circuit of the liquid crystal display device. 2 is a circuit diagram showing a concrete configuration of each part shown in FIG. 1, FIG. 3 is a time chart showing an operation of a drive circuit of the liquid crystal display device, and FIG. 4 is an overall configuration of the liquid crystal display device. It is a block diagram showing.

The structure of the liquid crystal display device of this embodiment will be described with reference to FIG. Here, a case of performing gradation display using a liquid crystal display device of the TFT active matrix system will be described.

In the figure, reference numeral 100 denotes a TFT active matrix type liquid crystal display device.
Is provided with a liquid crystal layer which is a display medium, and a liquid crystal panel 13 composed of two substrates 11 and 12 which sandwich the liquid crystal layer.
On one substrate 11 of the liquid crystal panel 13, a plurality of picture element electrodes 14 forming picture elements are arranged in a matrix of m rows and n columns, and m scanning lines corresponding to each row of the picture element electrodes are further arranged. Wirings G1 to Gm and n signal wirings S1 to Sn corresponding to each column of the picture element electrodes are arranged.

At the intersection of the scanning line Gj (j is an integer of 1 to m) and the signal line Si (i is an integer of 1 to n), a thin film transistor (hereinafter also referred to as a TFT) forming a pixel is formed. .) 15 are arranged and the TFT 1 of each picture element is arranged.
Reference numeral 5 is connected between the corresponding signal wiring Si and the picture element electrode 14 and is controlled to be turned on / off by a signal from the corresponding scanning wiring Gj.

On the other substrate 12 constituting the liquid crystal panel 13, a common electrode 16 is formed on the entire surface of the substrate. Then, in the portion where the common electrode 16 of the substrate 12 and each pixel electrode 14 of the substrate 11 face each other with the liquid crystal layer interposed therebetween,
A pixel capacity is formed.

Further, the scanning wiring Gj is based on the timing signal from the control circuit 19 and the scanning wiring Gj.
The signal wiring Si is connected to a gate driver 18 for sequentially driving 1 to Gm, and the signal wiring Si sends a video signal to the signal wiring S1 based on a timing signal from the control circuit 19.
Is connected to a digital data driver 17 which outputs to Sn.

Here, the video signal is 2-bit data D.
It consists of 0 and D1 and can display four gradations. Therefore, the digital data driver 17 has four kinds of gradation voltages V0 generated by the gradation voltage generation circuit group 20.
To V3 are supplied, any one of the gradation voltages V0 to V3 is selected according to the values of the data D0 and D1 and is output to the corresponding signal wiring Si. And the picture element electrode 1 of each picture element
Each time the scanning line Gj of the corresponding row is scanned, the gradation voltage V0 to V3 corresponding to the video signal of the picture element is charged from the signal line Si through the TFT 15 until the scanning is performed next time. The gradation voltages V0 to V3 are held.

The counter voltage supplied from the counter voltage generating circuit 21 is applied to the common electrode 16 of the other substrate 12. Therefore, the liquid crystal layer of each picture element changes its optical characteristics due to the potential difference between the gray scale voltages V0 to V3 charged in the picture element electrode 14 and the counter voltage applied to the common electrode 16, whereby the liquid crystal panel 13 is changed. Dot matrix display is performed.

Further, here, in order to prevent the deterioration of the liquid crystal, the voltage levels of the gradation voltages V0 to V3 and the counter voltage are periodically switched between a high voltage level and a low voltage level, and the gradation levels are changed. AC driving is performed in which the polarity between the voltages V0 to V3 and the counter voltage is reversed.

The polarity level inversion signal POL supplied from the control circuit 19 is used to switch the voltage level.
In synchronization with the above, the gradation voltage generating circuit group 20 and the counter voltage generating circuit 21 are performed. The counter voltage generation circuit 2
The counter voltage generated by 1 is kept constant, and the gradation voltages V0 to V3
It is also possible to switch only the voltage level of.

Further, a storage capacitor (not shown) may be formed in each picture element of the liquid crystal panel 13. In this auxiliary capacitance, one electrode is connected to the drain terminal of the TFT 15, and the auxiliary capacitance counter voltage is applied to the other electrode (counter electrode). If each picture element is provided with such an auxiliary capacitance, when the picture element electrode 14 is charged with the gradation voltages V0 to V3, the auxiliary capacitance is also charged.
The leakage current after T15 is cut off causes the pixel electrode 14
It is possible to compensate for the decrease in the charging voltage. And
Also in this case, the auxiliary capacitance counter voltage applied to the counter electrode of the auxiliary capacitance by the auxiliary capacitance counter voltage generation circuit (not shown) is periodically switched between the high voltage level and the low voltage level based on the polarity inversion signal POL. You can

FIG. 1 shows the control circuit 1 shown in FIG.
9 is a block diagram showing a circuit portion related to a polarity inversion signal POL in FIG. 9 and an internal configuration of a grayscale voltage generation circuit group 20. FIG. However, in FIG. 1, the gradation voltage generation circuit group 20
As for the internal configuration of the above, only the gradation voltage generating circuit 1 for generating the gradation voltage V0 is shown.

The control circuit 19 includes a polarity inversion signal generation circuit 2, a switch circuit 3, and a control circuit 4, and is configured to supply the polarity inversion signal POL to the gradation voltage generation circuit group 20.

Here, the polarity inversion signal generation circuit 2 is
It is a circuit that generates a polarity inversion signal POL whose voltage level changes periodically based on a synchronization signal of an image signal. The switch circuit 3 is provided on the output side of the circuit 2, and supplies and cuts off the polarity inversion signal POL to the gradation voltage generating circuit 1 by turning on and off the switch circuit 3. The control circuit 4 controls the switch circuit 3 by a control signal.
This is a circuit for controlling so that the output of the polarity inversion signal POL is cut off by the switch circuit 3 when the power is turned on, and the output of the polarity inversion signal POL is applied to the gradation voltage generating circuit 1 after a lapse of a certain time.

The gradation voltage generating circuit 1 is a power supply for generating a gradation voltage V0 whose voltage level periodically switches between a high voltage level and a low voltage level based on the polarity switching signal POL from the control circuit 19. Circuit. The gradation voltage V0 generated by the gradation voltage generating circuit 1 is supplied to the digital data driver 17 from the gradation voltage generating circuit group 20 shown in FIG.

FIG. 2 shows a specific configuration of the polarity reversal signal generation circuit 2, the switch circuit 3, the control circuit 4, and the grayscale voltage generation circuit 1. In this embodiment, since the liquid crystal AC drive is line inversion drive, the polarity inversion signal generation circuit 2
Generates a polarity inversion signal POL based on the horizontal sync signal. That is, the polarity inversion signal generation circuit 2 is composed of a frequency dividing circuit which inputs the horizontal synchronizing signal to the clock input CK of the D flip-flop circuit 2a and feeds the inverted output Q bar back to the D input. Therefore, from the output Q of the D flip-flop circuit 2a,
A signal whose logic level is inverted is output every time the horizontal synchronizing signal rises, and this signal becomes the polarity inversion signal POL.

The switch circuit 3 is composed of an analog switch, a three-state buffer, or the like which conducts when the control input becomes H level. In the case of these analog switches and the like, the input of the polarity inversion signal POL in the grayscale voltage generation circuit 1 becomes a high impedance state when the analog switches are cut off. However, depending on the circuit configuration, it may be better to fix it to either the H level or the L level rather than such a high impedance state. In this case, as shown in FIG. Can be pulled up to the H level power source via the resistor RU, or can be pulled down to the L level ground power source via the resistor RD.

The control circuit 4 has a resistor R3 between the power supply grounds.
And a capacitor C1 are connected in series, and the terminal voltage of the capacitor C1 is output to the switch circuit 3 as an on / off voltage SP via the two inverters 4a and 4b.

Therefore, when the power supply voltage rises when the power is turned on, the capacitor C1 is charged through the resistor R3 and the terminal voltage gradually rises. When the terminal voltage of the capacitor C1 becomes a predetermined voltage or more after a certain time, the inverter 4a Output switches to the L level, and the output of the inverter 4b, that is, the on / off voltage SP switches to the H level. Since the on / off voltage SP output from the control circuit 4 is sent to the control input of the switch circuit 3, this on / off voltage S
By switching P to the H level, the switch circuit 3 which has been cut off until then becomes conductive. The on / off voltage SP
Can be arbitrarily set by adjusting the time constants of the resistor R3 and the capacitor C1 before switching to H level.

The gradation voltage generating circuit 1 is an operational amplifier 1
The output of a is negatively fed back to the inverting input via the resistor R1, and the polarity switching signal POL is input to the inverting input of the operational amplifier 1a via the resistor R2. Therefore, when the voltage of the polarity switching signal POL is VPOL, the gradation voltage V0 output from the operational amplifier 1a is represented by V0 =-(R1 / R2) VPOL, and the voltage VPOL of this polarity switching signal POL is in the horizontal scanning period. When switching between the H level and the L level for each, the voltage level of the gradation voltage V0 also switches between the high voltage level and the low voltage level for each horizontal scanning period. Further, the gradation voltage generating circuit 1 outputs an L level voltage level when its input is in a high impedance state.

Similarly to the gradation voltage generating circuit 1, the gradation voltage generating circuit for generating the other gradation voltages V1 to V3 in the gradation voltage generating circuit group 20 is also composed of an inverting amplifier by an operational amplifier. However, the gradation voltage generating circuit 1 is configured so that the ratio of the resistors R1 and R2 is different.
Further, the counter voltage generating circuit 21 is also configured by using an operational amplifier like the gradation voltage generating circuit 1. Further, when the auxiliary capacitance is provided, the auxiliary capacitance counter voltage generation circuit (not shown) is also configured by using an operational amplifier like the counter voltage generation circuit 21. The polarity inversion signal PO supplied to the gradation voltage generating circuit for generating the other gradation voltages V1 to V3, the counter voltage generating circuit 21, and the auxiliary capacitor counter voltage generating circuit.
L is also the same as that supplied to the gradation voltage generating circuit 1.

Next, the operation of the liquid crystal display device having the above structure will be described with reference to FIG.
It will be described based on.

When the power is turned on at time t1 and the power supply voltage rises, the polarity inversion signal POL is synchronized with the horizontal synchronization signal.
Alternate between H level and L level. However, the on / off voltage SP is at the L level and the switch circuit 3
Is cut off, the input of the gradation voltage generating circuit 1 is
It is in a high impedance state or fixed to H level or L level (in FIG. 3, the state is fixed to L level). Then, at time t2 after the lapse of a certain time, the on / off voltage SP is switched to the H level and the switch circuit 3
Are connected to each other, so that the grayscale voltage generating circuit 1 has an H level and an L level.
The polarity inversion signal POL whose level and the level are alternately switched is input.

Therefore, according to the liquid crystal display device of the present embodiment, from the time the power is turned on until a certain time elapses, that is, the digital data driver 17 and the gate driver 18.
Until each of them operates stably, each gradation voltage generating circuit of the gradation voltage generating circuit group 20 and the counter voltage generating circuit 21 respectively output a constant voltage.

For this reason, it is possible to avoid charging and discharging in the pixel capacity when the operation of each circuit is unstable immediately after the power is turned on.

Further, during this period, the storage capacitor counter voltage generating circuit also outputs a low voltage level, so that charging and discharging of the storage capacitor can be avoided.

As a result, the AC drive of the liquid crystal panel is not performed for a certain period after the power is turned on, which can essentially eliminate the malfunction of the driver or the like when the main power is turned on. There is an effect that the reliability of the liquid crystal display device is made extremely high and the occurrence rate of defects in the market can be greatly reduced.

(Embodiment 2) FIGS. 5 and 6 show the second embodiment of the present invention.
6 is a diagram for explaining a drive circuit of the liquid crystal display device according to the embodiment of the present invention, FIG. 5 is a circuit diagram showing a part of the drive circuit of the liquid crystal display device, and FIG. 6 is a time chart showing the operation of the drive circuit of the liquid crystal display device. It is a chart. However, components having the same functions as those in the first embodiment shown in FIGS. 1 to 4 are designated by the same reference numerals.

The liquid crystal display device of this embodiment also shows a case where gradation display is performed using the same TFT active matrix type liquid crystal display device as that of the first embodiment shown in FIG. The details of the circuit portion related to the polarity inversion signal POL and the gradation voltage generation circuit group 20 in the control circuit 19 shown in FIG. 4 are the same as those in the first embodiment shown in FIG. However, a part of the specific configuration of the control circuit 19 and the gradation voltage generation circuit group 20 is different from that of the first embodiment.

FIG. 5 shows the control circuit 19 of this embodiment.
And a specific circuit configuration of the gradation voltage generation circuit group 20.

Also in this embodiment, the gradation voltage generating circuit 1
Is constructed by using the operational amplifier 1a as an inverting amplifier as in the case of the first embodiment. The polarity inversion signal generation circuit 2 is also composed of a circuit for dividing the horizontal synchronizing signal by the D flip-flop circuit 2a, as in the case of the first embodiment.

In this embodiment, the switch circuit 3
Is composed of an AND gate. When the on / off voltage SP which is the output of the control circuit 4 is at the H level, the AND gate configuring the switch circuit 3 outputs the polarity inversion signal POL from the polarity inversion signal generation circuit 2 as it is, and the on / off voltage SP is L. Level is always L
The level is output and the voltage level as the polarity inversion signal POL is fixed.

The control circuit 4 is composed of a single shot circuit by the timer circuit 4c. The timer circuit 4c connects an external resistor R4 and an external capacitor C2 to the external RC terminal and the external C terminal, and sets the power supply voltage to B
By inputting to the input terminal, it functions as a single shot circuit (monostable multivibrator).

Therefore, when the power supply voltage rises when the power is turned on, the inverting output Q bar of the timer circuit 4c becomes L level and the timer starts operating. That is, the on / off voltage SP rises to the H level. The on / off voltage SP output from the control circuit 4 is supplied to the switch circuit 3
When the on / off voltage SP is switched to the H level, the AND gate, which has been outputting the L level until then, outputs the polarity inversion signal POL as it is. The fixed time until the on / off voltage SP is switched to the H level can be arbitrarily set by adjusting the time constants of the external resistor R4 and the external capacitor C2.
The control circuit 4 may be replaced with the timer circuit 4c by using a circuit in which a simple oscillation circuit such as a flip-flop circuit and a counter circuit are combined.
However, in such an oscillation circuit, it is necessary to set the initial state correctly.

Regarding the gradation voltage generating circuit for generating the other gradation voltages V1 to V3 in the gradation voltage generating circuit group 20, the counter voltage generating circuit 21 and the auxiliary capacitor counter voltage generating circuit,
It is configured similarly to the gradation voltage generating circuit 1.

Next, the operation of the liquid crystal display device having the above configuration will be described with reference to FIG.
It will be described based on. When the power is turned on and the power supply voltage rises at time t3, the polarity inversion signal POL switches between the H level and the L level in synchronization with the horizontal synchronizing signal. Further, the on / off voltage SP becomes L level when the timer circuit 4c starts measuring the time, and the AND of the switch circuit 3 is performed.
Since the output of the gate is fixed to the L level, the input of the gradation voltage generating circuit 1 is also fixed to the L level. Then, at time t4 after the elapse of a certain time, the timer circuit 4c completes the time measurement, the on / off voltage SP is switched to the H level, and the gradation voltage generating circuit 1 is switched to the H level via the AND gate of the switch circuit 3. The polarity inversion signal POL that alternately switches between the level and the L level comes to be input.

Therefore, according to the liquid crystal display device of the present embodiment, from the time the power is turned on until a certain time elapses, that is, until the digital data driver 17 and the gate driver 18 operate stably. , Each gradation voltage generation circuit of the gradation voltage generation circuit group 20 and the counter voltage generation circuit 21
Will output a low voltage level voltage.
For this reason, it is possible to avoid charging and discharging in the pixel capacity in a state where the operation of each circuit is unstable immediately after the power is turned on.

Further, during this period, the storage capacitor counter voltage generating circuit also outputs a low voltage level, so that charging and discharging of the storage capacitor can be avoided.

As a result, also in this embodiment, the same effect as in the above embodiment can be obtained.

The switch circuit 3 can also be formed by analog switches as in the first embodiment.
Further, if the on / off voltage SP output from the control circuit 4 is output from the output Q of the timer circuit 4c, it changes to the L level after a lapse of a fixed time after the power is turned on. Therefore, the switch circuit 3 may be configured by an OR gate. it can.

(Embodiment 3) FIGS. 7 and 8 show a third embodiment of the present invention.
8 is a diagram for explaining a drive circuit of the liquid crystal display device according to the embodiment of the present invention, FIG. 7 is a circuit diagram showing a part of the drive circuit of the liquid crystal display device, and FIG. 8 is a time chart showing the operation of the drive circuit of the liquid crystal display device. It is a chart. However, components having the same functions as those in the first embodiment shown in FIGS. 1 to 4 are designated by the same reference numerals.

The liquid crystal display device of this embodiment also shows a case where gradation display is performed using the same TFT active matrix type liquid crystal display device as that in the first embodiment shown in FIG. However, from the control circuit 19,
Not only the polarity inversion signal POL but also the on / off voltage SP is sent to the gradation voltage generating circuit group 20.
Therefore, the details of the circuit portion related to the polarity inversion signal POL and the gradation voltage generation circuit group 20 in the control circuit 19 shown in FIG. 7 are different from the configuration of the first embodiment shown in FIG. Is configured to include the polarity inversion signal generation circuit 2 and the control circuit 4, and the gradation voltage generation circuit group 20 is configured to include the gradation voltage generation circuit 1 and the switch circuit 3.

Specific configurations of the control circuit 19 and the gradation voltage generating circuit group 20 will be described with reference to FIG.

Also in this embodiment, the gradation voltage generating circuit 1
Is constructed by using the operational amplifier 1a as an inverting amplifier as in the case of the first embodiment. The polarity inversion signal generating circuit 2 is also composed of a circuit for dividing the horizontal synchronizing signal by the D flip-flop circuit 2a, as in the case of the first embodiment. Further, the control circuit 4 also has a resistor R3 and capacitors C1 and C2 as in the case of the first embodiment.
It is composed of individual inverters 4a and 4b.
The switch circuit 3 is also composed of analog switches and the like as in the case of the first embodiment.

However, in the present embodiment, the polarity inversion signal POL output from the polarity inversion signal generation circuit 2 of the control circuit 19 is directly input to the gradation voltage generation circuit 1 of the gradation voltage generation circuit group 20, and The switch circuit 3 is connected to the output side of the gradation voltage generating circuit 1. The ON / OFF voltage SP from the control circuit 4 is input to the control input of the switch circuit 3.

Therefore, when the on / off voltage SP is at the L level, the switch circuit 3 is cut off and the output of the grayscale voltage generating circuit 1 is in a high impedance state. However, depending on the circuit configuration, it may be better to fix the voltage level to a constant voltage level than in such a high impedance state. In this case, as shown in FIG. It is also possible to pull up to the H level power supply via the resistor and to pull down to the L level ground power source via the resistor RD.

Regarding the gradation voltage generating circuit for generating the other gradation voltages V1 to V3 in the gradation voltage generating circuit group 20, the counter voltage generating circuit 21 and the auxiliary capacitor counter voltage generating circuit,
It is configured similarly to the gradation voltage generating circuit 1.

Next, the operation of the liquid crystal display device having the above configuration will be described with reference to FIG.
It will be described based on. When the power supply is turned on at time t5 and the power supply voltage rises, the polarity inversion signal POL switches between the H level and the L level in synchronization with the horizontal synchronization signal, and the grayscale voltage generation circuit 1 switches between the high voltage level and the low voltage level. The gradation voltage V0 that is switched between is output. However, since the on / off voltage SP is L level at this time and the switch circuit 3 is cut off, this gradation voltage V0 is not sent to the digital data driver 17 shown in FIG. 4, and the output from the switch circuit 3 is output. Is fixed to a high impedance state or H level or L level. At time t6 after a lapse of a certain time, the on / off voltage SP is switched to the H level and the switch circuit 3 is turned on, so that the gradation voltage V0 that switches between the high voltage level and the low voltage level is supplied to the digital data driver 17. Will be done.

Therefore, according to the liquid crystal display device of the present embodiment, from the time the power is turned on until a certain time elapses, that is, until the digital data driver 17 and the gate driver 18 operate stably. Are the grayscale voltage generation circuits of the grayscale voltage generation circuit group 20 and the counter voltage generation circuit 2
1 outputs a constant voltage, or this output is in a high impedance state. Also in this embodiment having such a configuration, the same effects as those of the above-described embodiments can be obtained.

In the first to third embodiments described above, the control circuit 4 switches the on / off voltage SP to the H level after a lapse of a certain time after the power is turned on. However, a predetermined signal from an external circuit or the like is transmitted. When input, this on-off voltage S
It is also possible to switch P to H level. In this case, the external circuit or the like sends a predetermined signal at an appropriate time after the power is turned on.

In the first to third embodiments, the TF
The case where gradation display is performed using the T active matrix type liquid crystal display device has been described. The same can be applied to the generation circuit as in the above embodiment.
The invention is not limited to the TFT active matrix system, and can be applied to the inversion voltage generation circuit of the liquid crystal display device of other systems in the same manner as described above.

[0074]

As described above, according to the drive circuit of the liquid crystal display device of the present invention, the AC drive of the picture element is performed after the appropriate period has elapsed since the power was turned on and the operation of the driver is stabilized. With this configuration, the charge and discharge of the pixel capacity and auxiliary capacity are started after the operation of the driver is stabilized, and the malfunction of the driver etc. when the main power is turned on can be essentially eliminated. Thus, there is an effect that the reliability of the liquid crystal display device is made extremely high and the occurrence rate of defects in the market can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of a drive circuit of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of a part of the drive circuit of the first embodiment.

FIG. 3 is a time chart showing the operation of the drive circuit of the liquid crystal display device according to the first embodiment.

FIG. 4 is a block diagram showing an overall configuration of a liquid crystal display device according to the first embodiment.

FIG. 5 is a circuit diagram showing a partial configuration of a drive circuit of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a time chart showing the operation of the drive circuit of the liquid crystal display device of the second embodiment.

FIG. 7 is a circuit diagram showing a configuration of part of a drive circuit of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a time chart showing the operation of the drive circuit of the liquid crystal display device of the third embodiment.

FIG. 9 is a time chart showing an operation when the logic power supply voltage and the drive power supply voltage are turned on in the drive circuit of the conventional liquid crystal display device.

FIG. 10 is a diagram showing a configuration of a reference voltage generation circuit for a drive circuit in a conventional liquid crystal display device.

[Explanation of symbols]

 1 gradation voltage generation circuit 1a operational amplifier 2 polarity inversion signal generation circuit 2a flip-flop 3 switch circuit 4 control circuit 4a, 4b inverter 4c timer circuit 11, 12 substrate 13 liquid crystal panel 14 picture element electrode 15 switching element 16 counter electrode 17 digital data Driver 18 Gate driver 19 Control circuit 20 Grayscale voltage generation circuit group 21 Opposed voltage generation circuit 100 Liquid crystal display device POL Polarity inversion signal SP ON / OFF signal V0 Grayscale voltage RU Pullup resistance RD Pulldown resistance

Claims (5)

[Claims] 1. A polarity inversion signal generation circuit for generating a polarity inversion signal in synchronization with a synchronization signal of an image signal, and a voltage for driving a display pixel, the polarity of which is inverted based on a level change of the polarity inversion signal. A switch means connected between the output of the polarity inversion signal generation circuit and the input of the inversion voltage generation circuit, and from the time of power-on until a certain period of time elapses, or A switch control means for controlling the switch means so that the supply of the polarity inversion signal to the inversion voltage generation circuit is interrupted from the time of power-on until a predetermined signal is input, and then the interruption is released. A drive circuit for the liquid crystal display device provided. 2. A polarity inversion signal generating circuit for generating a polarity inversion signal in synchronization with a synchronizing signal of an image signal, and a voltage for driving a display pixel, the polarity of which is inverted based on a level change of the polarity inversion signal. And a polarity inversion signal that forcibly fixes the polarity inversion signal to a constant level from the time the power is turned on until a certain period elapses, or from the time the power is turned on until a predetermined signal is input. A drive circuit for a liquid crystal display device, comprising a potential fixing means. 3. A gradation voltage generating circuit for generating a gradation voltage whose polarity is inverted every predetermined period; and a gradation voltage connected to an output of the gradation voltage generating circuit,
The gradation voltage generating circuit is provided with a driver circuit for applying to a pixel electrode that constitutes a pixel, and a predetermined signal is input to the gradation voltage generating circuit from power-on until a certain period elapses or from power-on. A drive circuit for a liquid crystal display device having an output control means for keeping its output in a high impedance state or at a constant potential. 4. A counter voltage generating circuit for generating a counter voltage whose polarity is inverted every predetermined period; and a counter voltage connected to an output of the counter voltage generating circuit,
The counter voltage generating circuit is provided with a driver circuit for applying to a counter electrode forming a pixel, and the counter voltage generating circuit operates from a time when the power is turned on until a predetermined period elapses, or a time when a predetermined signal is input from the time when the power is turned on. A drive circuit of a liquid crystal display device having an output control means for setting its output to a high impedance state or a constant potential during a period. 5. A counter voltage generating circuit that generates a counter voltage whose polarity is inverted every predetermined period; and a counter voltage connected to an output of the counter voltage generating circuit,
And a driver circuit for applying to the counter electrode of the auxiliary capacitor added to the capacitor forming the picture element, and the counter voltage generating circuit is provided for a predetermined period after the power is turned on, or for a predetermined period after the power is turned on. The drive circuit for the liquid crystal display device, which has an output control means for keeping its output in a high impedance state or at a constant potential until the signal is input.