JPH08172359A - Processor for sigma delta signal - Google Patents

Abstract

PURPOSE: To process a ΣΔ signal without spoiling the feature of the ΣΔ A signal. CONSTITUTION: A ΣΔ signal supplied to an input terminal 1 is supplied to a low pass filter(LPF) 2 and converted into a multi-bit digital sound signal, which is supplied to a multiplier 3. On the other hand, a control signal from a control signal input terminal 4 is supplied to a coefficient generator 6 through a control circuit 5 and a coefficient for processing an optional sound signal is generated and supplied to the multiplier 3. A signal from the multiplier 3 is supplied to a ΣΔ converter 7 and a reconverted ΣΔ signal is supplied to the fixed contact B of a switch 8. The ΣΔ signal from the input terminal 1 is supplied also to the fixed contact A of the switch 8 through a delay circuit 9 corresponding to the LPF 2, the multiplier 3 and the ΣΔ converter 7. The switch 8 is controlled by the control circuit 5 so as to select the contact A in a normal state and select the contact B only in a processing period and a signal switched by the switch 8 is extracted from an output terminal 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sigma-delta signal processing apparatus for subjecting a sigma-delta modulated audio signal to arbitrary processing such as fading.

[0002]

2. Description of the Related Art As a method of digitizing and transmitting (recording / reproducing) an audio signal, a recording / reproducing apparatus such as a CD or DAT, or a digital audio broadcasting such as satellite broadcasting has been conventionally practiced. In such a digital audio transmission device, conventionally, when digitized, a format such as a sampling frequency of 48 kHz, 44.1 kHz or the like and a quantization bit number of 16 bits or the like was specified.

However, in such a conventional digital audio transmission apparatus, the number of quantization bits of the digital audio signal generally defines the dynamic range of the demodulated audio signal. Therefore, for example, in order to transmit a signal with higher sound quality, it is necessary to increase the number of quantization bits from the current 16 bits to 20 or 24 bits. However, once the format is specified, it is not possible to easily increase the number of quantization bits, so that it is not possible to extract an audio signal of higher sound quality from these devices.

By the way, for example, a method called sigma delta (ΣΔ) modulation has been proposed as a method for digitizing an audio signal (Journal of the Acoustical Society of Japan, Vol. 46, No. 3, (199).
0) pp. 251-257, "AD / DA converter and digital filter (Yoshio Yamazaki)", etc.).

That is, FIG. 9 shows an example of a configuration using, for example, 1-bit ΣΔ modulation. In FIG. 9, the input audio signal from the input terminal 91 is supplied to the integrator 93 through the adder 92. The signal from the integrator 93 is supplied to the comparator 94, is compared with, for example, the midpoint potential of the input audio signal, and is quantized by, for example, 1 bit for each sample period. The frequency (sampling frequency) of the sampling period is 64 times or 128 times that of the conventional 48 kHz and 44.1 kHz. The quantization may be 2 bits or 4 bits.

This quantized signal is supplied to the delay unit 95 and delayed by one sample period. This delayed signal is, for example, 1
It is supplied to the adder 92 through the bit DA converter 96 and added to the input audio signal from the input terminal 91. The quantized signal output from the comparator 94 is the output terminal 9
Taken out to 7. Therefore, according to this ΣΔ modulation, as shown in the above-mentioned document, by sufficiently increasing the frequency of the sampling period (sampling frequency), for example, a digital audio signal having a wide dynamic range can be obtained even with a small number of bits of 1 bit. You can

[0007]

By the way, in the conventional digital audio recorder, when a digital audio signal is recorded / reproduced on / from a recording medium such as a magnetic tape,
It may be necessary to mute the level of the reproduced audio signal to zero level. That is, for example, the error of the reproduction signal increases due to the defect of the recording medium during reproduction
If the error correction capability of the recorder is exceeded, the reproduced audio signal will contain very large noise.

Therefore, in such a case, the level of the reproduced audio signal is usually set to zero. However, in that case, if the level of the audio signal is suddenly set to zero, it may sound like noise in the sense of hearing. Therefore, in such a case, the level of the reproduced audio signal is gradually lowered (faded) with time, and is completely reduced to zero after about several milliseconds to several tens of milliseconds.

In such a case, in the conventional format such as CD or DAT, for example, the processing shown in FIG. 10 is performed. That is, in FIG. 10, the multi-bit (for example, 16-bit) digital audio signal from the input terminal 81 is taken out to the output terminal 83 through the multiplier 82.

Further, for example, a control signal designating a fade start timing and a speed is supplied to the control signal input terminal 84, and this control signal is supplied to the control circuit 85 to generate an arbitrary fade signal. Then, by supplying the fade signal to the coefficient generator 86, for example, a coefficient for gradually lowering the level of the audio signal to mute it to a zero level is generated, and this coefficient is supplied to the multiplier 82.

As a result, the level of the digital audio signal supplied to the digital signal input terminal 81 at the output terminal 83 gradually decreases at a specified speed from the timing specified by the control signal, for example. The signal that has been muted to zero level is taken out, and so-called fade-out processing is performed. It is also possible to perform fade-in processing for gradually increasing the level of the audio signal from zero level by reversing the order of generation of the coefficients.

However, such processing cannot be performed on the ΣΔ-modulated digital audio signal (hereinafter referred to as ΣΔ signal). That is, for the ΣΔ signal,
Since the word length of each data is short, for example, 1 bit, it is not possible to obtain sufficient calculation accuracy even if multiplication is performed using the multiplier 82 as described above as in the conventional case. Therefore, it is difficult to realize the fade process in the above-mentioned ΣΔ signal by the same method as the conventional one.

On the other hand, for example, as shown in FIG. 11, a ΣΔ signal is converted into a conventional CD or D by using a low-pass filter.
It is conceivable to convert into a signal format such as AT for processing. That is, in FIG. 11, the input terminal 7
For example, the 1-bit ΣΔ signal supplied to 1 is supplied to the low-pass filter 72 and converted into, for example, a 16-bit multi-bit digital audio signal. The converted digital audio signal is supplied to the multiplier 73.

Further, for example, a control signal designating the start timing and speed of the fade is supplied to the control signal input terminal 74, and this control signal is supplied to the control circuit 75 to generate an arbitrary fade signal. Then, by supplying the fade signal to the coefficient generator 76, for example, a coefficient for gradually lowering the level of the audio signal and muting it to the zero level is generated, and this coefficient is supplied to the multiplier 73.

As a result, a digital audio signal whose level is controlled by the coefficient from the coefficient generator 6 is extracted from the multiplier 73 with respect to the digital audio signal from the low-pass filter 72. Then, this digital audio signal is further supplied to the ΣΔ modulator 77, and again converted into, for example, a 1-bit ΣΔ signal, and the reconverted ΣΔ signal is taken out to the output terminal 78.

Thus, the output terminal 78 is connected to the input terminal 71.
For the ΣΔ signal from, the level of the audio signal is gradually reduced at a specified speed from the timing specified by the control signal, and a signal muted to zero level is taken out, and so-called fade-out processing is performed. Be seen. It is also possible to perform fade-in processing in which the level of the audio signal is gradually increased from zero level by reversing the order of generation of the coefficients. That is, according to this apparatus, it is possible to perform processing such as fade in the same manner as in the past.

However, when this device is used,
The ΣΔ signal supplied to the input terminal 71 is always converted by the low-pass filter 72 into, for example, a 16-bit multi-bit digital audio signal. That is, in this device,
Even if the ΣΔ signal is not processed such as fade,
It passes through the low-pass filter 72 and the ΣΔ modulator 77. Therefore, the characteristics of the signal become the same as those of the conventional CD, DAT, etc., and the characteristics of the original ΣΔ modulation such as wide band and high dynamic range cannot be utilized.

This application has been made in view of such a point, and a problem to be solved is that ΣΔ modulation has a problem in a conventional apparatus when a process such as a fade is performed on a ΣΔ signal. However, the characteristics such as wide band and high dynamic range cannot be utilized, and it is difficult to realize processing such as fade.

[0019]

The first means of the present invention uses a low-pass filter (2) for the ΣΔ-modulated signal in performing arbitrary processing on the ΣΔ-modulated signal (input terminal 1). Means for converting into a multi-bit signal, an operation means (multiplier 3) for performing the above-mentioned arbitrary processing on the converted multi-bit signal, and the operation-processed signal is subjected to the ΣΔ modulation again. And a means (switch 8) for switching the reconverted signal to the original ΣΔ-modulated signal (delay circuit 9) and outputting the signal (switch 8). ΣΔ
It is a signal processing device.

According to a second means of the present invention, in the ΣΔ signal processing apparatus according to the first means, the ΣΔ signal processing apparatus is such that a fade process, an equalize process or a filter process is performed in the arbitrary process. Is.

According to a third means of the present invention, in the ΣΔ signal processing apparatus according to the first means, a plurality of the ΣΔ modulated signals are supplied (input terminals 1A and 1B) and the plurality of ΣΔ modulated signals are supplied. Means for converting the obtained signals into multi-bit signals using low-pass filters (2A, 2B), and arithmetic means (multiplication) for mutually performing the above-mentioned arbitrary processing on these converted multi-bit signals. 3A, 3B, and adder 3C), a means (ΣΔ modulator 7) for re-converting these arithmetically processed signals into the ΣΔ-modulated signal again, and the re-converted signal as an arbitrary original signal. The ΣΔ modulated signal (delay circuits 9A and 9B)
And a means for switching and outputting (switch 8).

A fourth means according to the present invention is the ΣΔ signal processing apparatus according to the third means, wherein the mixing processing or the crossfade processing is performed in the arbitrary processing. .

A fifth means according to the present invention is the ΣΔ signal processing apparatus according to any one of the first to fourth means, wherein the reconverted signal and the original ΣΔ modulated signal are switched. The ΣΔ signal processing device is configured to perform an interpolation process (interpolation circuit 11) for eliminating a step difference at the time of switching when outputting.

[0024]

According to this, in performing arbitrary processing on the ΣΔ-modulated signal, a means for converting the ΣΔ-modulated signal into a multi-bit signal by using a low-pass filter and a means for converting the converted multi-bit signal. And an arithmetic means for performing an arbitrary process by the Σ
Arbitrary processing for the converted multi-bit signal by having means for reconverting to a Δ-modulated signal and means for switching this reconverted signal to the original ΣΔ-modulated signal and outputting In addition to being able to perform, the original ΣΔ-modulated signal is taken out when the processing is not performed, so that the ΣΔ-modulated signal of the ΣΔ-modulated signal can be Processing can be realized.

Further, by this, it is possible to perform a fade process, an equalize process, a filter process, etc. on the ΣΔ modulated signal.

Further, a plurality of .SIGMA..DELTA. Modulated signals are supplied, and a means for converting each of the .SIGMA..DELTA. Modulated signals into a multi-bit signal by using a low-pass filter, and to these converted multi-bit signals. On the other hand, an arithmetic means for mutually performing arbitrary processing, a means for reconverting these arithmetically processed signals into a ΣΔ-modulated signal again, and an arbitrary original ΣΔ-modulated signal for this reconverted signal. Signal and a means for switching and outputting the signal, it is possible to perform any processing on the converted multi-bit signal, and when the processing is not performed, the original ΣΔ-modulated signal is extracted. Therefore, the processing of the ΣΔ-modulated signal can be realized without killing the characteristics of the ΣΔ-modulated signal at the normal time.

Further, by this, it is possible to perform a mixing process, a crossfade process, etc. of the ΣΔ modulated signal.

Further, when the re-converted signal and the original ΣΔ-modulated signal are switched and output, interpolation processing for eliminating the step at the time of switching is performed, so that a better ΣΔ-modulated signal is obtained. Can be processed.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the configuration of an embodiment of a ΣΔ signal processing apparatus according to the present invention. In FIG. 1, the 1-bit ΣΔ signal supplied to the input terminal 1 is supplied to the low-pass filter 2 and converted into a 16-bit multi-bit digital audio signal, for example. The converted digital audio signal is supplied to the multiplier 3.

Further, for example, a control signal designating a fade start timing and a speed is supplied to the control signal input terminal 4, and this control signal is supplied to the control circuit 5 to generate an arbitrary fade signal. Then, by supplying the fade signal to the coefficient generator 6, for example, a coefficient for gradually lowering the level of the audio signal and muting it to the zero level is generated, and this coefficient is supplied to the multiplier 3.

As a result, with respect to the digital audio signal from the low-pass filter 2, a signal whose level is controlled by the coefficient from the coefficient generator 6 is extracted from the multiplier 3. Further, this signal is supplied to the ΣΔ modulator 7 and again converted into, for example, a 1-bit ΣΔ signal, and the reconverted digital audio signal is supplied to the fixed contact B of the switch 8.

Further, the 1-bit ΣΔ signal supplied to the input terminal 1 is supplied to the delay circuit 9. The delay circuit 9 includes the low-pass filters 2 to ΣΔ described above.
A delay time corresponding to the processing time of the modulator 7 is provided.
The digital audio signal from the delay circuit 9 is supplied to the fixed contact A of the switch 8. The switch 8 is controlled by the control circuit 5, and the signal switched by the switch 8 is taken out to the output terminal 10.

Therefore, in this apparatus, for example, when performing the fade processing of the ΣΔ signal, the ΣΔ signal is supplied to the digital signal input terminal 1 and the control signal input terminal 4 specifies the fade start timing and speed. A control signal for controlling is supplied.

Until the fade start timing designated by the control signal, the coefficient generator 6 generates a coefficient of "1", and the multiplier 3 outputs the same signal as the input. Be done. Therefore, this signal is the ΣΔ modulator 7
In the case of being re-converted by, the digital audio signal which is almost the same as the original ΣΔ signal is taken out except for the band limited by the low pass filter 2.

On the other hand, in the switch 8, the delay circuit 9 side is initially selected. Therefore, for example, the 1-bit ΣΔ signal supplied to the input terminal 1 is taken out after being delayed by an amount corresponding to the processing time of the low-pass filter 2 to the ΣΔ modulator 7.

The switch 8 is switched to the ΣΔ modulator 7 side immediately before the fade start timing designated by the control signal. As a result, the output terminal 10
After the switch 8 is switched, a digital audio signal whose audio signal level is controlled by the multiplier 3 comes out.

That is, the level of the digital audio signal from the low-pass filter 2 is gradually reduced from the multiplier 3 to a zero level, for example, from the timing specified by the control signal at a specified speed. The muted digital audio signal is taken out, and this signal is reconverted into a 1-bit ΣΔ signal by the ΣΔ modulator 7 and taken out to the output terminal 10.

In this way, the signal of which the level of the digital audio signal from the input terminal 1 is gradually lowered and muted to the zero level is taken out to the output terminal 10 and so-called fade-out processing is performed. Therefore, according to this apparatus, processing such as fade can be performed in the same manner as the conventional method.

In the above process, the fade-in process of gradually increasing the level of the digital audio signal from the zero level can be performed by reversing the order of generation of the coefficients. In this case, the switch 8 is initially ΣΔ.
The modulator 7 side is selected and switched to the delay circuit 9 side immediately after the fade end timing designated by the control signal.

Thus, according to this apparatus, when the ΣΔ-modulated signal (input terminal 1) is subjected to arbitrary processing, Σ
Means for converting the Δ-modulated signal into a multi-bit signal using the low-pass filter (2), operation means (multiplier 3) for performing arbitrary processing on the converted multi-bit signal, and The processed signal is re-calculated by ΣΔ
Means for reconverting to a modulated signal (ΣΔ modulator 7),
Means (switch 8) for switching and outputting the re-converted signal with the original ΣΔ-modulated signal (delay circuit 9)
By having and, it is possible to perform arbitrary processing on the converted multi-bit signal, and since the original ΣΔ-modulated signal is extracted when processing is not performed, The processing of the ΣΔ-modulated signal can be realized without destroying the characteristics of the ΣΔ-modulated signal.

That is, when this apparatus is used, the signal processed by the ΣΔ modulator 7 is selected from the low-pass filter 2 only when the processing is performed, and only delayed by the delay circuit 9 when the processing is not performed. Signal is taken out. Therefore, the original characteristics of the ΣΔ signal can be obtained as the characteristics of the signal while the processing is not performed, and the processing can be performed without killing the characteristics such as wide band and high dynamic range.

Note that this device is not limited to the above-described fade processing, but can also perform, for example, equalization processing of the ΣΔ signal and filter processing by changing the calculation contents of the multiplier 3.

By the way, in the above apparatus, since the ΣΔ signal is composed of a small number of bits (for example, 1 bit),
If there is a level change or the like in the audio signal at the time of signal switching, this may cause a large noise. Therefore, in the above-described embodiment, the level change is minimized by switching the switch 8 immediately before the fade-out start timing when the coefficient becomes “1” or immediately after the fade-in end timing. is there.

This switching is performed by detecting the time when the patterns of the two signals to be switched coincide with each other, as proposed by the applicant of the present application (FIG. 10 of Japanese Patent Application No. 6-33822). You may control so that switching may be performed. In this case, it is also conceivable to perform feedback control on, for example, the coefficient generator 6 so that the patterns of the two signals may match.

Alternatively, as shown in FIG. 2, an interpolator 11 may be provided after the switch 8 so that the signals between the two signals to be switched are interpolated by, for example, linear interpolation. As such an interpolator (method and apparatus), the applicant of the present application has previously proposed Japanese Patent Application No. 6-299814.

In other words, the invention of this earlier application has an error Σ
The Δ signal is interpolated in the form of a ΣΔ signal in an attempt to restore it to data that has no audible problem. Therefore, in the present invention, both signals to be switched are regarded as signals immediately before and after the error, and the signal between them is restored with data that is audibly no problem to switch the signals without noise. be able to.

The outline of the invention of this prior application will be described below. In the invention of this prior application, an error ΣΔ signal is predicted using a filter, and the error is interpolated using this predicted ΣΔ signal. That is, for example, if the coefficient is c0,
If the ΣΔ signal of the data sequence of b0, b1, b2 ,,,, bm is input to the n-tap FIR low-pass filter of c1, c2 ,,,, cn-1, the output signal Yn of the filter is It becomes like the following formula. Yn = c0 * b0 + c1 * b1 + c2 * b2 + ,,,,, cn-1 * bn-1

If an error occurs in 4 bits of (b0, b1, b2, b3) of the ΣΔ signal having a data word length of 1 bit, the output of the FIR filter is as follows. Yn = (c0 * b0 + c1 * b1 + c2 * b2 + c3 * b3) + (c4 * b4 + ,,,,, + cn-1 * bn-1) (1)

In this equation (1), (c0 * b0 + c1 * b
1 + c2 * b2 + c3 * b3) cannot be calculated because the data was lost, but (c4 * b4
+ ,,,,, + cn-1 * bn-1) can be calculated because the values of the data b4 to bn-1 are known. This is A0
Then it becomes as follows. Y0 = (c0 * b0 + c1 * b1 + c2 * b2 + c3 * b3) + A0

Similarly, the outputs of the filters after 1 sample, 2 samples, and 3 samples are as follows. Y1 = (c1 * b0 + c2 * b1 + c3 * b2 + c4 * b3) + A1 Y2 = (c2 * b0 + c3 * b1 + c4 * b2 + c5 * b3) + A2 Y3 = (c3 * b0 + c4 * b1 + c6 * b1 + c6 * b1 + c5 * c6 * b2 + A3

On the other hand, for the value of Yn, the value immediately before the error is A,
If the value immediately after the error is B and the interval between A and B is N samples, it can be obtained from Yn = A + n * (B−A) / N (2) by the formula of linear interpolation. Similarly to the above, the following equation is obtained. (C0 * b0 + c1 * b1 + c2 * b2 + c3 * b3) + A0 = Y0 (c1 * b0 + c2 * b1 + c3 * b2 + c4 * b3) + A1 = Y1 (c2 * b0 + c3 * b1 + c4 * b3 + c5 * b2 + c5 * c2 * c3 * b3 Y2 (c3 * b0 + c4 * b1 + c5 * b2 + c6 * b3) + A3 = Y3 (3) The value of the lost data can be estimated by solving this simultaneous equation (3) for b0 to b3.

In reality, however, the data word length of the data bn is 1 bit, so that its value is only 1 or -1. On the other hand, the solution of simultaneous cubic formula (3) is 1 or -1.
Any value other than. Therefore, even if the value of the data is determined to be 1 or -1 from the solution of the equation by paying attention to the sign of the solution, the interpolated ΣΔ signal may include a very large level of noise.

On the other hand, noting that the data bn takes only one value of 1 or -1, (c0 * b0 + c1 * b1 + c2 * b2 + c3 * b3) on the left side of the equation (3).
) Takes only 16 values in total due to the combination of 1 or -1 of the four data b0 to b3. So this one
All six values are calculated in advance and the left side of equation (3) (c0 * b0 + c1 * b1 + c2 * b2 + c3 * b3)
The value of + A0 closest to Y0 should be found out of these 16 values.

As an actual example, using a 29-tap FIR filter as shown in Table 1 and FIG. 3, 4-bit data (b
Consider the case where 0, b1, b2, b3) causes an error and interpolates the error.

[0055]

[Table 1]

[0056]

[Table 2]

The data in Table 2 is an example of a sine wave with a sampling frequency of 2.822 MHz, a signal frequency of 1 kHz, and an amplitude of -50 dB from full scale. Further, when the filter calculation of the equation (3) is performed, it does not matter which phase of the FIR filter the data in which an error has occurred, but it is placed in the center of the FIR filter as shown in FIG.

Here, if the term that cannot be filter-calculated due to an error is Bn, then Bn = c12 * b0 + c13 * b1 + c14 * b2 + c15 * b3 If the remaining error-free term is A0, A0 = c0 * b (-12) + c1 * b (-11) + ,,,, + c10 * b (-2) + c11 * b (-1) + c16 * b4 + c17 * b5 + ,,,,, + C27 * b15 + c28 * b16, and the formula (3) is eventually Bn + A0 = Y0 (4).

On the other hand, b0 to b3 are 1 or-, respectively.
When calculating the value of Bn in the case of 16 when the value of 1 is taken, when b0 = 1, b1 = 1, b2 = 1, b3 = 1 Bn ＝ B0 = 13331 b0 ＝ -1, b1 = 1, b2 = 1 , b3 = 1, Bn = B1 = 701 b0 = 1, b1 = -1, b2 = 1, b3 = 1, Bn = B2 = 659 b0 = -1, b1 = -1, b2 = 1, b3 = When 1 Bn = B3 = 29 b0 = 1, b1 = 1, b2 = 1, b3 = 1 Bn = B4 = 643 b0 = -1, b1 = 1, b2 = 1, b3 = 1 Bn = B5 = 13 b0 = 1, b1 = -1, b2 = -1, b3 = 1, Bn = B6 = -29 b0 = -1, b1 = -1, b2 = -1, b3 = 1 Bn = B7 = -659 b0 = 1, b1 = 1, b2 = 1, b3 = -1 Bn = B8 = 659 b0 = -1, b1 = 1, b2 = 1, b3 = -1 Bn = B9 = 29 b0 = 1, b1 = -1, b2 = 1, b3 = -1, Bn = B10 = -13 b0 = -1, b1 = -1, b2 = 1, b3 = -1, Bn = B11 = -643 b0 = 1, b1 = 1, b2 = -1, b3 When -1 Bn = B12 = -29 b0 = -1, b1 = 1, b2 = -1, b3 = -1 When Bn = B13 = -659 b0 = 1, b1 = -1, b2 = -1, When b3 = -1, Bn = B14 = -701 b0 = -1, b1 = -1, b2 = -1, b3 = -1, and Bn = B15 = -1331.

Next, the filter calculation is performed on the data portion where no error has occurred. A0 = -3.0 Also, the value A of the filter output immediately before the data in which the error occurred is A = c0 * b (-29) + c1 * b (-28) + ,,,,,, + c27 * b (-2) + c28 * b (-1) = 12.0 Filter output value B immediately after the data that caused an error
Is B = c0 * b4 + c1 * b5 + ,,,,, + c27 * b31 + c28 * b32 = 0.0 N = 29 + 4 = 33 n = 14 Therefore, using the equation (2), Y0 = A + n * (B- A) /N=12.0+14* (0.0-12.0) /33=6.9.

Therefore, in each case of Bn, when Bn = B0, Bn + A0 = 1328, Bn = B1, Bn + A0 = 698, Bn = B2, Bn + A0 = 656, Bn = B3, Bn + Bn = 26. When Bn + A0 = 640 Bn = B5 When Bn + A0 = 10 Bn = B6 When Bn + A0 = -32 Bn = B7 When Bn + A0 = -662 Bn = Bn = Bn = Bn = A0 = 657 When + A0 = 26 Bn = B10 Bn + A0 = -16 Bn = B11 Bn + A0 = -646 Bn = B12 Bn + A0 = -32 Bn = B13 Bn + A0 = -662 Bn Bn + B14 + = -704 When Bn = B15, Bn + A0 = -1334.

That is, B5 + A0 = 10, which is the value closest to Y0 = 6.9 of the interpolation target value, that is, B5: (b0 = -1, b1 = 1, b2 = -1, b3 = 1) The data will be Note that in this example, the interpolated data matches the original data in Table 2.

In this way, the digital signal digitized with an arbitrary small number of bits and containing the error portion is supplied, and the error portion of the digital signal is set as an arbitrary position, and the data excluding the error portion is subjected to an arbitrary digital filter. By using the value obtained by supplying to and the value obtained by supplying all possible interpolation data of the error part to any position of the digital filter, the interpolation data of the error part is obtained. Interpolation data similar to the original data can be obtained, and good digital signal interpolation can be performed.

Further, the sum of the value obtained by supplying the data excluding the error part of the digital signal to the digital filter and the value obtained by supplying all the interpolation data that the error part can take to the digital filter is obtained, The value of this sum is determined from the value obtained by supplying the digital signal data immediately before and immediately after the error portion to the digital filter and calculating the value approximate to the value obtained by calculation based on an arbitrary interpolation formula, By obtaining the interpolation data corresponding to the determined value, it is possible to reduce the amount of calculation and perform better digital signal interpolation.

In order to carry out this method, for example, a structure as shown in FIG. 5 can be used. That is, in FIG. 5, 10 is a data input terminal to which a digital audio signal is supplied, and an input data signal from the data input terminal 10 is supplied to the data selector 30 through the memory 20. Further, the data signal from the memory 20 is an n-tap FIR type low-pass characteristic digital filter 40 having, for example, the above-mentioned coefficients c0, c1, c2, ..., Cn-1.
Is supplied to.

Reference numeral 50 is an error detection signal input terminal to which an error detection signal indicating whether or not the digital audio signal supplied to the data input terminal 1 is correct is supplied. A predetermined period before and after the switching is determined to be an error. The detection signal from the error detection signal input terminal 50 is supplied to the control circuit 60. The control signal from the control circuit 60 is supplied to the memory 20, the data selector 30, and the ALU circuit 70 described later.

When an error is detected in the digital audio signal supplied to the data input terminal 10 and the error detection signal is supplied to the error detection signal input terminal 50, the control signal from the control circuit 60 is first supplied to the memory 20. Then, the data immediately before the data in which the error occurred is read and supplied to the digital filter 40. As a result, the above-mentioned value A is taken out from the digital filter 40, and this value A is stored in the register 701 of the ALU circuit 70.

Next, the control signal from the control circuit 60 is supplied to the memory 20, and the data immediately after the data in which the error has occurred is read out and supplied to the digital filter 40. As a result, the above-mentioned value B is taken out from the digital filter 40, and this value B is taken out by the ALU circuit 70.
Stored in the register 702 of Then, using the values A and B, the value Y0 is taken out by the operation circuit 703 performing the operation according to the equation (2).

Further, the control signal from the control circuit 60 is supplied to the memory 20, and the data before and after the errored data is read out and supplied to the digital filter 40, for example, as shown in FIG. As a result, the above-mentioned value A0 is taken out from the digital filter 40, and this value A0 is stored in the register 704 of the ALU circuit 70.

The value of Bn described above is stored in the memory 705 of the ALU circuit 70, and this value Bn is sequentially read out and supplied to the adder 706 to be added to the above value A0. This added value is supplied to the determination circuit 707. Then, in this discriminating circuit 707, the value Y from the above-mentioned arithmetic circuit 703
The value Bn that is closest to these values is discriminated and the interpolated data is formed by the discriminated value Bn.

The value Bn is calculated in advance according to the configuration (coefficient) of the digital filter 4 used and the position where the error portion is set, and this value is stored as a table. Further, the internal configuration of the ALU circuit 70 is shown by dividing the functions into blocks in the figure, and is actually configured by software.

Further, the interpolation data from the ALU circuit 70 is supplied to the data selector 30, and the data selector 30 is controlled by the control signal from the control circuit 60. As a result, the interpolation data is selected from the ALU circuit 70 during the period in which the error detection signal is supplied to the error detection signal input terminal 50, and the interpolated data is taken out to the data output terminal 80.

In this way, the digital signal digitized with an arbitrary small number of bits and containing the error portion is supplied, and the error portion of the digital signal is set as an arbitrary position, and the data excluding the error portion is subjected to an arbitrary digital filter. By using the value obtained by supplying to and the value obtained by supplying all possible interpolation data of the error part to any position of the digital filter, the interpolation data of the error part is obtained. Interpolation data similar to the original data can be obtained, and good digital signal interpolation can be performed.

In addition to the above, 1 that can be taken from B0 to B15
The 6 values are rearranged in descending order, and this is set as B'0 to B'15, and is approximated to a straight line (interpolation straight line) with slope p and y intercept q using the method of least squares. Substituting this B'into Bn in the equation (4) by setting B '= px + q, px + q + A0 = Y0∴x = (Y0-A0-q) / p (5) is obtained, and the equation (5) is obtained. It is also possible to find the lost data from the nearest integer value to the solution.

Alternatively, by using the differential filter, as in the case of the interpolation by the above FIR filter, (5)
The formula corresponding to the formula can be used to interpolate the erroneous data. Further, by using the point symmetry of the coefficient of the difference filter, it is possible to perform the interpolation processing at the two positions that are point-symmetrical to each other in the same manner as the above method.

As an actual example of interpolation in this way, a sine wave with a sampling frequency of 2.822 MHz, a signal frequency of 1 kHz, and an amplitude of -50 dB from full scale is faded, and then a low-pass filter is used to perform conventional digital audio. The results of the processing when converted into a signal are shown in FIGS. 6 is a waveform when switching is performed using the apparatus of FIG. 1, and FIG. 7 is a waveform when interpolation is performed after switching using the apparatus of FIG. The filter used in this example is a FIR low-pass filter, which is a moving average filter in which 64 taps are stacked in four stages.

Therefore, as is apparent from FIGS. 6 and 7, the noise generation is reduced by the interpolation, especially at the switching time at the fade-out (the left side of the drawing). However, even in FIG. 6, the noise level is not so large that it can be put to practical use.

Thus, according to the above apparatus, when the re-converted signal and the original ΣΔ-modulated signal are switched and output, the interpolation processing for eliminating the step difference at the time of switching is more preferable. The ΣΔ modulated signal can be processed.

Further, FIG. 8 shows the configuration of another embodiment of the ΣΔ signal processing apparatus according to the present invention. In this FIG.
Each of the input terminals 1A and 1B has, for example, a 1-bit ΣΔ
Signal is supplied. The signals from these input terminals 1A and 1B are supplied to the low-pass filters 2A and 2B, respectively, and are converted into, for example, 16-bit multi-bit digital audio signals. The converted digital audio signals are supplied to the multipliers 3A and 3B, respectively.

Further, for example, a control signal for designating the start and end timings and speed of the crossfade is supplied to the control signal input terminal 4, and this control signal is supplied to the control circuit 5 to generate an arbitrary crossfade signal. . Then, by supplying the crossfade signal to the coefficient generator 6, for example, a coefficient for gradually decreasing the level of one audio signal to zero level and gradually increasing the level of the other audio signal from zero level is obtained. Is generated.

These coefficients are supplied to the multipliers 3A and 3B, respectively. As a result, for example, a digital signal whose audio signal level is gradually decreased to zero level is taken out from the multiplier 3A, and a digital signal whose audio signal level is gradually increased from zero level is extracted from the multiplier 3B. Taken out. These digital signals are added by the adder 3C, and this added signal is supplied to the ΣΔ modulator 7 and reconverted into a 1-bit ΣΔ signal, for example. Then, the re-converted digital audio signal is supplied to the fixed contact B of the switch 8.

Further, for example, the 1-bit ΣΔ signal supplied to the input terminals 1A and 1B is supplied to the delay circuit 9 respectively.
It is supplied to A and 9B. The delay circuits 9A and 9B are provided with a delay time corresponding to the processing time of the low pass filters 2A and 2B to the ΣΔ modulator 7. Digital audio signals from the delay circuits 9A and 9B are supplied to fixed contacts A and C of the switch 8, respectively. The switch 8 is controlled by the control circuit 5, and the signal switched by the switch 8 is taken out to the output terminal 10.

Therefore, in this device, for example, two Σ
When performing the cross-fade processing of the Δ signal, these two ΣΔ signals are respectively input to the digital signal input terminals 1A and 1B.
In addition to the above, the control signal input terminal 4 is supplied with a control signal for designating the start and end timing and speed of the crossfade.

Here, until the fade start timing designated by the control signal, the coefficient generator 6 generates the coefficients "1" and "0", for example, the input to the output of the multiplier 3A. The same signal as is extracted. Therefore, when this signal is reconverted by the ΣΔ modulator 7, a digital audio signal that is almost the same as the original ΣΔ signal is extracted, except that the band is limited by the low-pass filter 2A.

On the other hand, in the switch 8, the delay circuit 9A side (contact A) is initially selected. Therefore, output terminal 1
0 is, for example, a 1-bit Σ supplied to the input terminal 1A.
The Δ signal is extracted with a delay corresponding to the processing time of the low pass filter 2A to the ΣΔ modulator 7.

The switch 8 is switched to the ΣΔ modulator 7 side (contact B) immediately before the fade start timing designated by the control signal. As a result, after the switch 8 is switched, a digital audio signal whose audio signal level is controlled by the multipliers 3A and 3B is taken out from the output terminal 10.

Further, after the fade end timing designated by the control signal, the coefficient generator 6 outputs "0".
And a coefficient of "1" are generated, and for example, the same signal as the input is taken out from the output of the multiplier 3B. Therefore, this signal is Σ
When the signal is reconverted by the Δ modulator 7, the original ΣΔ is removed except that the band is limited by the low-pass filter 2B.
A digital audio signal that is almost the same as the signal is extracted.

Then, the switch 8 is switched to the delay circuit 9B side (contact C) immediately after the end timing of the fade designated by the control signal. As a result, the 1-bit ΣΔ signal supplied to the input terminal 1B is extracted at the output terminal 10 with a delay corresponding to the processing time of the low-pass filter 2B to the ΣΔ modulator 7.

That is, from the multipliers 3A, 3B, one of the digital audio signals from the low-pass filters 2A, 2B is changed in the level of the audio signal from the timing specified by the control signal to the other at a specified speed. A digital audio signal that is gradually lowered and muted to zero level and the other is gradually raised from zero level is taken out, and this signal is reconverted into a 1-bit ΣΔ signal by the ΣΔ modulator 7 and output. It is taken out to the terminal 10.

Thus, the output terminal 10 has the input terminal 1A
The level of the digital audio signal from is gradually reduced and muted to zero level, and the signal from which the level of the digital audio signal from the input terminal 1B is gradually reduced from the zero level is taken out. Is done. Therefore, according to this apparatus, it is possible to perform processing such as crossfade by the same method as the conventional method.

Thus, according to the above apparatus, a plurality of ΣΔ
Modulated signals are supplied (input terminals 1A, 1B), and means for converting a plurality of ΣΔ-modulated signals into multi-bit signals by using low-pass filters (2A, 2B), respectively, and means for converting these signals. Arithmetic means (multiplier 3) for mutually performing arbitrary processing on multi-bit signals
A, 3B, adder 3C), a means (ΣΔ modulator 7) for re-converting the arithmetically processed signals into a ΣΔ-modulated signal again, and an arbitrary original ΣΔ-modulation for the re-converted signals. By including the generated signal (delay circuits 9A and 9B) and means (switch 8) for switching and outputting,
Arbitrary processing can be performed on the converted multi-bit signal, and the original Σ
Since the Δ-modulated signal is taken out, Σ
The processing of the ΣΔ-modulated signal can be realized without destroying the characteristics of the Δ-modulated signal.

That is, when this apparatus is used, the signals processed by the ΣΔ modulator 7 are selected from the low-pass filters 2A, 2B only when the processing is performed, and the delay circuits 9A, 9B are selected when the processing is not performed. Only the delayed signal has been retrieved. Therefore, the original characteristics of the ΣΔ signal can be obtained as the characteristics of the signal while the processing is not performed, and the processing can be performed without killing the characteristics such as wide band and high dynamic range.

This device is not limited to the above-mentioned cross-fade processing, but can change the arithmetic contents of the multipliers 3A and 3B to perform, for example, a mixing processing of a plurality of ΣΔ signals and other processing.

Therefore, by using the sigma-delta signal processing apparatus of the present invention, it becomes possible to favorably perform processing such as fade processing on the ΣΔ signal.
Recording and reproduction (transmission) of a signal to a magnetic medium or the like can be enabled.

[0095]

According to the present invention, in performing arbitrary processing on a ΣΔ-modulated signal, a means for converting the ΣΔ-modulated signal into a multi-bit signal using a low-pass filter, and the converted multi-bit signal. Arithmetic means for performing arbitrary processing on the signal, means for reconverting the arithmetically processed signal into a ΣΔ-modulated signal again, and the original ΣΔ-modulated signal for the reconverted signal By including means for switching and outputting, it is possible to perform arbitrary processing on the converted multi-bit signal, and when the processing is not performed, the original ΣΔ modulated signal is taken out. Therefore, the processing of the ΣΔ modulated signal can be realized without killing the characteristics of the ΣΔ modulated signal in the normal state.

Further, as a result, it becomes possible to perform a fade process, an equalize process, a filter process, etc. on the ΣΔ modulated signal.

Further, a plurality of .SIGMA..DELTA. Modulated signals are supplied, and a means for converting each of the .SIGMA..DELTA. Modulated signals into a multi-bit signal by using a low-pass filter, and to these converted multi-bit signals. On the other hand, an arithmetic means for mutually performing arbitrary processing, a means for reconverting these arithmetically processed signals into a ΣΔ-modulated signal again, and an arbitrary original ΣΔ-modulated signal for this reconverted signal. Signal and a means for switching and outputting the signal, it is possible to perform any processing on the converted multi-bit signal, and when the processing is not performed, the original ΣΔ-modulated signal is extracted. Therefore, the processing of the ΣΔ-modulated signal can be realized without killing the characteristics of the ΣΔ-modulated signal at the normal time.

Further, as a result, it becomes possible to perform the mixing process, the crossfade process, etc. of the ΣΔ modulated signal.

Furthermore, when the re-converted signal and the original ΣΔ-modulated signal are switched and output, an interpolation process for eliminating a step at the time of switching is performed, so that a better ΣΔ-modulated signal is obtained. You can now process.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a processing apparatus for a sigma delta signal according to the present invention.

FIG. 2 is a configuration diagram of another example of a processing apparatus for a sigma delta signal according to the present invention.

FIG. 3 is a diagram for explaining an interpolation method previously proposed by the applicant of the present application.

FIG. 4 is a diagram for explaining an interpolation method previously proposed by the applicant of the present application.

FIG. 5 is a configuration diagram of an interpolation device previously proposed by the applicant of the present application.

FIG. 6 is a diagram showing a waveform obtained by processing a 1-bit ΣΔ signal by the apparatus of FIG.

7 is a diagram showing a waveform obtained by processing a 1-bit ΣΔ signal by the device of FIG. 2.

FIG. 8 is a configuration diagram of still another example of the sigma-delta signal processing device according to the present invention.

FIG. 9 is a configuration diagram for explaining ΣΔ modulation.

FIG. 10 is a block diagram of a conventional digital signal processing apparatus.

FIG. 11 is a configuration diagram of a conventional digital signal processing device.

[Explanation of symbols]

 1 Input Terminal 2 Low Pass Filter 3 Multiplier 4 Control Signal Input Terminal 5 Control Circuit 6 Coefficient Generator 7 ΣΔ Modulator 8 Switch 9 Delay Circuit 10 Output Terminal 11 Interpolator

Claims (5)

[Claims] 1. When performing arbitrary processing on a sigma-delta modulated signal, a means for converting the sigma-delta modulated signal into a multi-bit signal using a low-pass filter, and a means for converting the converted multi-bit signal. Calculating means for performing the above arbitrary processing, means for re-converting the processed signal into the sigma-delta modulated signal again, and the re-converted signal which has been originally processed for the sigma-delta modulation. An apparatus for processing a sigma-delta signal, comprising a signal and a means for switching and outputting. 2. The sigma-delta signal processing device according to claim 1, wherein a fade process, an equalize process, or a filter process is performed in the arbitrary process. 3. The sigma-delta signal processing device according to claim 1, wherein a plurality of said sigma-delta modulated signals are supplied, and a multi-pass filter is provided for each of said plurality of sigma-delta modulated signals using a low-pass filter. A means for converting into a bit signal, an operation means for mutually performing the above-mentioned arbitrary processing with respect to these converted multi-bit signals, and these operation-processed signals are again converted into the sigma-delta modulated signals. An apparatus for processing a sigma-delta signal, comprising means for re-converting and means for switching the re-converted signal to an arbitrary original sigma-delta modulated signal for output. 4. The sigma-delta signal processing device according to claim 3, wherein a mix process or a crossfade process is performed in the arbitrary process. 5. The sigma-delta signal processing device according to claim 1, wherein the re-converted signal and the original sigma-delta modulated signal are switched and output. An apparatus for processing a sigma-delta signal, which is adapted to perform an interpolation process to eliminate a time step.