JPH08172353A - Digital pll circuit - Google Patents

Abstract

PURPOSE: To optionally set up filter characteristics from the external, to enable a user to set up characteristics in accordance with specifications, to provide this digital PLL circuit with a synchronous state displaying function, and to easily execute characteristic evaluation. CONSTITUTION: The digital PLL circuit is provided with an edge detecting circuit 1 for detecting the edge of a reference input signgal, a phase comparing circuit 2 for comparing the phase of an edge pulse with that of a self-return pulse 9 and outputting detection signals in respective ranges of phase synchronism, delay and advance and a filter 3 for up/down counting the detection signals in the delay and advance ranges. The circuit is also provided with a selector 4 for switching and setting up the number of stages of the filter 3 in accordance with a filter stage setting signal 12 applied from the external, a phase shifting circuit 5 for outputting the pulse of a phase shift request signal 101 outputted from the filter 3, a frequency dividing circuit 7 for controlling the frequency dividing ratio of a reference clock 101 by the phase shift pulse, and a phase state detecting circuit 6 for inputting a detection signal 102 in the synchronizing range with the signal 101 and outputting a synchronous state display signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase locked loop (hereinafter referred to as DPLL) circuit used in an apparatus composed of integrated circuits such as IC and LSI, and discrete parts.

[0002]

2. Description of the Related Art Conventionally, a DPLLIC that has been used has a fixed filter characteristic, has no characteristic variable function, and has no synchronization state display function.

[0003]

As described above, the conventional D
In the case where the PLL circuit is integrated into an IC, the filter characteristic is fixed. Therefore, the user has to search for a DPLLIC that meets the specifications or change the specifications to match the characteristics of the IC.

Further, the DPLL has a characteristic that the behavior looks the same whether it is in synchronization or out of synchronization. For this reason, since the conventional DPLL does not have a function of displaying the synchronized state, it is difficult to evaluate the characteristics because it is not known whether the synchronized state or not.

An object of the present invention is to arbitrarily set a filter characteristic from the outside so that a user can set the characteristic in accordance with the specifications, to enhance versatility and usability in the case of an IC, and also to synchronize. It has a function to display the status, so that the lock range, jitter characteristics, etc.
It is to facilitate the characteristic evaluation of L.

[0006]

The above object is achieved by providing a selector for arbitrarily switching the number of stages of filters of a digital PLL circuit by a filter stage number setting signal from the outside.

Further, the above object is to provide a phase state detection circuit for inputting the phase shift request signal output from the filter of the digital PLL circuit and the detection signal of the synchronization range from the phase comparison circuit and outputting the synchronization state display signal. Achieved by

[0008]

According to the above means, since the filter circuit is provided with a selector for switching the number of filter stages in accordance with the external filter stage number setting signal, the number of filter stages can be arbitrarily switched and set according to the characteristics.

Further, the phase state detection circuit can display whether the phase is in sync or out of sync with the phase request signal and the sync state display signal, so that it can be easily confirmed and the characteristics can be easily evaluated.

[0010]

EXAMPLES The present invention will be described below with reference to examples. FIG.
FIG. 3 is a circuit configuration diagram in the case of being adapted to a DPLL using a random walk filter in an embodiment of the present invention.

In the figure, 10 is an operation clock, 11 is a reference input signal, 12 is a filter stage number setting signal, and 13 is a synchronization range setting signal. The operation clock 10 needs a frequency several times faster than the reference input signal 11, and is set to 32 times the frequency in this embodiment.

The edge detection circuit 1 that receives the reference input signal 11 detects the rising edge of the reference input signal 11 and outputs it to the phase comparison circuit 2 as a pulse signal of one pulse width of the clock 10. The phase comparison circuit 2 compares the phase of the edge pulse of the input reference signal with the phase of the self-folding signal 9 to determine whether the phase of the folding signal is in synchronization with the reference signal, delayed or advanced. The result is output to the filter circuit 3 and the phase state detection circuit 6 as a pulse signal having a 1-pulse width of the clock 10.

The filter circuit 3 is provided with a random walk type filter using a 32-way bidirectional counter. Although this filter circuit itself is a known technique, the number of filter stages is usually fixed. However, in this embodiment, the selector circuit 4 is provided after the counter so that the number of filter stages can be arbitrarily switched and set from the outside. To set the number of filter stages, the selector circuit 4 is switched by the filter stage number setting signal 12, and this is switched to the stage number set value shown in FIG. 2, whereby the characteristics of the DPLL itself such as the lock range and the jitter characteristic can be changed. For example, in terms of lock range, when the filter range number setting value is set to 8 and the lock range is taken as a reference, maximum 8 times to minimum 1
It can be changed up to / 8.

The bidirectional counter of the filter circuit 3 counts up the signal in the delay range from the phase comparison circuit 2 to decrease the count value and counts the signal in the lead range to increase the count value. In this way, the count value is increased or decreased according to the phase comparison result, and the count value is canceled by the delay or advance. However, when the same phase comparison result continues, when the value set by the selector circuit 4 is reached, the signal output is performed. To do. For example, in FIG. 2, when the number of stages setting value is 8, the selection count value when the phase delay is 6 and the selection count value when the phase lead is 23 are output.

The output of the filter circuit 3 having the number of stages set by the selector circuit 4 is input to the frequency dividing circuit 7 via the phase shift circuit 5 and the frequency dividing ratio is controlled to output an output pulse when the preset value and the input value match. . In this way, the phase is shifted,
The clock signal synchronized with the reference input signal is output from the frequency dividing circuit 7 to the outside.

Next, the phase state display circuit 6 will be described. FIG. 3 shows a specific example of the phase state display circuit 6. DPL
Focusing on the fact that the phase correction is completed by one phase shift when L is in synchronization, and two or more phase shifts are required when out of synchronization, the phase shift request signal 101 from the filter circuit 4
Then, the synchronization state is detected using the detection signal 102 of the synchronization range from the phase comparison circuit 2.

In the figure, a phase shift request signal 101 and a synchronization range detection signal 102 are input to AND gates 105 and 106, and a flip-flop 10 is supplied through an OR gate 107.
8 outputs the signal 104. The output signal 104 becomes level “1” when the phase shift request signal 101 is input, and becomes level “0” when the synchronization range detection signal 102 is input. This signal output 104 is connected to AND gates 109 and 11
0 and OR gate 111, and sync range adjusting circuit 112
To enter. The output signal 104 is the synchronization range adjusting circuit 1
After being protected by the set number of stages at 12, the output signal 113 is output from the flip-flop 118 as the synchronization state display signal 114 via the AND gates 115 and 116 and the OR gate 117. The synchronization status display signal 114 indicates that the synchronization is currently in progress when the level is “0”, and indicates that the synchronization is currently out of sync when the level is “1”.

Further, the range determined by the synchronization range adjusting circuit 112 to be in synchronization can be arbitrarily switched and set by the synchronization range setting signal 103. This synchronization range adjustment circuit 112
For example, if a quaternary counter is used, four settings can be made depending on the number of counting stages as shown in FIG.

[0019]

As described above, according to the present invention, by having the function of variable characteristic setting, it is possible to construct a DPLL having various characteristics in the same circuit, and it is versatile when integrated into an IC. Is significantly improved. Moreover, the effect of facilitating the DPLL characteristic evaluation, which has been difficult in the past, can be obtained by the synchronization status display function.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a stage number set value of a filter according to an embodiment of the present invention.

FIG. 3 is a phase state detection circuit diagram of an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a relationship between a synchronization range and set values according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Edge detection circuit, 2 ... Phase comparison circuit, 3 ... Filter, 4 ... Selector, 5 ... Phase shift circuit, 6 ... Phase state detection circuit, 7 ... Dividing circuit, 9 ... Self-folding signal, 10 ... Operating clock, 11 ... Reference input signal, 12 ... Filter setting signal, 13 ... Synchronization range setting signal, 101 ... Phase shift request signal,
102 ... Sync range detection signal, 103 ... Sync range setting signal, 105, 106, 115, 116 ... AND gate,
107, 117 ... OR gates, 108, 118 ... Flip-flops, 112 ... Synchronous range adjusting circuit, 114 ... Synchronous state display signals.

Claims (5)

[Claims] 1. An edge detection circuit for detecting an edge of a reference input signal, a phase comparison circuit for comparing the phases of an edge pulse output from the edge detection circuit and a self-folding pulse from the frequency dividing circuit, and the phase comparison circuit. Output delay of
In a digital PLL circuit including a filter that counts up and down the detection signal in each leading range and a frequency dividing circuit whose frequency division request signal output from the filter controls the frequency dividing ratio of the reference clock, the number of stages of the filter is Is provided with a selector for arbitrarily switching and setting the filter according to a filter stage number setting signal from the outside.
LL circuit. 2. An edge detection circuit for detecting an edge of a reference input signal, a phase comparison circuit for comparing the phases of an edge pulse output from the edge detection circuit and a self-folding pulse from the frequency dividing circuit, and the phase comparison circuit. Output delay of
In a digital PLL circuit including a filter that counts up and down the detection signal in each leading range, and a frequency dividing circuit whose frequency dividing ratio of the reference clock is controlled by the phase shift request signal output from the filter, A digital PLL circuit comprising a phase state detection circuit for inputting a phase shift request signal and a detection signal of the synchronization range from the phase comparison circuit and outputting a synchronization state display signal. 3. The phase state detection circuit includes a logic circuit which outputs a level “1” signal when the phase shift request signal is input and a level “0” signal when the synchronization range detection signal is input, and 3. A synchronization range adjusting circuit for counting the output signal of the logic circuit to protect a set number of stages, and a logic circuit for outputting a synchronization state indicating signal by the output of the synchronization range adjusting circuit. Digital PLL circuit. 4. The digital PLL circuit according to claim 3, wherein the synchronization range adjusting circuit is capable of switching and setting the set number of stages by an external synchronization range setting signal. 5. The logic circuit which outputs the synchronization status display signal outputs a synchronization status display signal which is binarized between a synchronization status and an out-of-sync status. Digital PLL circuit.