JPH0817206B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a protection device against static electricity applied to an external terminal such as an input terminal, an output terminal, or an input / output terminal.

[0002]

2. Description of the Related Art Since electrostatic discharge causes characteristic deterioration, junction breakdown, oxide film breakdown, etc., it is important to prevent electrostatic breakdown in manufacturing, assembling and using semiconductor devices. In particular, in the current situation where semiconductor devices such as ICs and LSIs are becoming finer with higher densities and higher integration, even a small amount of electrostatic discharge causes a failure. Above all, M
Since the OS type semiconductor device is an integrated field effect transistor (FET) having an insulated gate electrode, it is particularly vulnerable to electrostatic breakdown. This tendency is particularly strong in logic circuits such as CMOS ICs. Conventionally, as a protection circuit for static electricity applied to an external terminal connected to the outside of a MOS type semiconductor integrated circuit device, that is, an input terminal, an output terminal, an input / output terminal (hereinafter referred to as an I / O terminal), or the like, A protection element that performs a bipolar operation when static electricity is discharged is often used. This type of semiconductor device is disclosed in JP-A-61-217577,
It is disclosed in USP 4734752.

FIG. 14 shows a cross-sectional view of a conventional silicon semiconductor substrate having a MOS type semiconductor integrated circuit and a protection element which constitutes this protection circuit against static electricity. As shown in this figure, in a conventional MOS semiconductor integrated circuit, an LDD (Lightly Doped Drain-source) structure is often used to prevent characteristic deterioration of a MOS field effect transistor (hereinafter referred to as a MOS transistor) due to hot carry. Has been adopted. In the MOS structure device,
When the channel length is shortened to about 1.2 μm, the generation of hot carriers and the reduction of the breakdown voltage become problems, but this structure can prevent them. Although a plurality of N-channel MOS transistors are formed on the semiconductor substrate 10, as shown in FIG.
The drain 14 and the source 15 which are high-concentration diffusion layers of the transistors 7 and 8 have a low-concentration diffusion layer _LDDN- , respectively. Transistor 7
Is a protection element, and is a MOS transistor directly connected to an external terminal whose drain region 14 is connected to the external terminal (I / O terminal) 1. Further, the transistor 8 is a MOS transistor (hereinafter referred to as an internal transistor) in which the diffusion layer such as the drain region 14 is not directly connected to the I / O terminal 1, that is, not directly connected to the external terminal. The internal transistor is, for example,
It is used as an element forming an integrated circuit such as an inverter. The impurity concentration (dose amount) of the low-concentration diffusion layer _LDDN- can take an appropriate value required, but at present,
It is about 10 ¹⁸ to 10 ¹⁹ / cm ³ . In addition, here
A MOS in which an external terminal is directly connected to a diffusion layer such as a source or drain region is directly connected to the external terminal
The term “transistor” is also included in this category, in which a resistor is interposed between the external terminal and the diffusion layer.

Conventionally, the low concentration diffusion layers of a plurality of MOS transistors formed on one semiconductor substrate are usually made to have the same impurity concentration. Of course, for example, when a high-voltage circuit is in the same semiconductor substrate, the impurity concentration of the low-concentration diffusion layer of the MOS transistor included in the circuit is different from the impurity concentration of the low-concentration diffusion layer of the MOS transistor in another region. There are exceptions when the concentration is different. However, if the impurity concentrations of the low-concentration diffusion layers of a plurality of MOS transistors on the same semiconductor substrate are made different from each other, the ion implantation for forming the diffusion layer must be separated depending on the difference in the impurity concentration, and a mask for that purpose. It is also necessary to increase the value of the impurity concentration, and the benefit of changing the impurity concentration of the low-concentration diffusion layer is not particularly recognized. Therefore, the impurity concentration is usually the same as described above.

FIG. 10 shows a substrate current (Isub of the semiconductor substrate).
4) and the impurity concentration (Q _LDDN −) of the low concentration diffusion layer of the MOS transistor formed on this substrate. The vertical axis represents the substrate current (A), and the horizontal axis represents the impurity concentration (/ cm ³ ) of the low concentration diffusion layer. Curve L ₂ in this figure is an example of this prior art. L ₂ simultaneously shows the channel length of the MOS transistor, and it can be seen that the relationship between the substrate current and the impurity concentration depends on this channel length. A substrate current is a typical example in which a hot carrier in a channel jumps out of the channel without being confined in the channel, and this generation indicates characteristic deterioration. Therefore, such substrate current should be as small as possible. N channel M shown in FIG.
The impurity concentration of the low concentration diffusion layer L _DDN − of the OS transistor is set to a value (Q ₂ ) that minimizes the substrate current in view of the reliability of the semiconductor device and the demand for the power supply voltage. This value is the current value of 10 ¹⁸ to 10 ¹⁹ as described above.
/ Cm ^{3 is} selected. Curve L _1, a substrate current when the channel length of the MOS transistor to longer L ₁ than L ₂ - is a curve showing the impurity concentration profile. The reliability level of a MOS transistor is various phenomena represented by, for example, Vth shift and gm deterioration caused by the generation of hot carriers, and is described in "Ultra High Speed MOS Device, p 38, l4 ~
5, published by Baifukan ", it is possible to perform a linear approximation evaluation using the substrate current Isub. The reliability depends on the impurity concentration Q _LDDN − and the channel length. When the impurity concentration Q _LDDN − is increased or decreased, the reliability decreases. However, increasing the channel length provides sufficient reliability. It is possible to secure. Therefore, it can be seen that the longer the channel length, the smaller the minimum value of the substrate current as shown in the figure. However, for example, MOS transistors in low voltage circuits such as watches and calculators are
Since it is not significantly affected by hot carriers, it is not so affected by the substrate current-impurity concentration characteristics.

The channel length of the conventional MOS transistor is set to a length that can be processed by fine technology, and the channel lengths of the transistors 7 and 8 shown in FIG. 14 are the same. Although reliability increases as the channel length increases, it cannot be considered to increase as the miniaturization of semiconductor devices is strongly demanded as described above. It could be damaged.

[0007]

As described above, as semiconductor devices are miniaturized, the channel length becomes shorter and the resistance to electrostatic breakdown becomes smaller. Therefore, M that is directly connected to the external terminal that constitutes the protection circuit, etc.
The OS transistor cannot obtain a sufficient electrostatic breakdown voltage. Therefore, until now, M that is directly connected to the external terminal
In order to increase the electrostatic breakdown voltage of the OS transistor, the channel width (W) of the transistor has been increased. However, in order to effectively increase the breakdown voltage, for example, the channel length (L)
However, when 1.2 μm, the channel width W is usually 400 μm
However, it is necessary to increase this to about 800 to 1200 μm. Since this cannot cope with the trend toward miniaturization of semiconductor devices, this method cannot be said to be an effective means for increasing the breakdown voltage.

The present invention solves the problems of the conventional semiconductor device described above, and provides a semiconductor device capable of obtaining a sufficient electrostatic breakdown voltage and ensuring the same level of reliability as conventional ones. Is what you are trying to do.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
An external terminal, a low-concentration diffusion layer having a low impurity concentration, and a high-concentration diffusion layer continuously in contact with the low-concentration diffusion layer are provided on a semiconductor substrate, and the high-concentration diffusion layer is directly connected to the external terminal. An insulating gate type field effect transistor, a low-concentration diffusion layer and a high-concentration diffusion layer continuously in contact with the low-concentration diffusion layer, the high-concentration diffusion layer not directly connected to the external terminal. Type field effect transistor, and the impurity concentration of the low concentration diffusion layer of the insulating gate type field effect transistor directly connected to at least a part of the external terminals is directly connected to at least a part of the external terminals. It is characterized in that it is thinner than the impurity concentration of the low concentration diffusion layer of the insulating gate type field effect transistor which is not formed. The low concentration diffusion layer is a diffusion layer having an LDD structure or a double diffusion structure. A transistor in which the high-concentration diffusion layer is directly connected to an external terminal when the impurity concentration of the low-concentration diffusion layer of the transistor in which the high-concentration diffusion layer is not directly connected to the external terminal is 10 ¹⁸ to 10 ¹⁹ / cm ^3. The impurity concentration of the low-concentration diffusion layer of 3 × 10 ¹⁷ / c
m ³ to below. In this case, the channel length of the transistor directly connected to the external terminal is the same as the channel length of the transistor not directly connected to the external terminal.

[0010]

That is, according to the present invention, the impurity concentration of the low-concentration diffusion layer of the MOS transistor directly connected to at least a part of the external terminal is set to the impurity concentration of the low-concentration diffusion layer of the MOS transistor not directly connected to the at least a part of the external terminal. By making the concentration lower than the impurity concentration, the electrostatic breakdown voltage of the MOS transistor directly connected to the external terminal is improved. This is based on the knowledge of the inventor of the present invention that the relationship between the impurity concentration Q _LDDN − of the MOS transistor and the electrostatic breakdown voltage of the transistor has the characteristics shown in FIG. As is clear from the figure, the impurity concentration Q
_{If LDDN} − is made lower than the conventionally used concentration Q ₂ (Q ₃ ), it approaches a conventional structure and electrostatic withstand voltage is improved. Further, from the figure, it can be seen that even if the impurity concentration Q _LDDN − is made higher than the impurity concentration Q ₂ (Q ₁ ), it approaches a conventional structure and the electrostatic breakdown voltage is improved. In this example, Q ₁ is 3 × 10 ¹⁹ / cm ³ and Q ₂ is 3 × 10
¹⁸ / cm ³ and Q ₃ are 3 × 10 ¹⁷ / cm ³ .

FIG. 12 shows the relationship between the impurity concentration Q _LDDN − of the low concentration diffusion layer L _DDN − and the electric field in the lateral direction of the substrate. The vertical axis represents the electric field strength (× 10 ⁵ V / cm),
The horizontal axis represents the low concentration diffusion layer L _{DDN −high} concentration diffusion layer N ⁺ ,
The horizontal position of the substrate surface on which the dots and the like are formed is shown, and the boundary between both diffusion layers is zero. As shown in the figure, the electric field distribution with respect to the gate in the substrate changes depending on the impurity concentrations Q ₁ , Q ₂ , and Q ₃ . In particular, the peak position of the electric field is 0.1 at the gate edge for Q ₁ and Q ₃ , respectively.
It appears inside 5 μm and outside 0.02 μm. And Q
_In the case of ₂ , it appears 0.05 μm inside the gate edge. By the way, the gate edge is about 0.15.
A bird's beak is formed to the inside of μm. This part is usually not uniform in shape and is often notched. In the process of manufacturing a MOS transistor, after the polysilicon gate is patterned and post-oxidized to the polysilicon gate, the edge portion at the bottom of the gate is oxidized along the width direction of the gate. Get this oxidized part
A plurality of notches are formed in this area. The notches appear to correspond to the polysilicon grain boundaries.

The breakdown occurs when a high voltage is applied because the electric field is concentrated.
Many breakdowns occur at the above-mentioned peak positions. Q
_In the case of ₂ , since it is the notch portion, the number of break-down points is smaller than that of the other two cases, and the amount of current per unit area at the time of break-down increases, so that the transistor is destroyed at a low voltage. This is the reason why the breakdown voltage varies depending on the impurity concentration of the low concentration diffusion layer. When the breakdown voltage is increased by changing the impurity concentration, the transistor reliability such as generation of a substrate current may be reduced. In such a case, the reduction can be prevented by changing the channel length or the channel width.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an N-channel MOS transistor 11 which is directly connected to an external terminal such as an input / output terminal, an internal transistor and an N-channel MOS transistor 12 which are not directly connected to an input / output terminal.
The DD structure is adopted. Each transistor includes a source 15 and a drain 14 which are high-concentration diffusion layers, and a low-concentration diffusion layer _LDDN -which is continuously in contact with these. Also,
The length of the gate 13, that is, the channel length, is different between the two so that the transistor 12 is L ₂ and the transistor 11 is L ₁ . The drain 14 of the transistor 11 is directly connected to the I / O terminal 1.

2 to 6 show an example of a protection element that operates in a bipolar manner. FIG. 2 shows a P-channel MOS transistor 2 diode-connected to the 00 I / O terminal 1.
And an N-channel MOS transistor 3 are connected to each other. FIG. 3 shows an input protection circuit composed of the transistors 2 and 3 and a P-channel MOS transistor for inputting and outputting a signal in accordance with an internal signal. 4, an input / output circuit including an N-channel MOS transistor 5. Further, FIG. 4 shows an input protection circuit having an N-channel MOS transistor 6 for pulling down. In some cases, as shown in FIG. 5, only the input / output circuit directly connected to the I / O terminal 1 is used.

FIG. 6 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Bonding pads that are external terminals (I / O terminals) 1 are formed on the semiconductor substrate 10, and the external terminals 1 are connected to the drains 14 of the P-channel MOS transistor 2 and the N-channel MOS transistor 3. This transistor 3
Uses a MOS transistor 11 directly connected to the external terminal shown in FIG.
An input protection circuit is configured with the OS transistor 2.
The input protection circuit is connected to an internal circuit such as the inverter circuit IV, for example, through the aluminum wiring 9 and the resistor R made of polysilicon. The aluminum wiring 9 connects the drain 14 of the P-channel MOS transistor 2 and the resistor R, and further connects the resistor R and the gate 13 of the MOS transistor of the inverter circuit IV. The transistor of the inverter circuit IV is, for example, C
P channel MOS transistor 21 having a MOS structure
And N-channel MOS transistor 22. These transistors are internal transistors,
The channel transistor 22 uses the MOS transistor 12 described above. In this embodiment, the P-channel transistor does not have the LDD structure.

FIG. 7 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Here, only the MOS transistor directly connected to the external terminal is shown, and, for example, the portion of the internal transistor used in the internal circuit such as the inverter circuit is omitted. The external terminal 1 is directly connected to the input protection circuit and the input / output circuit. The drains 14 of the P-channel MOS transistors 2 and 4 constituting these circuits and an internal circuit such as an inverter circuit are connected by an aluminum wiring 9 via a polysilicon resistor R. The N-channel MOS transistor 11 shown in FIG. 1 is applied to the transistors 3 and 5 in this figure.

FIG. 8 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Here, only the MOS transistor directly connected to the external terminal is shown. In addition to the input protection circuit, the pull-down N-channel MOS transistor 6 is directly connected to the external terminal 1 to maintain a constant voltage. P that constitutes these circuits
The drain 14 of the channel MOS transistor 2 and an internal circuit such as an inverter circuit are connected by an aluminum wiring 9 through a polysilicon resistor R. The N-channel MOS transistor 11 shown in FIG.
In this figure, it is applied to the transistors 3 and 6.

FIG. 5 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Here, only the MOS transistor directly connected to the external terminal is shown. The input protection circuit is not connected to the external terminal 1, but the P-channel MOS transistor 4 and the N-channel MOS transistor 5 forming the input / output circuit are directly connected, and this circuit also serves as a protection circuit. Drain 1 of P-channel MOS transistor 4 which constitutes these circuits
4 to an internal circuit, for example, an inverter circuit, are connected by an aluminum wiring 9 via a polysilicon resistor R. The N-channel MOS transistor 11 shown in FIG. 1 is applied to the transistor 5 in this figure.
6 to 9, the source 15 of the transistors 2 and 4
The gate 13 is connected to the power supply V _DD , and the source 15 of the transistors 3 and 5 and the gate 13 are connected to the power supply V _ss . Also, the source 15 of the transistor 6 is
V _ss and gate 13 are connected to V _DD , respectively.

In such a circuit, in order to prevent deterioration of the characteristics of the MOS transistor due to hot carriers, for example, an LDD structure is adopted for the N-channel MOS transistor.

In this embodiment, as described above,
The electrostatic withstand voltage is improved by making the impurity concentration of the low concentration diffusion layer L _DDN − constituting the LDD structure of the MOS transistor 11 thinner than that of the MOS transistor 12. Of course, the electrostatic characteristics are improved by making the density higher than that of the MOS transistor 12, but this is not related to this embodiment. The impurity concentration range of the low concentration diffusion layer of the MOS transistor 12 is 1
Although it is 0 ¹⁸ to 10 ¹⁹ / cm ³ , the impurity concentration of the low concentration diffusion layer of the MOS transistor 11 for improving the electrostatic breakdown voltage is 3 × 10 ¹⁷ / cm ³ or less. That is, the relationship between the impurity concentration Q _LDDN -and the electrostatic breakdown voltage has the characteristics shown in FIG. As is clear from the figure, even if the impurity concentration Q _LDDN − is made thin (or made thicker), it approaches a conventional structure and the electrostatic breakdown voltage is improved. When _{increasing the} impurity concentration Q _LDDN −, the MOS transistor 11
The impurity concentration of the low-concentration diffusion layer _LDDN-
In the case of the μ process, Q ₁ , 3 × 10 ¹⁹ / cm ^3, and M
The impurity concentration of the low-concentration diffusion layer _{LDDN- with} respect to the OS transistor 12 is Q ₂ , 3 × 10 ¹⁸ / cm ³ . M
The impurity concentration of the low concentration diffusion layer of the OS transistor 11 is Q.
If it remains ₂ , the withstand voltage is about 50V, but Q ₃
Then, the breakdown voltage is improved to 350 V or higher.

In order to change the impurity concentration of the low-concentration diffusion layer _{LDDN- of} the MOS transistors 11 and 12, for example, first, impurities are ion-implanted into the MOS transistors 11 and 12 with the dose amount of the MOS transistor 12. After this,
Impurities are ion-implanted only into the low-concentration diffusion layer _{LDDN- of the} MOS transistor 11. In this way, when the dose amount (impurity concentration) with respect to the MOS transistor 11 is made higher than that of the MOS transistor 12, assuming that the channel lengths of these MOS transistors 11 and 12 are both the same as L ₂ , as shown in FIG. Transistor 11
The substrate current Isub may be larger than that of the MOS transistor 12.

Therefore, as shown by L ₁ in FIG.
When the impurity concentration is Q ₁ , the channel length of the MOS transistor 11 is set to the MOS so that the substrate current Isub of the MOS transistor 11 becomes the same as that of the MOS transistor 12.
The reliability can be improved by making the channel length longer than the channel length L ₂ of the transistor 12. If the channel length L ₂ of the MOS transistor 12 is 1.2 μm,
A suitable channel length L ₁ of the transistor 11 is 1.9 μm or more, and the optimum value is 1.9 μm. L ₂ is 1.
In the case of 0 μm, L ₁ is suitably 1.5 μm or more,
The optimum value is 1.5 μm. When L ₂ is 0.8 μm,
L ₁ is preferably 1.2 μm or more. However, if the impurity concentration is made as thin as Q ₃ as in this embodiment, the influence of hot carriers is reduced, so that the channel length does not have to be changed when used in a low voltage circuit. Increasing only the channel length of a MOS transistor connected to an external terminal such as an I / O terminal does not cause any design problem, and although the output current decreases, it is actually designed with a sufficient margin. In many cases, this does not hinder practical use.

In the above embodiment, the description has been made for the N-channel MOS transistor, but the LDD structure may be applied to the P-channel MOS transistor, or a high withstand voltage M of the double-diffused structure similar to the LDD structure.
The present invention may be applied to OS transistors and the like. FIG. 13 shows a MOS transistor having a double diffusion structure. Both the transistor 11 directly connected to the external terminal and the internal transistor 12 are provided with a drain 14 and a source 15 each consisting of a high concentration region n ⁺ and a low concentration region n ⁻ outside thereof. The channel length of the transistor 11 is L ₂ and the channel length of the transistor 12 is L ₁
Is set to. In order to increase the electrostatic breakdown voltage, the impurity concentration of the low concentration diffusion layer n ⁻ of the transistor 11 may be made lower than that of the transistor 12 as Q ₃ based on FIG.
As shown in FIG. 11, the low-concentration diffusion layer n of the transistor 11 is used.
^{Even if} the impurity concentration of ⁻ is made higher than that of the transistor 12 as Q ₁ , the electrostatic breakdown voltage is improved. However, if the concentration of the diffusion layer is high, the depletion layer becomes thin and the parasitic capacitance becomes large. In such a state, it is a problem for the high speed operation of the semiconductor device, and therefore, the low concentration diffusion layer n ^{− of the} transistor 11 is used.
It is more advantageous to make the impurity concentration of the transistor 12 thinner than that of the transistor 12 than to make it higher.

The present invention does not have to be applied to all MOS transistors connected to external terminals such as I / O terminals, but may be applied only to some MOS transistors. For example, the input / output circuit N shown in FIG.
The impurity concentration of the low concentration diffusion layer of the channel MOS transistor 5 can be made the same as that of the internal transistor. Since the impurity concentration is the same as that of the internal transistor, the reliability is sufficiently secured. Therefore, although the channel length is not lengthened, it is necessary to appropriately widen the channel width in order to improve the breakdown voltage. Since it is the MOS transistor that is directly connected to a small part of the external terminals that widens the channel width, there is no particular problem in practical use.

Of course, various modifications can be made without departing from the spirit of the invention. In the embodiment, the inverter is shown as a circuit that constitutes the internal transistor, but the present invention is not limited to this, and NOR, NAN
There are no particular restrictions on the circuit to which D, the transmission gate, etc. are applied. Further, it is optimally applied to, for example, a micro controller.

[0027]

As described in detail above, according to the present invention, the impurity concentration of the low concentration diffusion layer of the MOS transistor directly connected to the external terminal is made lower than the impurity concentration of the low concentration diffusion layer of the internal MOS transistor. As a result, it is possible to provide a semiconductor device that can obtain a sufficient electrostatic breakdown voltage and at the same time ensure the same level of reliability as conventional ones.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a circuit according to the present invention.

FIG. 3 is a configuration diagram showing a circuit according to the present invention.

FIG. 4 is a configuration diagram showing a circuit according to the present invention.

FIG. 5 is a configuration diagram showing a circuit according to the present invention.

6 is a schematic plan view of a semiconductor device in which the circuit of FIG. 2 is applied to a semiconductor substrate.

7 is a schematic plan view of a semiconductor device in which the circuit of FIG. 3 is applied to a semiconductor substrate.

8 is a schematic plan view of a semiconductor device in which the circuit of FIG. 4 is applied to a semiconductor substrate.

9 is a schematic plan view of a semiconductor device in which the circuit of FIG. 5 is applied to a semiconductor substrate.

FIG. 10 is a characteristic diagram showing a relationship between an impurity concentration corresponding to a channel length and a substrate current.

FIG. 11 is a characteristic diagram showing the relationship between the impurity concentration and the electrostatic breakdown voltage.

FIG. 12 is a diagram showing a relationship between an impurity concentration and an internal electric field distribution.

FIG. 13 is a cross-sectional view of a main part showing an embodiment of the present invention.

FIG. 14 is a sectional view of a main part of a conventional semiconductor device.

[Explanation of symbols]

1 external terminal (I / O terminal) 2, 4 P-channel MOS transistor 3, 5 N-channel MOS transistor 6 pull-down N-channel MOS transistor 7, 11 transistor directly connected to external terminal 8, 12 not directly connected to external terminal Internal transistor 9 Aluminum wiring 10 Semiconductor substrate 13 Gate 14 Drain 15 Source 21 Internal transistor (P channel MOS transistor) 22 Internal transistor (N channel MOS transistor)

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 29/78 H01L 29/78 301 L 301 K (72) Inventor Tomotaka Saito 580 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 1 Inside Toshiba Semiconductor System Technology Center (56) References JP-A-2-54959 (JP, A)

Claims (6)

[Claims] 1. A semiconductor substrate, an external terminal formed on the semiconductor substrate, a low-concentration diffusion layer formed on the semiconductor substrate, and a high-concentration diffusion layer continuously in contact with the low-concentration diffusion layer, An insulating gate type field effect transistor in which the high concentration diffusion layer is directly connected to the external terminal, a low concentration diffusion layer formed on the semiconductor substrate, and a high concentration diffusion layer continuously contacting the low concentration diffusion layer And the high concentration diffusion layer is not directly connected to the external terminal.
And a low concentration diffusion layer of the insulating gate type field effect transistor directly connected to at least a part of the external terminals, the impurity concentration of the low concentration diffusion layer is directly connected to at least a part of the external terminals. A semiconductor device, wherein the impurity concentration of the low concentration diffusion layer of the insulated gate type field effect transistor which is not connected is lower than that of the low concentration diffusion layer. 2. The insulation gate type field effect in which the impurity concentration of the low concentration diffusion layer of the insulation gate type field effect transistor directly connected to all the external terminals is not directly connected to all the external terminals. The semiconductor device according to claim 1, wherein the impurity concentration of the low-concentration diffusion layer of the transistor is lower than that of the transistor. 3. An insulating gate type field effect transistor in which the impurity concentration of the low concentration diffusion layer of the insulating gate type field effect transistor directly connected to at least a part of the external terminals is not directly connected to all the external terminals. The semiconductor device according to claim 1, wherein the impurity concentration of the low concentration diffusion layer of the field effect transistor is lower than that of the low concentration diffusion layer. 4. The semiconductor device according to claim 1, wherein the low-concentration diffusion layer is also a diffusion layer having an LDD structure or a double diffusion structure. 5. The semiconductor according to claim 1, wherein the channel length of the transistor directly connected to the external terminal is the same as the channel length of a transistor not directly connected to the external terminal. apparatus. 6. The high-concentration diffusion layer is connected to the external terminal when the impurity concentration of the low-concentration diffusion layer of the transistor in which the high-concentration diffusion layer is not directly connected to the external terminal is 10 ¹⁸ to 10 ¹⁹ / cm ^3. 7. The semiconductor device according to claim 6, wherein the low concentration diffusion layer of the directly connected transistor has an impurity concentration of 3 × 10 ¹⁷ / cm ³ or less.