JPH0816900B2 - How to build a data processing system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing technique and a technique particularly effective when applied to a microprocessor.

[0002]

2. Description of the Related Art A microcomputer system comprises a microprocessor, storage devices such as ROM (read only memory) and RAM (random access memory), and an input / output interface (I / O). It In this case, using the dynamic type RAM as the RAM is advantageous in that the system can be constructed at a low cost.

However, in the dynamic RAM, the address multiplex system is adopted and the refresh operation is required, so that the control is more troublesome than the ROM and the static RAM. Therefore, the conventional microprocessor is exclusively configured to directly access the ROM or the static RAM,
When configuring a system using a dynamic RAM, a / RAS (row address strobe) signal necessary for operating the dynamic RAM based on a clock signal and a control signal output from the microprocessor. A complicated external circuit such as a circuit for forming a signal / RFSH indicating a fresh timing together with a / CAS (column address strobe) signal has to be provided. In this specification, / (slash) added to the alphabetic symbol represents a bar signal whose low level is an active level. It should be noted that in the drawings, a line is added to the bar signal above the signal name or terminal name in alphabet by the conventional description method.

As described above, the conventional microprocessor has the problems that the system design becomes complicated when the dynamic RAM is used and the mounting area of the system becomes large.

Some conventional microprocessors have a built-in refresh counter for generating a refresh address of a dynamic RAM. Even such a microprocessor has a / RAS signal or a / RAS signal.
The CAS signal must be generated by an external circuit.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor which facilitates the design of a system using a dynamic RAM and can reduce the mounting area of the system.

Another object of the present invention is to provide a highly versatile microprocessor in which the capacity and number of dynamic RAMs to be used or the position of a dynamic RAM area in an address space can be freely changed to some extent. Especially.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, data having a dynamic memory accessed by the address multiplex system, a register for storing first data for instructing the address multiplex system, and second data for the capacity of the dynamic memory. A data processing system comprising a processing device and a read-only memory that stores a program to be executed by the data processing device and that is accessed by a method other than the address multiplex method. A method for constructing a data processing system capable of accessing the dynamic memory according to, wherein the first bit of a register of the data processing device is reset, and in response to the reset, the data processing device is configured to: Access the above read-only memory And a step of supplying the first data and the second data to an internal data bus of the data processing device by executing a program in the read-only memory by the data processing device, and the internal data. By writing the first data supplied to the bus into the first bit of the register, it becomes possible to multiplex and output a column address signal and a row address signal to the dynamic memory, and the data processing device. Setting step for setting the function of, and writing the second data supplied to the data bus to the second bit of the register to output the column address signal and the row address to the dynamic memory. In order to set the number of bits of each of the signals in response to the second data, The first to set the function 2
A data processing system including a setting process is constructed.

[0011]

[0012]

By the means described above, the static RAM and the dynamic RAM can be accessed and refreshed without providing any external circuit to facilitate system design and reduce the mounting area of the system. Let

By the means described above, it is possible to provide a highly versatile microprocessor in which the capacity and the number of dynamic RAMs used can be changed to some extent.

..

FIG. 1 shows an embodiment in which the present invention is applied to a 16-bit microprocessor. In the figure, the portion surrounded by the chain line A is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique.

In FIG. 1, what is indicated by a circuit code CPU is a microprocessor unit. Although the details of the microprocessor unit CPU are not shown,
For example, it is read from an execution unit EXEC that includes an arithmetic logic unit, a program counter, a stack pointer, a dedicated register such as a status register, and a general-purpose register group used as a work area, and an external memory (not shown). It is composed of an instruction register into which instructions of a macro program are sequentially input and a control unit CONT including a micro ROM storing micro instructions corresponding to each macro instruction.

The execution unit EXEC is a control unit CONT.
The control signals output from the devices are operated in an appropriate order. As a result, the desired data processing is executed. An external terminal group CT to which an interrupt signal and a reset signal are supplied is coupled to the control unit CONT.

An oscillator circuit OSC and a clock generator circuit CPG are provided for controlling the operation timing of the microprocessor unit CPU. The oscillation frequency of the oscillator circuit OSC is determined by a circuit element such as a crystal oscillator or a ceramic oscillator coupled between the external terminals XT1 and XT2. The clock generation circuit CPG receives the oscillation output of the oscillation circuit OSC and divides it appropriately to form the system clock φ.

In this embodiment, a dynamic RAM is provided on the same semiconductor substrate as the microprocessor CPU.
, A refresh counter RC for generating the refresh address, an address multiplexer MPX for selectively passing either the refresh counter RC or the address output from the execution unit EXEC, and the address multiplexer MPX.
The refresh counter RC, which is provided with a control signal generation circuit CSG for controlling the operation of, is operated by the operation clock signal φ of the system and is about 2 m.
The synchronizing signal / RFSH indicating the refresh timing is output once per second. Refresh counter RC
Further, within the period of the synchronizing signal / RFSH, the synchronizing signal / RFSH forming an address signal for accessing each row of the dynamic RAM is supplied to the microprocessor unit CPU and the control signal generating circuit CSG as a pair.

When the synchronizing signal / RFSH is generated, the microprocessor unit CPU is prohibited from accessing the address bus A-BUS. At the same time, a switching control signal is supplied from the control signal generation circuit CSG to the address multiplexer MPX. The switching control signal causes the multiplexer MPX to pass the refresh address supplied from the refresh counter RC instead of the address signal on the address bus A-BUS, and to the external address bus via the address buffer A-BBF. It is designed to output.

The synchronizing signal supplied from the refresh counter RC to the control signal generating circuit CSG is output to the outside as a signal / RFSH indicating refresh timing.

According to this embodiment, although not particularly limited, a plurality of types of memories can be coupled to the external address terminal AT at the same time, a plurality of address spaces corresponding to the respective memories, and a plurality of address spaces. Data indicating the attributes of the memory are set.

Although not particularly limited, two address setting registers AR1 and AR1 for identifying a plurality of address spaces,
AR2 and the address setting registers AR1 and AR2
2 and the address output from the microprocessor CPU on the address bus A-BUS are compared with each other, and two comparison circuits COMP1,
COMP2 and these two comparison circuits COMP1 and COM
A determination circuit DCD for determining which address range the address signal on the address bus A-BUS is in from the output state of P2 is provided. Address data is written to each of the address setting registers R1 and AR2 by the microprocessor unit CPU via the data bus D-BUS. Address setting register AR1
The contents of each of AR2 and AR2 are
It can be read out via the BUS.

The two address setting registers AR1 and AR2 allow the entire memory space to be divided into three. Although not particularly limited, the address data of the address setting register AR1 means the start address of the second address space,
That of R2 is made to mean the start address of the third address space.

That is, the boundary of the first address space and the second address space can be identified by the data of the register AR1, and the boundary of the second address space and the third address space can be identified by the data of the register AR2. To be

For example, the address data of the address setting registers AR1 and AR2 are "4" in hexadecimal.
If it is 00000 ”or“ B00000 ”, the first address space is set to the address range from“ 000000 ”to“ 3FFFFF ”, and the second address space is set to“ 40 ”.
The range is from "0000" to "AFFFFF".
Similarly, the third address space is in the range from "B00000" to "FFFFFF".

Address setting registers AR1 and AR2
A register including B0 to B2 in which data indicating the attributes of the memory corresponding to each of the three address spaces or ranges divided by the address set in is written (hereinafter referred to as a configuration register). CR1) to CR3 are provided.

In these configuration registers CR1 to CR3, bit B0 is written with data corresponding to the addressing system of the externally attached memory, and bits B1 and B2 are stored in the externally attached memory. Data corresponding to the capacity is written.

That is, the bit B0 is a memory of an address multiplex system such as a dynamic RAM, that is, a memory to which two kinds of address data such as a row address and a column address are to be supplied in a time division manner. Sometimes, it is set to "1", and when it is a memory such as ROM or static RAM to which two kinds of address data should be supplied simultaneously, it is set to "0".

Two bits consisting of bits B1 and B2 correspond to four types of storage capacities. For example, bit B
Combination of 1 and B2, "00", "01", "10"
And "11" are 16k bit, 64k bit, 25
It corresponds to a storage capacity of 6 kbits and 1 Mbits, respectively.

As a result, for example, each of the address setting registers AR1 and AR2 has a hexadecimal number of "4".
Consider a case in which the bits B0 of the configuration registers CR1 to CR3 are set to "0", "1", and "0", respectively. However, it is assumed here that "0" of the bit B0 indicates an address range other than the dynamic RAM, and "1" of the bit B0 indicates an address range other than the dynamic RAM. Then, as shown in FIG. 2, the addresses “000000” to “3FFFFF” become
Addresses “400000” to “AFFFFF” in the address area of the static RAM or ROM are the address areas of the dynamic RAM, and the address “B00”.
000 "to" FFFFFF "can be set to be the address area of the ROM or static RAM.

The above configuration register C
The information of each bit B0 of R1 to CR3 is the above-mentioned decision circuit
One of them is selectively supplied to the control signal generation circuit CSG through the selection circuit SEL1 which is switched by the judgment output signal of the CD. That is,
The address output on the address bus A-BUS is "0.
If it is between 00000 "and" 3FFFFF ",
Selection circuit SE controlled by output of determination circuit DCD
Configuration register CR by L1
The content of bit B0 of 1 is the control signal generation circuit CS
Supplied to G. On the other hand, if the address on the address bus is between "400000" and "AFFFFF", the contents of bit B0 of the configuration register CR2 and the address on the address bus are "B".
If it is between 00000 "and" FFFFFF ", the contents of the configuration register CR3 are supplied to the control signal generating circuit CSG.

Address determining means is constituted by the determining circuit DCD, the configuration registers CR1 to CR3, and the selecting circuit SEL1.

When the supplied bit B0 information is "0", the control signal generation circuit CSG outputs the address data A0 to A23 on the address bus as they are through the address multiplexer MPX to the address buffer A-.
It produces a control signal that is supplied to the BBF and outputs it to the address multiplexer MPX. On the other hand, when the information of the bit B0 supplied to the control signal generation circuit CSG is "1", the microprocessor unit CP
Of the address data output from U on the address bus A-BUS, a signal of a portion corresponding to the upper bit (or lower bit) necessary for accessing the dynamic RAM is latched in the address multiplexer MPX (not shown). And the signal of the portion corresponding to the lower bit (or upper bit) of the address is passed through the address multiplexer MPX as it is and output as the row address signal. Then, the upper bit (or lower bit) of the address already held in the latch circuit in the address multiplexer MPX is sent from the address multiplexer MPX to the address buffer A-BFF, and the same address terminal outputs it as a column address signal to the outside. Output. As a result, when the address range of the dynamic RAM is accessed, the upper bits and the lower bits of the address are output separately, that is, in the address multiplex system. Moreover, in the above case, the address multiplexer M
When the row address signal is output from the PX, the control signal generating circuit CSG is synchronized with this to form and output the low level / RAS signal as shown in FIG. 3, and the address multiplexer MPX outputs the row address signal. When the address signal is output, low level / CAS
A signal is formed and output.

The dynamic RAM connected to the microprocessor of this embodiment uses the / RAS signal and the / C signal.
In synchronization with the fall of the AS signal, the address output from the address buffer A-BFF at that time is fetched and accessed, and desired data can be read.

A data buffer D-BFF for inputting / outputting data to / from an external memory (not shown) is connected to the data bus D-BAS via an external data terminal DT as shown in the figure. .

On the other hand, when an address signal outside the address range of the dynamic RAM is output from the microprocessor unit CPU, the address signal passes through the address multiplexer MPX and is output to the outside as it is.

Further, the information of the bits B1 and B2 of the configuration registers CR1 to CR3 passes through the selection circuit SEL2 whose switching state is controlled by the output of the determination circuit DCD, one of which generates a control signal. Sent to the circuit CSG. Bits B1 and B2 of configuration registers CR1 to CR3
As described above, for example, when it is set to "0,0", the capacity of the corresponding dynamic RAM is 16K.
Indicates that it is a bit, and when it is "0, 1" it is 64
K bits, 256K bits when "1,0", "1,0"
When it is "1", it indicates that it is 1 Mbit.

When the information of the bits B1 and B2 of the configuration registers CR1 to CR2 is supplied, the control signal generation circuit CSG outputs the signal on the address bus A-BUS when it is "0,0". Of these, 14 bits (for example, A1 to A14) are recognized as a regular address of the dynamic RAM, the first half (A8 to A14) is latched in the address multiplexer MPX, and the other half (A1 to A7) is passed through. After that, half (A8 to A14) is output to the same external terminal.

When the bits B1 and B2 are "0, 1", 16 bits (for example, A
1 to A16) are recognized as regular addresses, and half of them (A9 to A1) are recognized by the address multiplexer MPX.
6) is latched and the other half (A1 to A8) is passed through. Even when the bits B1 and B2 are "1,0" and "1,1", the signals of 18 bits and 20 bits are similarly halved and output in two steps. .

Of the addresses A0 to A23 output from the microprocessor unit CPU, the dynamic type R
The remaining bits not used for the access to the AM are once latched in the address multiplexer MPX and continuously output to the outside while the lower bit and the upper bit are sequentially output as described above. For example, an address decoder provided on the memory board forms a chip select signal to select a dynamic RAM.

Further, in this embodiment, the selection circuit SEL
A signal indicating whether or not the address range of the dynamic RAM is supplied from 1 to the control signal generating circuit CSG is output to the outside as a / DRAM signal. This / DRAM signal makes it possible to know whether or not the microprocessor is in a state of accessing the dynamic RAM, and this signal can be used as a chip select signal of the dynamic RAM or the ROM or static RAM can be used. It can be deselected.

FIG. 4 is a connection diagram of the external memory. Although not particularly limited, the external memories DM1 and DM2 include address terminals A0 to A7, a data processing terminal DOUT, a column address strobe terminal / CAS, a reference potential terminal (ground terminal) Vss, a refresh control terminal / RFSH,
Data input terminal DIN, write enable terminal / WE,
Row address strobe terminal / RAS and power supply terminal Vc
It is composed of a 64K-bit dynamic RAM having c. The memories DM1 and DM2 are capable of inputting / outputting data bit by bit. In this case,
When a plurality of bits of input / output are required at the same time, a plurality of memories are required.

In the figure, the external address bus A-BU
SE is coupled to the external address terminal AT of FIG. 1, and the external data bus D-BUSE is connected to the external data terminal DT of FIG.
Is combined with

The decoder DEC has an external address bus A-
The row address strobe signals / RAS1 and / RAS2 to be supplied to the memories DM1 and DM2 are determined by the address signal supplied via BUSE and the row address strobe signal supplied via the terminal / RAS in FIG.
To form.

A common address signal is applied to the address terminals A0 to A7 of the memories DM1 and DM2 via the external address bus A-BUSE. As a result, the memory DM1 is selected by the address signal applied to the address terminals A0 to A7, and similarly, the memory DM2 is selected.
Are selected by the signal / RAS2 and the signals of the address terminals A0 to A7.

Column address strobe terminal / CAS and refresh control terminal / R of memories DM1 and DM2
The FSH and the write enable terminal / WE are commonly connected to the terminals / CAS, / RFSH and / WR of FIG. 1, respectively.

The data output terminals DOUT of the memories DM1 and DM2 are commonly connected to the input terminal of the bus driver TSC, and the data input terminal DIN is connected to the bus driver TSC.
And an output terminal of the external data bus D-BUSE.

The bus driver TSC is composed of a tri-state circuit and is supplied with a read control signal /
When RD is low level, the output signal of the level corresponding to the input signal supplied to the input terminal is output to the output terminal. The output of the bus driver TSC is brought to a high impedance state when the signal / RD is at high level.

According to this embodiment, the refresh counter RC is built in, and when the refresh address of the refresh counter RC is output to the outside, the signal / RFSH indicating the timing is output. Therefore, it is not necessary to form a complicated refresh control circuit for forming the refresh signal of the dynamic RAM with an external circuit.

Further, the microprocessor of this embodiment has a register for setting the address range of the dynamic RAM inside, and when accessing the address of the dynamic RAM, the address is automatically multiplexed inside the chip. It has become so.

Therefore, even when the static RAM and the dynamic RAM are mixed to form a system, the dynamic RAM without any external circuit is provided.
The AM can be accessed as easily as the static RAM.

In this case, the read / write control of the dynamic RAM is performed by the read control signal / RD and the write control signal / WR output from the microprocessor unit CPU.

Moreover, in this embodiment, the address range of the dynamic RAM can be arbitrarily set by setting appropriate addresses in the address setting registers AR1 and AR2.

In the case of the above embodiment, by resetting the bit Bo of the configuration registers CR1 to CR3 to "0" in the reset state, the ROM is initially set.
In general, the access state is set and the programs in the ROM are executed to set the address setting registers AR1 and AR2 according to the system configuration. However, it is also possible to change the setting values of the address setting registers AR1 and AR2 during the program to change the address range of the dynamic RAM.

As a result, it is possible to construct a system in which the address area of the ROM and the address area of the dynamic RAM overlap, and use the ROM or the RAM area as required. The address spaces set by the address setting registers AR1 and AR2 may correspond to a plurality of types of memories. For example, ROM and static RAM having the same addressing scheme can be associated with one address space. In this case, one partial address space in one address space corresponds to the ROM, and the other partial address space corresponds to the static type R.
Corresponding to AM.

Further, in the above embodiment, the dynamic type R is used for the configuration registers CR1 to CR3.
Since the bits B1 and B2 indicating the capacity of the AM are provided, the system can be configured using the RAM having an arbitrary capacity of 16K to 1M bits. However, the number of bits B1 and B2 of the configuration registers CR1 to CR3 indicating the capacity of the dynamic RAM is not limited to two as in the above embodiment, and one bit or three or more bits may be provided. Good.

Similarly, the bit B0 for pouring information as to whether or not it is within the address range of the dynamic RAM is set to 2 bits instead of 1 bit so that the ROM and the static RAM are
The address ranges may be distinguished. Also, the configuration registers CR1 to CR3
Further, bits for carrying information other than the above may be provided (for example, a bit indicating whether the corresponding address area is read-on or read / write, a program or data bit, a system area or user area).

In the above embodiment, two address setting registers are provided so that the address space of the microprocessor can be divided into three, but the number of these registers is not limited to two. It is also possible to provide one or three or more.

In the above embodiment, the present invention is applied to a 16-bit microprocessor, but it can also be applied to an 8-bit microprocessor.

[0060]

(1) Since the address to the dynamic RAM of the address multiplex system and the address to the static RAM (or ROM) not of the address multiplex system are supplied from a common terminal, the number of address terminals is increased. (If the invention of the present application is not applied, the number of address terminals can be 1.5 times as large as that of the invention of the present application). The ratio occupied in the chip is very large.) And the increase in the chip area of the semiconductor device can be prevented. Further, it is possible to prevent an increase in the number of pins of a package that seals the chip, and the package itself does not become large, so that it is possible to prevent an increase in system area.

(2) Addresses output from the multiplexer are dynamic type RAM and static type RAM
(Or ROM), which has a register in which information for designating which is supplied and a circuit for controlling the multiplexer in response to the contents of the register are included, so that the ROM is stored only at system startup. It is possible to operate in accordance with the above program, rewrite the register in the program, and then change the same address space to the dynamic RAM. This increases system design flexibility. (3) Since the address multiplexer controls whether the address is multiplexed and outputs the address or the address is not multiplexed according to the contents of the register, even if the address multiplexer is built in the semiconductor chip, The output of the address multiplexer is a dynamic type R of the address multiplex system.
It can be supplied to both AM and static RAM (or ROM) that is not address multiplexed. That is, since the signal delay in the semiconductor chip is much smaller than the signal delay between the semiconductor chips, the dynamic RAM and the static RAM (and ROM)
In both cases, since the address signal is not delayed and is input to the address terminal of the memory, the maximum characteristics (speed) of the memory can be obtained. (4) Further, since the register and the control means for changing the number of bits for address multiplexing of the address multiplexer are included, the memory capacity, that is, 1
It is possible to connect memories with different numbers of address bits corresponding to the number of address pins of each dynamic memory. That is, for example, in a 256K × 1 dynamic type memory, an 18-bit address needs to be divided into 9 bits, and in a 1M × 1 dynamic type memory, a 20-bit address needs to be divided into 10 bits and the address needs to be output. However, in the present invention, the address can be automatically output according to the contents of the register. Furthermore, in a system that initially used 256K dynamic memory, the memory generation changed,
Even if the 1M dynamic memory is used, it can be dealt with by simply rewriting the above register in the program at system startup. (5) Dynamic RA in the microprocessor
A register for specifying M access or static RAM (or ROM) access is provided, and the output format of the address can be changed according to the contents of this register, so not only static RAM but also dynamic RAM can be accessed directly. With such an effect, it is possible to facilitate the design of the system using the dynamic RAM and reduce the mounting area of the system. (6) Dynamic RA in the microprocessor
M access or static RAM (or RO
M) is provided with a register for designating access, and the output format of the address can be changed according to the contents of this register, and the address range and capacity of the dynamic RAM to be used, that is, the address signal Since a register for specifying the number of bits is provided, it is possible to freely change the capacity and number of the dynamic RAM to be used to some extent.
This has the effect of improving the versatility of the microprocessor.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it can be modified without departing from the scope of the invention. There is no end. For example, although the address range of the dynamic RAM is variable by the register in the above embodiment, it is also possible to fix the division of the address space by providing means for generating a constant address instead of the register.

Further, the configuration registers CR1 to CR3 are omitted, and which memory the address range divided by the address setting registers AR1 and AR2 belongs to is uniquely designated by the determination output of the determination circuit DCD. The address multiplexer MPX may be operated accordingly.

In the above description, the invention mainly made by the present inventor is described as being applied to a one-chip microprocessor which is the application field as the background, but the invention is not limited to this. It can also be used when configuring a chip microprocessor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a microprocessor according to the present invention.

FIG. 2 is a memory map showing an example of a divided state of an address space by an address setting register.

FIG. 3 is a timing chart showing timings of address signals and control signals when accessing a dynamic RAM.

FIG. 4 is a connection part of an external memory.

[Explanation of symbols]

CPU Microprocessor CONT Control unit EXEC execution unit MPX Address switching means (address multiplexer) RC Refresh address forming means (refresh counter) CSG control signal forming means AR1, AR2 Address setting means (address setting register) COMP1, COMP2 Comparing circuit DCD judgment circuit CR1 to CR3 configuration register SEL1, SEL2 selection circuit A-BUS address bus D-BUS data bus

Claims (2)

[Claims] 1. A dynamic memory which is accessed by an address multiplex system, and a first memory for instructing the address multiplex system.
Second on the capacity of data and the dynamic memory
Data processing in which a data processing device having a register for storing data and a read-only memory which stores a program to be executed by the data processing device and which is accessed by a method other than the address multiplex method are combined. A method of constructing a data processing system capable of accessing the dynamic memory by the data processing device, comprising resetting a first bit of a register of the data processing device and responding to the reset. The data processing device accesses the read-only memory, and the data processing device executes the program in the read-only memory to convert the first data and the second data into the data. Supplying to the internal data bus of the processing device, By writing the first data supplied to the data bus to the first bit of the register, it becomes possible to multiplex and output the column address signal and the row address signal to the dynamic memory, and the data processing is performed. A first setting step for setting the function of the device; and the column address signal and the row output to the dynamic memory by writing the second data supplied to the data bus into the second bit of the register. A second setting step of setting the function of the data processing device so as to set the number of bits of each of the address signals in response to the second data. 2. The method according to claim 1, wherein the first and second
The setting process is executed by the CPU, and the CPU is
A method for constructing a data processing system, wherein the data processing apparatus is provided inside the data processing apparatus, and the data processing apparatus is formed on a single semiconductor substrate.