JPH08167857A - Decoding system - Google Patents

Abstract

PURPOSE: To reduce the number of processing steps and to appropriately and easily execute a processing by executing parallel processing by a syndrome circuit for inputting plural received signal data. CONSTITUTION: Plural received signal data are outputted in parallel from a received signal buffer 1a through plural connection lines I11 .I12 ...I1j ...I1k . The syndrome circuit 2a inputs plural received signal data, generates syndrome by parallel processing and outputs the syndrome through wirings O1.0 .O1.1 ...O1.2t-2 .O1.2t-1 . Since the circuit 2 generates the syndrome by the parallel processing of syndrome operation, the number of processing steps in a decoding system for a Reed-Solomon code can be reduced and the processing can appropriately and easily be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for correcting a code error. In particular, it relates to a decoding method using a syndrome circuit in Reed-Solomon code.

[0002]

2. Description of the Related Art In a Reed-Solomon code decoding method, the code length of a received signal to be error-corrected is n,
_{Let the} received signals be r _n-1 , r _n-2 , r _n-3 ... R ₀ . At this time, the reception polynomial is expressed as in equation (1).

[0003]

[Equation 1]

Here, it is considered that the generator polynomial is defined by the equation (2).

[0005]

[Equation 2]

From the equations (1) and (2), the syndrome S _i
Is defined by equation (3).

[0007]

(Equation 3)

A conventional syndrome circuit is shown in FIGS.
This will be described with reference to FIG. 25 will be described. The reception signal is sent from the reception signal buffer 1 to the syndrome circuit 2 through the data line I, and after being subjected to arithmetic processing,
The syndromes S _{0 to} S _2t-1 are output to O _{0 to} O _2t-1 . Here, on the data line I, data is sequentially transferred every one clock cycle.

Here, when a RAM is used as the reception signal buffer, a storage method for holding the data in order, one data at a time, is adopted as shown in FIG. Then, if the address is incremented from 0 every clock, data can be easily transferred.

FIG. 27 shows the syndrome circuit 2 of FIGS. 6 to 7 in detail, which is 3A ₀ , 3A _1, ... 3A _2t-2.
3A _2t-1 indicates a syndrome generation circuit that generates S ₀ · S ₁ ... S _2t-2 · S _2t-1 respectively. Then, the syndrome generation circuits respectively have O ₀ · O ₁ ... O _2t-2 ·
Connected to the output line of O _2t-1 , the syndrome S ₀ · S ₁ ...
Outputs S _2t-2 and S _2t-1 .

[0011] Figure 28 is a diagram showing in detail the circuit configuration of the syndrome generating circuit _{3A0 · 3A1 ... 3A 2t-2} · 3A 2t -1 in Figure 27. _{5A 0 · 5A 1 ... 5A 2t} -2 · 5A
_2t-1 is an adding circuit, which is 4A ₀ , 4A _1, ... 4A _2t-2 , 4A
_2t-1 is a latch circuit. 6A ₀・ 6A ₁ … 6A _2t-2・
6A _2t-1 is a Galois field coefficient multiplication circuit of δ _a δ _{a + 1} ... δ _{a + 2t-2} δ _{a + 2t-1} .

These syndrome generation circuits 3A ₀ 3A
₁ ... 3A _2t-2 and 3A _2t-1 each have a configuration of a linear feedback shift register. In FIG. 29, the syndrome S
indicates the i-th syndrome generating circuit for generating a _i,
FIG. 30 shows the waveform at each point.

First, in the initial state, the latch circuit 4A
_When the data of _i is 0, 0 is output from the output terminal O _i . Next, the received data r _n-1 is input to the input terminal I, and C
When the clock is input to LK and the data is latched at 4A _i , r _n-1 is output from the output terminal O _i . Then, when the clock and the received data are sequentially input, the value of the following expression (4) is output.

[0014]

[Equation 4]

From the equation (4), the output O of the nth clock
_It can be seen that _in is the syndrome S _i . Thus, in the conventional circuit, in order to generate the syndrome value,
The number of clocks equal to the code length of the received signal is required, and in order to shorten the syndrome processing time, the clock frequency and the data transfer speed have been increased.

[0016]

SUMMARY OF THE INVENTION The present invention intends to appropriately and easily carry out processing by parallel processing of syndrome operations.

It is an object of the first invention to reduce the number of processing steps by parallel processing of syndrome operations and to perform the processing properly and easily.

A second object of the present invention is to reduce the number of processing steps by parallel processing of the syndrome operation and to perform the processing more appropriately and easily.

A third object of the present invention is to reduce the number of processing steps by parallel processing of the syndrome operation and to perform the processing more appropriately and easily.

A fourth object of the present invention is to reduce the number of processing steps by parallel processing of the syndrome operation and to perform the processing more appropriately and easily.

A fifth aspect of the present invention has an object of appropriately performing code length adjustment in performing parallel processing of syndrome operations and performing the processing appropriately and easily.

A sixth object of the present invention is to accurately perform syndrome generation and chain search, and parallel syndrome generation processing for a plurality of received signals.

[0023]

In the first invention, a received signal data buffer capable of outputting a plurality of received signal data in parallel and a plurality of received signal data outputted from the received signal data buffer are inputted and processed. And a syndrome circuit for performing the above. The syndrome circuit performs parallel processing.

In the second invention, when the plurality of received signal data input to the syndrome circuit are assigned in the order of the received signal data, the syndrome circuit respectively assigns the Galois field coefficient to the assigned data. Parallel processing is performed by the feedback shift register composed of the multiplication circuit and the addition circuit of the next data, and after the final data is processed, the data of each feedback shift register is multiplied by the predetermined Galois field coefficient multiplication circuit and multiplied. The syndrome is generated by adding the respective data.

In the third invention, when a plurality of received signal data input to the syndrome circuit are allocated in the order of the received signal data, the plurality of data are added to the feedback circuit of one feedback shift register. An addition circuit for performing the above is provided, and a predetermined Galois field coefficient multiplication circuit is inserted between the respective addition circuits.

In the fourth invention, when a plurality of received signal data are allocated in a discrete order, the syndrome circuit adds the Galois field coefficient multiplication circuit and the next data addition circuit to the allocated data, respectively. After performing the parallel processing by the feedback shift register configured by, the data of each feedback shift register is multiplied by the predetermined Galois field coefficient multiplication circuit, and each multiplied data is added. By doing so, the syndrome is generated.

In the fifth aspect of the invention, when the code length of the received signal data is not divisible by the parallel number for parallel processing, 0 data is added to the beginning of the received signal data to adjust the code length. On the input side of the data buffer.

In the sixth invention, the feedback shift register for performing respective parallel processing controls the input signal line for the coefficient data of the error locator polynomial, the selector for selecting the input signal line and the received signal data, and the selector. By installing a mode setting register and a decoder, the syndrome generation and chain search, and the parallel syndrome generation processing for a plurality of received signals are performed.

[0029]

In the first aspect of the invention, the syndrome circuit receives a plurality of received signal data output from the received signal data buffer and performs parallel processing.

In the second invention, the syndrome circuit is a feedback shift register composed of a Galois field coefficient multiplication circuit and a next data addition circuit for a plurality of received signal data assigned in the order of the received signal data. By parallel processing, and after processing the final data, the data of each feedback shift register is multiplied by a predetermined Galois field coefficient multiplication circuit, and each multiplied data is added. Generate.

In the third invention, the adder circuit adds a plurality of received signal data assigned in the order of the received signal data to the feedback circuit of one feedback shift register, and a predetermined Galois field coefficient is provided between the adder circuits. A multiplication circuit is inserted.

In the fourth invention, the syndrome circuit uses a feedback shift register composed of a Galois field coefficient multiplication circuit and a next data addition circuit for a plurality of received signal data allocated in a discrete order. Parallel processing is performed, and after the final data is processed, the data in each feedback shift register is multiplied by the predetermined Galois field coefficient multiplication circuit, and each multiplied data is added to generate the syndrome. I do.

In the fifth aspect of the present invention, the code length adjusting circuit provided on the input side of the data buffer, if the code length of the received signal data is not divisible by the number of parallel processes for parallel processing,
0 data is added to the beginning of the received signal data, and the code length is adjusted.

In the sixth invention, an input signal line for coefficient data of an error locator polynomial, provided in a feedback shift register for performing respective parallel processing, and a selector for selecting the input signal line and the received signal data, The mode setting register for controlling the selector and the decoder perform syndrome generation and chain search, and parallel syndrome generation processing for a plurality of received signals.

[0035]

【Example】

Example 1. 1 to 4 show a first embodiment of the present invention. FIG. 1 is a system block diagram showing a connection state of the reception signal buffer 1a and the syndrome circuit 2a. From the received signal buffer 1a, k-number of connecting lines I ₁₁ · I ₁₂ ......
I _1j ... I _1k are connected to the syndrome circuit 2a, and the syndrome S ₀ · S ₁ ...
Wiring for outputting S _2t-2・ S _2t-1 O ₁ , ₀・ O ₁ , _1, ... O ₁ , _2t-2
-O ₁ , _2t-1 is output (however, k is an arbitrary number that can divide n).

FIG. 2 shows an example of the memory configuration of the reception signal buffer 1a shown in FIG. 1. When the address 0 is accessed, k reception signals r _n-1 , r _n-2 ... R _nj ... R _{nk are received. Are} output in parallel to the connection lines I ₁₁ , I ₁₂ ... I _1j ... I _1k . Similarly, every time the address is incremented, k received signals in order are output in parallel to the syndrome circuit 2a.

FIG. 3 shows the syndrome circuit 2 in FIG.
3 is a detailed representation of the internal configuration of a. The k connecting lines I ₁₁ , I ₁₂ ... I _1j ... I _1k are respectively S ₀ · S ₁ ... S _2t-2.
・ Syndrome generation circuit 3a ₀ , 3a for generating S _2t-1
1 ... 3a _2t-2 and 3a _2t-1 are connected in parallel.
These syndrome generation circuits 3a ₀ , 3a _1, ... 3a _2t-2 ,
3a _2t-1 constitutes a linear feedback shift register.

FIG. 4 shows a syndrome generation circuit for generating the syndrome S _i . Further, FIG. 5 shows a timing chart at each point of FIG.

In FIG. 4, L _1i1 , L _1i2 ... L _1ij ...
L _1ik is a latch circuit, M _1i1 , M _1i2 ... M _1ij ... M _1ik
Is a Galois field coefficient multiplication circuit of α ^{(a + i) k} , M _1i11 , M _1i22
... M _1ij1 are respectively α ^{(a + i) (k-1)} , α ^{(a + i) (k-2)} ,
…, Α ^{(a + i) (kj)} Galois field coefficient multiplication circuit, 5a _i1 , 5
a _i2 ... 5a _ij ... 5a _ik is an adder circuit, N _i1 , N _i2 ... N _ij ...
N _ik is an output signal line of M _1i1 , M _1i2 ... M _1ij ... M _1ik ... L _1ik , 7a _i is an adder circuit for adding signals of N _i1 , N _i2 ... N _ik , and O 1i is an adder circuit. This is an output signal terminal and outputs the syndrome S _i .

The operation will be described with reference to the timing chart of FIG. First, as an initial state, the latch circuits L _1i1 ,
The data value of L _1i2 ... L _1ij ... L _1ik is set to 0. At this time, the value at the output end is O1i0 = 0. At the first clock, the reception signal data r _n-1 , r _n-2, ..., R _nj, ..., R _nk are input to I ₁₁ , I _12, ..., I _1j, ..., I _1k , respectively, and the output terminal O _1i.
Then

[0041]

(Equation 5)

Is output. Similarly, at the second clock, I ₁₁ , I ₁₂ ... I _1j ... I _1k are _replaced by r _nk-1 , r _nk-2, ... R.
_nkj … r _n-2k is input,

[0043]

(Equation 6)

Similarly, at the third clock,

[0045]

(Equation 7)

At the 4th clock,

[0047]

(Equation 8)

Therefore, at the n / kth clock,

[0049]

[Equation 9]

From the equation (5), if the syndrome generation circuit of FIG. 4 is used, the syndrome can be generated with the clock number of 1 / k of the conventional case.

With the progress of miniaturization process technology, the circuit scale and the signal propagation delay have been reduced.
The clock frequency is bound to some part throughout the system and cannot be increased easily. Therefore, according to the embodiment of the present invention, it is possible to provide k times the processing capability at the same frequency, which contributes to the realization of high-speed error correction.

Thus, in this embodiment, as shown in FIG.
To the configuration of the processing system or apparatus shown in FIG. 4 and the processing method in the system / apparatus,
The content of the implementation.

Embodiment 2 FIG. 6 to 7 show a second embodiment of the present invention.
An example will be described. FIG. 6 shows a syndrome circuit that generates the syndrome S _i . FIG. 7 shows a timing chart at each point in FIG.

The input terminals I ₂₁ , I ₂₂ ... I _2j ... I of FIG.
_2k is I ₁₁ , I ₁₂ ... I _1j ... I in FIG. 5 of the first embodiment.
To _1k, and a terminal to which each corresponding, at the first clock, to the respective terminals, k number of receiving the order data _{r n-1, r n-} 2 ... r nj ... in parallel r _nk input _However , at the second clock, r _nk-1 , r _nk-2 ... R _nkj ... R
Enter _n-2k . In this way, n received signal data are input for n / k clocks.

The input data are added to the outputs of the Galois field coefficient multiplication circuits M _2i1 , M _2i2 ... M _2ij ... M _2ik by addition circuits 8 _i1 , 8 _i2 ... 8 _ij ... 8 _ik . CLK2 is a clock input terminal for latching data in the latch circuit L _2i . O _2i is a latch circuit L
_{This is a} terminal connected to the output terminal of the _2i data and for outputting the syndrome S _i .

The operation will be described with reference to FIG. The initial state is 0. First, the data latched in the latch circuit at the first clock is

[0057]

[Equation 10]

At the second clock,

[0059]

[Equation 11]

At the third clock,

[0061]

(Equation 12)

At the n / k clock,

[0063]

(Equation 13)

From the equation (6), if the syndrome circuit of FIG. 7 is used, the syndrome can be generated with the number of clocks of 1 / k of the conventional case, as in the first embodiment. Although this circuit has a longer critical path than that of the first embodiment, it can be realized by adding only a Galois field coefficient multiplication circuit and an addition circuit to the conventional circuit. The same processing can be performed with a smaller circuit scale than

Thus, in this embodiment, as shown in FIG.
To the configuration of the processing system or apparatus shown in FIG. 7 and the processing method in the system / apparatus,
The content of the implementation.

Example 3. 8 to 12 show a third embodiment of the present invention. FIG. 8 is a system block diagram including a reception signal buffer and a syndrome circuit. Each of the k received signal buffers 1 _b1 , 1 _b2 ... 1 _bj ... 1 _bk is n.
/ K received data are stored.

FIG. 9 shows a memory configuration example of the reception signal buffer. Received signal buffer [1] 1 _b1 stores received signal data from address 0 to (n / k) -1
_n-1 , r _n-2 ... r _{n- (2n / k) +1} ... r _{n- (2n / k) in} the order k
Are stored. Similarly, in the reception signal buffer [2] 1 _b2 , from address 0 to address (n / k) -1, r
_{n- (n / k) -1} , rn _{(n / k) -2} ... _{rn- (2n / k) +1} , ... _{rn- (2n / k)}
It is stored in the form. In this way, from the reception signal buffer [1] 1 _b1 to the reception signal buffer [k] 1 _bk
Up to this point, n pieces of received data from r _n-1 to r ₀ are stored. These received signal data are stored in the syndrome circuit 2
b through the data connection lines I ₃₁ , I ₃₂ ... I _3j ... I _3k ,
It is output in parallel from the address 0 in order.

FIG. 10 shows the internal structure of the syndrome circuit 2b in FIG. 8 in detail. The k connection lines I ₃₁ , I ₃₂ ... I _3j ... I _3k are respectively connected to the syndrome S.
₀ , S ₁ ... S _2t-2 , S _2t-1 are connected in parallel to the syndrome generation circuits 3b ₀ , 3b ₁ ... 3b _2t-2 , 3b _2t-1 .

FIG. 11 particularly shows a syndrome generation circuit for generating the syndrome S ₁ , and FIG. 12 shows a timing chart at each point of FIG. 11.
In FIG. 11, L _3i1 , L _3i2 ... L _3ij ... L _3ik are latch circuits, M _3i1 , M _3i2 ... M _3ij ... M _3ik are α ^{a + i.}
Galois field coefficient multiplication circuit, M _3i11 , M _3i21 ... M _3ij1 ... M
_3ik1 ... are each

[0070]

[Equation 14]

Galois field coefficient multiplication circuit of 5b _i1 and 5b _i2
... 5b _ij ... 5b _ik is an addition circuit, N _{i1 b} · N _i2b ... N
_ijb ... N _ikb are M _3i11 , M _3i21 ... M _3ij1 ... L, respectively.
_{3ik is} an output data signal line, 7b _i is an adder circuit for adding the signals of the output data signal lines N _i1b · N _i2b ... N _ijb ... N _{ik b} , and O _3i is an output signal terminal of the addition circuit 7 _bi. Yes,
Output the syndrome S _i .

The operation of the circuit will be described with reference to the timing chart of FIG. First, as an initial state, the latch circuits L _3i1 , L _3i2 ... L _3ij ... L _3ik are _set to 0. At the first clock, I ₃₁ , I ₃₂ ... I _3j ... I _3k respectively receive signal data

[0073]

(Equation 15)

When inputting, the output terminal O _3i

[0075]

[Equation 16]

At the second clock, I ₃₁ , I ₃₂ ... I _3j ... I
Received signal data for each _3k

[0077]

[Equation 17]

Is input, and at the output terminal O _3i ,

[0079]

(Equation 18)

At the third clock,

[0081]

[Formula 19]

Therefore, at the n / kth clock,

[0083]

(Equation 20)

From the equation (7), if the syndrome generation circuit of FIG. 11 is used, for received signal data of code length n, n
The syndrome S _i can be calculated with the number of clocks of / k. That is, the syndrome calculation process can be completed with the number of clocks of 1 / k of the conventional circuit.

Thus, in this embodiment, as shown in FIG.
To the configuration of the processing system or apparatus shown in FIG. 12 and the processing method in the system / apparatus,
The content of the implementation.

Example 4. 13 to 15 show a fourth embodiment of the present invention. FIG. 13 shows a code length adjusting circuit 8,
The system block diagram which comprises the received signal serial-parallel conversion circuit 9 and the received signal buffer 10 is shown. FIG.
4 shows an example of the code length adjusting circuit 8, and FIG. 15 shows a timing chart at each point of FIG.

In this embodiment, in the code length n and the arbitrary natural number k in the first to third embodiments, if n is not divisible by k, it becomes a divisible number for the input received signal symbol. It is characterized by using a code length adjusting circuit 8 for adding an appropriate O symbol.

The blocks or circuits of FIGS. 13 and 14 will be described with reference to the timing chart of FIG. Serial received signal data r _n-1 , r _n-2 , r _n-3, ... R ₀ is input from the input terminal R1 of FIG.
Examples 1 to 3 are applied to the input data.
In the syndrome circuit described above, the data is allocated to k pieces and the parallel processing is performed. However, when the remainder of Q is obtained when n is divided by k, k−Q pieces of 0 pieces of data are previously converted to the code length adjusting circuit. Add by 8.

FIG. 14 shows an example of the code length adjusting circuit 8.
It R₁ Is the input terminal of the received signal data, CLK4 is the
Shift register 11_-1・ 11 _-2… 11_-kIn contrast to the data
A clock input terminal for latching. RESE
T4 is the shift register 11_-1・ 11_-2… 11_-kDay of
This is a reset signal terminal for setting the initial state of the
It 12 is a shift register 11_-1・ 11_-2… 11_-kDe
Select one of the data from the selector
The data is R₂ Is output to The number of errors Q is the number of errors
The number register 13 is latched, and the decoder 14
Data of the control signal of the selector 12 is generated.

In FIG. 15, k = 5 and the remainder Q obtained by dividing n by k.
6 is a timing chart when = 1. Input terminal R1
To the data, and outputs the output data of the shift register 11 _-4 code length adjusting circuit 14 from the R ₂ by the selector 12. That is, k-Q = 4 pieces of 0 data are added to the beginning of the received signal data. In this way, with respect to the received signal to which 0 data is added, for example, in the case of the first and second embodiments, the received signal serial-parallel conversion circuit 9 causes the parallel data lines of R ₃₁ , R _32, ... R _k. A signal is allocated to the and the data is stored in the reception signal buffer.

[0091] The received code polynomial in _{R 1 R 1 (X),} R 2
Let R ₂ (X) be the received code polynomial in

[0092]

[Equation 21]

Equation (8) shows that, when k-Q pieces of received signal data are added, they are equivalent as polynomials if 0 is added to the higher order side. Further, according to the following equation (9), It turns out that the syndromes are equal.

[0094]

[Equation 22]

As described above, when this circuit is used, parallel processing can be easily performed when the code length is the number k of parallel processing and n is not divisible by k.

Thus, in this embodiment, as shown in FIG.
The configuration of the processing system or apparatus shown in FIGS. 3 to 15 and the processing method in the system / apparatus are the contents of implementation.

Example 5. 16 to 24 show a fifth embodiment of the present invention. FIG. 16 shows a system block diagram of the present invention. 1C1 and 1C2 are reception signal buffers, and each address has one reception data, as in the third embodiment. Reference numeral 15 is a control signal generation circuit, which receives the received signal data from the received signal buffer 1C1 or 1C2 in 1
Control signals SO and S for selecting whether to take in the linear feedback shift register circuit of 6a ₁ and 16a ₂ or to work on the coefficient data of the error locator polynomial from the input terminal 17.
1 is output.

In this embodiment, the functions shown in FIGS. 17 to 19 can be obtained by switching the control signal. FIG. 17 has the same function as the circuit when k = 2 in the third embodiment. The received signal buffer 1 stores received signals r _n-1 to r _{n / 2 in} order from address 0, and the received signal buffer 2 stores r _{(n / 2) -1} to r ₀ from address 0. Stored in order. The data in these two reception signal buffers are sequentially read from address 0, and the parallel feedback shift register circuits are used to perform the parallel processing of the syndrome generation, thereby ending the syndrome generation in n / 2 clocks.

In the method of FIG. 18, the first and second received code data are respectively stored in the two received signal buffers, and the linear feedback shift registers respectively generate the first and second syndromes in parallel. In FIG. 19, the linear feedback shift register circuit 1 is used for the Chien search and the linear feedback shift register circuit 2 is used for the syndrome generation.

20 and 21 are used to describe this linear feedback shift register circuit in detail. Figure 2
In the third embodiment, 0 is a circuit for generating the syndrome S _i when k = 2. The feedback shift register portions at this time are 18a ₁ and 18a ₂ . FIG. 21 shows the linear feedback shift register circuit unit 16a _{1 of} FIG. 16 according to the present embodiment.
And 16a ₂ are shown in detail. Where 18b
_1. 18b ₂ is a feedback shift register circuit equivalent to 18a ₁ 18a ₂ in FIG. Input terminal 17 is a terminal for inputting the coefficient data of the error position polynomial, Id ₁ · I
d ₂ is a terminal SO for inputting received signal data, respectively
S1 is a control signal input terminal for selecting input data 19b ₁ and 19b ₂ are selectors for selecting and outputting the input data. O _5i is an output terminal of the syndrome which performs n / 2 clock processing, and O _5i1 and O _5i2 are output terminals of the syndrome which outputs n clock processing or the error position data obtained by the Chien search.

22 to 24 show waveforms at respective points in the modes corresponding to FIGS. 17 to 19.

Thus, in this embodiment, as shown in FIG.
The configuration of the processing system or apparatus shown in FIGS. 6 to 24 and the processing method in the system / apparatus are the contents of implementation.

[0103]

According to the first aspect of the present invention, the number of processing steps can be reduced by parallel processing of the syndrome operation, and the processing can be appropriately and easily performed.

According to the second invention, the number of processing steps can be reduced by parallel processing of the syndrome operation, and the processing can be performed more appropriately and easily.

According to the third invention, the number of processing steps can be reduced by the parallel processing of the syndrome operation, and the processing can be performed more appropriately and easily.

According to the fourth invention, the number of processing steps can be reduced by parallel processing of the syndrome operation, and the processing can be performed more appropriately and easily.

According to the fifth aspect of the present invention, the code length adjustment can be appropriately performed in parallel processing of the syndrome operation, and the processing can be appropriately and easily performed.

According to the sixth invention, it is possible to accurately perform the syndrome generation and chain search, and the parallel syndrome generation processing for a plurality of received signals.

[Brief description of drawings]

FIG. 1 is a system block diagram showing a connection state of a reception signal buffer and a syndrome circuit according to a first embodiment.

FIG. 2 is a diagram showing a memory configuration example of a reception signal buffer according to the first embodiment.

3 is a diagram showing in detail the syndrome circuit portion of FIG. 1. FIG.

FIG. 4 is a diagram showing a syndrome circuit for generating a syndrome S _{i according} to the first embodiment.

FIG. 5 is a diagram showing a timing chart for explaining the operation of FIG. 4;

FIG. 6 is a diagram showing a syndrome circuit for generating a syndrome S _{i according} to the second embodiment.

FIG. 7 is a diagram showing a timing chart for explaining the operation of FIG. 6;

FIG. 8 is a system block diagram showing connection states of a reception signal buffer and a syndrome circuit according to a third embodiment.

FIG. 9 is a diagram showing a memory configuration example of a reception signal buffer according to a third embodiment.

FIG. 10 is a diagram showing in detail the syndrome circuit portion of FIG.

FIG. 11 is a diagram showing a syndrome circuit for generating a syndrome S _{i according} to the third embodiment.

FIG. 12 is a timing chart for explaining the operation of FIG.

FIG. 13 is a system block diagram according to a fourth embodiment.

FIG. 14 shows an example of a code length adjusting circuit according to a fourth embodiment.

FIG. 15 is a timing chart for explaining an operation according to the fourth embodiment.

FIG. 16 is a system block diagram according to a fifth embodiment.

FIG. 17 is a conceptual diagram showing the function of each feedback shift register section according to the fifth example.

FIG. 18 is a conceptual diagram showing the function of each feedback shift register section according to the fifth example.

FIG. 19 is a conceptual diagram showing the function of each feedback shift register section according to the fifth example.

FIG. 20 is a diagram illustrating a syndrome generation circuit according to a third embodiment.

FIG. 21 is a diagram showing a feedback shift register section in the fifth example.

22 is a diagram showing waveforms at respective points in a mode corresponding to the function shown in FIG.

23 is a diagram showing waveforms at respective points in the mode corresponding to the function in FIG.

24 is a diagram showing waveforms at respective points in the mode corresponding to the function shown in FIG.

FIG. 25 is a system block diagram showing a conventional example.

FIG. 26 is a diagram showing a memory configuration in a conventional example.

FIG. 27 is a diagram showing in detail the syndrome circuit portion of FIG. 25.

28 is a circuit configuration diagram of the syndrome circuit of FIG. 27. FIG.

FIG. 29 is a diagram illustrating one of conventional syndrome generation circuits.

30 is a diagram showing waveforms at respective points in FIG.

[Explanation of symbols]

 1 receive signal buffer, 2 syndrome circuit.

Claims (6)

[Claims] 1. In a Reed-Solomon code decoding method, a reception signal data buffer capable of outputting a plurality of reception signal data in parallel and a plurality of reception signal data output from the reception signal data buffer are input and processed. A decoding method, comprising: a syndrome circuit, wherein parallel processing is performed by the syndrome circuit. 2. When a plurality of received signal data input to the syndrome circuit are allocated in the order of the received signal data, the syndrome circuit operates as a Galois field coefficient multiplication circuit for each of the allocated data. Parallel processing is performed by the feedback shift register composed of the adder circuit of the next data, and after the final data is processed, the data of each feedback shift register is multiplied by the predetermined Galois field coefficient multiplication circuit, and each multiplied The decoding system according to claim 1, wherein the syndrome is generated by adding the data. 3. When a plurality of received signal data input to the syndrome circuit are allocated in the order of the received signal data, an addition for adding the plurality of data to the feedback circuit of one feedback shift register. The decoding system according to claim 1, wherein a circuit is provided and a predetermined Galois field coefficient multiplication circuit is inserted between the respective addition circuits. 4. When a plurality of received signal data are assigned in a discrete order, the syndrome circuit feeds back the assigned data by a Galois field coefficient multiplication circuit and a next data addition circuit, respectively. By performing parallel processing by the shift register and processing the final data, the data of each feedback shift register is multiplied by a predetermined Galois field coefficient multiplication circuit, and addition is performed on each multiplied data. The decoding method according to claim 1, wherein a syndrome is generated. 5. When the code length of the received signal data is not divisible by the number of parallel processes for parallel processing, 0 data is added to the beginning of the received signal data and a code length adjusting circuit for adjusting the code length is provided in the data buffer. The decoding system according to any one of claims 1 to 4, wherein the decoding system is installed on an input side. 6. A feedback shift register for performing respective parallel processes, an input signal line for coefficient data of an error locator polynomial, a selector for selecting the input signal line and received signal data, and a mode setting for controlling the selector. 5. The decoding system according to claim 4, wherein the register and the decoder are installed to perform the syndrome generation and the Chien search, and the parallel syndrome generation processing for a plurality of received signals.