JPH0816512A - Communication interface - Google Patents

Abstract

PURPOSE:To quickly perform communication between an information processor having a high-speed serial bus and a peripheral device having a SCSI bus. CONSTITUTION:A serial controller 24 communicates with a computer 1 having a high-speed serial bus through the high-speed serial bus, and a SCSI controller 25 communicates with a peripheral device 3 has SCSI interface through the SCSI bus. A CPU 21 controls the SCSI controller 25 in accordance with data from the computer 1 received by the serial controller 24 and controls the serial controller 24 in accordance with data from the peripheral device 3 received by the SCSI controller 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device having a serial bus, such as a portable (small) computer, and a SCSI (Small Computer System Interfac).
e) A bus, such as a hard disk drive or a CD-
The present invention relates to a communication interface suitable for use when connecting to a peripheral device such as a ROM device.

[0002]

2. Description of the Related Art In recent years, for example, RS is used in so-called personal computers (personal computers) and word processors.
232C (RS-232C) medium and low speed (for example, 1
A serial bus (serial interface) of 200 to 19,200 bps) is provided as a standard. This serial bus is usually used for communication between a computer and its peripheral devices such as a modem and a printer (serial printer).

The types of buses for connecting a computer and peripheral devices are roughly classified into parallel buses in addition to the serial buses described above. The serial bus has a smaller number of signal lines required for communication (data transmission) than the parallel bus, so the cable connecting the serial buses can be made thin, and its handling (routing) Is easy.
Furthermore, the connector can be small. (2) According to the standard, the cable connecting the serial bus can be extended around (the cable length can be increased). There are advantages such as.

In a small (portable) information processing device such as an electronic notebook device or a so-called notebook computer, the serial connector is more serial than the parallel bus because the connector is small as described above. Buses are often provided.

By the way, recently, due to the development of device technology and the use of balanced transmission, a serial bus (high-speed serial bus) capable of performing communication at a transmission speed of a dozen Mbps, that is, at a high speed has been realized.

However, since the transmission speed of the serial bus has recently been improved and most of the standards are proprietary to the manufacturer, peripheral devices having a high-speed serial bus have hardly been realized. Is the current situation. In addition, some manufacturers manufacture and sell their own peripherals with their own standards. However, because of the high development cost of such peripherals at the moment, the price is also low. It is expensive and often cannot connect to computers of other manufacturers.

[0007]

On the other hand, as the processing capacity of a portable computer is improved, the amount of data handled by the portable computer is also increasing. It has become necessary to use a secondary storage device (for example, a hard disk device or a CD-ROM device).

As a communication interface of a secondary storage device such as a hard disk device or a CD-ROM device, SCSI (Small Computer) of the above-mentioned parallel buses is used.
System Interface) bus is the mainstream at the moment, and this is an 8- or 9-bit (book) data line,
It consists of 9 control signal lines and other signal lines, and the total number of the signal lines is usually 50 (depending on the manufacturer, the total number of the signal lines is set to 25 to save the number of cores). There are some).

According to the SCSI bus, high-speed communication is possible, but unlike the serial bus, its connector is large and its cable is thick, so that it is difficult to handle (route) the SCSI bus. Are usually used in stationary (desktop) computers.

Therefore, if a computer is provided with a SCSI connector in order to transfer and store data at high speed from a small computer to the above-mentioned secondary storage device, the device becomes large. there were.

Further, conventionally, a small-sized computer having a serial bus (medium-low speed serial bus) is connected to a stationary computer (built-in or connected to the stationary computer via the serial bus. Data may be transferred to and stored in a hard disk drive, etc.).
There was a problem that it took time to transfer data.

The present invention has been made in view of the above circumstances, and is made up of an information processing device such as a small computer having a high-speed serial bus and a peripheral device such as a secondary storage device having a SCSI bus. It enables high-speed communication between the two.

[0013]

A communication interface of the present invention is connected between an information processing device having a high-speed serial bus and a peripheral device having a SCSI (Small Computer System Interface) bus, and communicates between them. A communication interface for controlling, which communicates with a peripheral device via a SCSI bus and a serial bus communication means (for example, the serial controller 24 shown in FIG. 1) that communicates with an information processing device via a serial bus. In accordance with the SCSI bus communication means (for example, the SCSI controller 25 shown in FIG. 1) to be executed and the data from the information processing device received by the serial bus communication means, the SC
Control means for controlling the SI bus communication means and control means for controlling the serial bus communication means in response to the data from the peripheral device received by the SCSI bus communication means (for example, the CPU 21 shown in FIG. 1). Is characterized by.

In this communication interface, the information processing apparatus makes an inquiry to the control means through the serial bus communication means about the phase of the SCSI bus state, and communicates with the serial bus communication means in response to the inquiry. In response to the inquiry about the phase from the information processing device, the control means may cause the SCSI bus communication device to check the phase and notify the information processing device via the serial bus communication device. .
The information processing device and the serial bus communication means are RS232.
Communication based on the C or RS422 standard can be performed.

[0015]

In the communication interface having the above structure,
The serial controller 24 communicates with the information processing device via a high-speed serial bus, and the SCSI controller 25 communicates with peripheral devices via the SCSI bus.
Then, the CPU 21 responds to the data from the information processing device received by the serial controller 24 in response to S
Controls the CSI controller 25 and
The serial controller 24 is controlled according to the data from the peripheral device received by the controller 25.
Therefore, an information processing device having a high-speed serial bus,
High-speed communication can be performed with a peripheral device having a SCSI bus.

[0016]

1 shows an example of the configuration of a computer system in which a computer 1, a peripheral device 3 and other peripheral devices (not shown) are connected by a conversion interface 2 to which the present invention is applied. In this computer system, the computer 1 and the conversion interface 2 are high-speed serial buses (cables connecting high-speed serial buses), and the conversion interface 2 and peripheral devices (SCSI devices) 3 are SCSI buses (SC
Cables that connect SI buses to each other). Although not shown, other peripheral devices (SCSI devices) are connected to the series by a SCSI bus, if necessary, after the peripheral device 3. However,
Here, in the following description, only the peripheral device 3 is connected as the SCSI device.

The computer 1 includes a CPU 11 and a ROM 1
2, a RAM 13, and a serial controller 14, which are connected to the system bus. The computer 1 includes a CPU 11, ROM 12, RA
In addition to the M13 and the serial controller 14, a display unit (for example, a display) for displaying images and characters, and an input unit (for example, a keyboard and a mouse) for inputting commands and necessary data are included. The illustration is omitted.

The ROM 12 stores a system program. The RAM 13 stores an application program or data necessary for the operation of the CPU 11. Further, in the RAM 13, a transmission buffer for temporarily storing data (packets) to be transmitted to the conversion interface 2, a reception buffer for receiving data (packets) transmitted from the conversion interface 2, and data received by the reception buffer. A storage area is secured as a packet queue for temporarily storing packets in the form of packets.

The CPU 11 is adapted to perform processing in accordance with a system program stored in the ROM 12 and an application program stored in the RAM 13. Further, when there is data to be transmitted to the conversion interface 2 (CPU 21) or the peripheral device 3, the CPU 11 sets (stores) the data (packet) in the transmission buffer of the RAM 13 and causes the serial controller 14 to store the data. , To the conversion interface 2. Further, when the data (packet) from the conversion interface 2 is received by the serial controller 14 and stored in the reception buffer of the RAM 13, the CPU 11 sets it in the packet queue and sets (stores) it in the packet queue. The packet is read and the processing corresponding to the content of the packet is performed.

The application program stored in the RAM 13 controls the serial controller 14 to convert the conversion interface 2 (serial controller 2).
4) includes a communication program for communicating with.

The serial controller 14 has a high-speed serial bus (for example, one complying with the RS232C or RS422 standard), and data is bidirectionally (half-duplex or full-duplex) via the serial bus. It is designed to be able to communicate. The data communication unit is, for example, 1 byte (8 bits) or 1 octet. Further, the serial controller 14 converts parallel data to be transmitted (format data that can be handled by the CPU 11) into serial data, and also converts serial data received from the conversion interface 2 into parallel data. Is also done.

In FIG. 1, the serial controller 1
4 is connected to the serial controller 24 of the conversion interface 2 via a high-speed serial bus,
Exchange data at high speed. That is, when the data (packet) is set (stored) in the transmission buffer of the RAM 13, the serial controller 14 transfers the packet to the serial controller 24 at high speed. Further, when data (packet) is transferred from the serial controller 24 at high speed, the serial controller 14 sends the data forming the packet,
After all the data forming the packet is stored in the reception buffer of the RAM 13 sequentially, the packet formed of the data is transferred to the packet queue of the RAM 13 and stored therein.

In addition, when the serial controller 14 receives data from the conversion interface 2, the serial controller 14 informs the CPU 11 that the data has been received by, for example, issuing a reception interrupt. Further, the serial controller 14 is connected to the conversion interface 2 connected via the serial bus in an emergency (for example, when an error that cannot continue processing occurs) even during the transmission and reception of data. To
When an exception interrupt for notifying this is requested, and when an exception interrupt is requested from the conversion interface 2, processing according to the request is also performed. However, the serial controller 14 may not be able to perform processing related to exception interrupt.

The conversion interface 2 includes a CPU 21,
ROM22, RAM23, serial controller 24,
And a SCSI controller 25, which are connected to the system bus. The ROM 22 stores a system program. The RAM 23 stores an application program, or the CPU 2
The data required for the operation of No. 3 are stored. Furthermore, RAM2
3 is a peripheral device 3 via the SCSI controller 25.
It is also made to temporarily store the data transmitted from. Further, the RAM 23 has a transmission buffer for temporarily storing packets to be transmitted to the computer 1, a reception buffer for receiving packets transmitted from the computer 1, and data received by the reception buffer in the form of packets. A storage area as a packet queue for temporarily storing the data is secured.

The CPU 21 is adapted to perform processing in accordance with the system program stored in the ROM 22 and the application program stored in the RAM 23.

The application program stored in the RAM 23 controls the serial controller 24 to communicate with the computer 1 (serial controller 14) and the SCSI controller 25 to control the peripheral device 3 (and When other peripheral devices are connected to the subsequent stage of the peripheral device 3, the peripheral device includes a peripheral device) and a communication program for communicating.

The CPU 21 performs processing according to these communication programs to convert the data (data (packet) described later with reference to FIG. 3) from the computer 1 (serial controller 14) received by the serial controller 24. Correspondingly, while controlling the SCSI controller 25, the SCSI controller 25
The serial controller 24 is controlled in response to the data (such as data notifying a phase described later) received from the peripheral device 3.

Specifically, for example, the computer 1 is an SCS that connects the conversion interface 2 and the peripheral device 3.
The CPU 21 is inquired of the phase that is the state of the I bus via the serial controller 24 (serial controllers 14 and 24), and in response to the inquiry, the response is sent (via the serial controller 14).
Communication is performed with the serial controller 24. In this case, the CPU 21 controls the SCSI controller 25 in response to the phase inquiry (data (packet) instructing the phase inquiry) from the computer 1, Ask them to examine the phase. And SCSI
As a result of checking the current phase from the controller 25, that is, when data (packet) notifying the phase is returned, the CPU 21 controls the serial controller 24 in accordance with the data, and the computer 1 is notified of the above-mentioned phase. Make a response to the inquiry (CPU2
1 informs the computer 1 of the phase).

The CPU 21 communicates with the computer 1 by controlling the serial controller 24 as follows. That is, the CPU 21
When there is data to be transmitted to the computer 1 (for example, data received from the peripheral device 3), the RAM 2
The data is set (stored) in the transmission buffer of No. 3, and the serial controller 24 is caused to transfer the packet of the data to the computer 1. Furthermore, C
PU21 is data (packet) from the computer 1.
Is received by the serial controller 24, stored in the reception buffer of the RAM 23, and then formed into a packet,
When the packet is set (stored) in the packet queue, the packet is read and the process corresponding to the content of the packet is performed.

The serial controller 24 is connected to the serial controller 14 via a high-speed serial bus and has the same structure as that. Therefore, the computer 1 (serial controller 14) and the conversion interface 2 (serial controller 24) communicate with each other in accordance with the standards such as RS232C and RS422. The serial controller 24 is the RAM 23.
When a packet is set (stored) in the transmission buffer of, the packet is transferred to the serial controller 14 at high speed, and when data (packet) is transferred from the serial controller 14, The data making up the packet is sequentially stored in the reception buffer of the RAM 23, and after all the data making up the packet is stored, the packet made up of the data is put in the RAM 23.
It is transferred to the packet queue and stored.

The SCSI controller 25 has an input / output interface conforming to the SCSI standard, and a peripheral device 3 such as a secondary storage device (for example, a CD-ROM device or a magnetic disk device), and a SCSI bus. Connected to the peripheral device 3 and SCSI.
Communication at high speed is performed according to the control procedure of. And
The CSCI controller 25, under the control of the CPU 21,
The data received from the peripheral device 3 is transferred to and stored in the transmission buffer of the RAM 23, and the data stored in the packet queue of the RAM 23 is transmitted to the peripheral device 3.

From the above, it can be said that the conversion interface 2 is an interface for converting the communication protocol of the computer 1 or the peripheral device 3 so that they can communicate with each other. Further, the computer 1 and the conversion interface 2 communicate at high speed via a serial bus, and the conversion interface 2
And the peripheral device 3 communicate at high speed via the SCSI bus, so that the computer 1 and the peripheral device 3 can communicate at high speed via the conversion interface 2.

That is, for example, the computer 1 and the peripheral device 3
Even when a large amount of data is exchanged between the and, the data can be transferred in a short time. Further, since it is not necessary to provide the computer 1 with a large connector for SCSI, it is possible to prevent the computer 1 from becoming large even if it is portable (small).

In order to prevent the computer 1 from increasing in size, the computer 1 is provided with a reduced SCSI connector, and the peripheral device 3 is provided with a reduced SCSI connector and a normal SCSI connector. Although there is a method of connecting with a conversion cable that has, the SCSI bus needs to be able to pass a current of 48 mA in the signal line in the worst case according to its standard.
If the computer 1 is small, it usually
Batteries or batteries are often used as the power source. Therefore, when a large current of 48 mA is supplied from the battery or battery that is the power source, the usage time of the computer 1 is shortened.

Therefore, the conversion interface 2 can be powered independently or from the peripheral device 3. In this case, it is not necessary to take power from the computer 1 for the conversion interface 2. For example, when the computer 1 is portable (small size) and uses a battery as a power source, the conversion interface 2 is not used. Since it is used, it is possible to prevent the use time from being shortened.

Next, the conversion interface 2 (SCSI
SC performed between the controller 25) and the peripheral device 3
The SI communication procedure will be described. S such as peripheral device 3
A peripheral device having an input / output interface conforming to the CSI standard (hereinbelow, referred to as a SCSI device as appropriate) is used as a conversion interface 2 (or SC
When connecting to a computer having an SI bus), a unique ID number is set in advance. ID
The numbers are, for example, numbers in the range of 0 to 7. Therefore, the conversion interface 2 includes seven SCSI devices (the conversion interface 2 (SCSI controller 25) is also a SCSI device, so the above eight ID numbers are used). One of them is assigned to conversion interface 2)
It is possible to connect up to a series.

In SCSI, for example, when a certain series of information (data) is exchanged without a master-slave relationship in which the conversion interface 2 (SCSI controller 25) is a parent and the peripheral device 3 is a child (communication When performing a command), the side that sends a command is called the initiator, and the side that receives the command and performs processing according to the command, such as sending data, is called the target. There are several states on the SCSI bus,
It is called a phase as described above.

FIG. 2 shows an example of phase changes (transitions) when communication is performed via the SCSI bus.
In FIG. 2, the conversion interface 2 (SCSI controller 25) or the peripheral device 3 serves as an initiator or a target, respectively, and a phase change when data is read (transferred) from the peripheral device 3 to the conversion interface 2 is shown. Shows.

(1) In the bus free phase, the SCSI bus is not used by any SCSI device. The SCSI controller 25 of the conversion interface 2, which is the initiator, confirms this state before the SCSI Go to get the right to use the bus.

(2) The arbitration phase is S
The right to use the CSI bus is assigned to SCSI devices (2 or more SCS
If there is a competition for usage rights in a state where I equipments) are competing with each other, for example, a larger SC of the above-mentioned ID number is used.
The SI device (hereinafter, appropriately referred to as a high-priority SCSI device) acquires the right to use the SCSI bus. The SCSI device that has acquired this usage right becomes an initiator. Here, the SCSI controller 25 is assumed to be the initiator.

(3) The selection phase is a state in which the SCSI device that has acquired the right to use the SCSI bus in the arbitration phase, that is, the initiator, designates a target to communicate with. In this case, the SCSI controller 25 that has become the initiator. Specifies the peripheral device 3 as the target. Note that, hereinafter, a state in which the initiator succeeds in designating the target is referred to as “I (initiator) -T (target) nexus” is appropriately established.

(4) The message out phase is a phase in which 1-byte unit data called a message is transferred from the initiator to the target.
It is possible to transfer not only one message but a plurality of messages in succession. Here, the SCSI controller 2
It is assumed that a so-called identify message (normally, a message sent from the initiator to the target at a predetermined timing in the message out phase) is transferred from the device 5 to the peripheral device 3. Note that this phase may be omitted.

(5) The command phase is a phase in which a command (instruction) is sent from the initiator to the target. Here, it is assumed that a read command (READ command) that is a command instructing to read data from the peripheral device 3 is sent from the SCSI controller 25 to the peripheral device 3.

(6) (7) The message in phase is
In the phase in which a message is sent from the target to the initiator, as in the case of the message out phase described above, it is possible to send not only one message but a plurality of messages in succession. Here, it takes time to search the data specified by the READ command from the target peripheral device 3 to the initiator SCSI controller 25, so that data to be transferred is transferred in the message in phase of (6). RA to remember
Address of M23 (If data is being transferred, the address of RAM23 that stores the data just transferred)
Save Dat is a message that instructs you to remember
A Pointer message is sent, and Disconne instructing to disconnect once in the message in phase of (7).
A ct message shall be sent.

After the Disconnect message is sent from the peripheral device 3 to the SCSI controller 25, the connection between them is cut off, and the (8) bus free phase is entered. As described above, the bus free phase is a state where the SCSI bus is not used, and therefore, during this bus free phase, another SCSI device (if there is another SCSI device) uses the SCSI bus. be able to. Also,
The SCSI device (here, the SCSI controller 25) that has become the initiator in (2) can perform other processing.

After that, when the data to be transferred is prepared in the peripheral device 3 which is the target in (3),
(9) Arbitration phase. here,
The target peripheral device 3 acquires the right to use the SCSI bus. In this case, when another SCSI device is using the SCSI bus, the target (peripheral device 3) waits until the session ends. In addition to the target (peripheral device 3), the SCSI device with higher priority than
The target (peripheral device 3) also waits until the session ends even when it participates in the acquisition of the I-bus.

When the peripheral device 3 acquires the right to use the SCSI bus, the (10) reselection phase is entered. (1
0) In the reselection phase, the target specifies (selects) the initiator, and here the peripheral device 3 specifies the SCSI controller 25. This establishes the IT nexus again.

(11) The message-in phase is a phase in which a message is sent from the target to the initiator as described above, and here, the peripheral device 3 sends an SCS message.
It is assumed that the Identify message is sent to the I controller 25.

(12) The data-in phase is a phase in which the data specified by the READ command is transferred from the target to the initiator.
The data is sent to the CSI controller 25. In addition,
In this case, when the amount of data to be transferred is large and the SCSI bus is likely to occupy for a long time, the peripheral device 3 which is the target judges this and repeats the phases (6) to (12). SCSI controller 2
5, so to speak, data is intermittently transferred (FIG. 2 shows the case where the data transfer is completed once).

(13) In the status phase, the target sends the status information, which is the execution result of the process corresponding to the command from the initiator, to the initiator. Here, the peripheral device 3 sends the status information to the SCSI controller 25. Good indicating that the data transfer was successful
Status shall be sent. The phase is
By shifting (transitioning) from the data-in phase (12) to this status phase, the SCSI controller 25, which is the initiator, recognizes that the data transfer has ended.

After that, the process transits to (14) message in phase. Here, from the peripheral device 3 which is the target to the SCSI controller 25 which is the initiator,
A Command Complete message (command complete message) indicating that the process corresponding to the READ command, that is, the data transfer process has been completed is sent. Then, the process returns to the initial state (15) bus-free phase.

Peripheral device 3 to SCSI controller 25
The transfer of data to and from is performed through the phase changes (transitions) described above. After the right to use the SCSI bus is acquired in the arbitration phase and the IT nexus is established in the selection phase (reselection phase), the target (not the initiator) takes the initiative on the SCSI bus and To transition.

Next, data exchanged between the computer 1 (serial controller 14) and the conversion interface (serial controller 24) via the serial bus will be described. Data is packetized and transmitted between the computer 1 and the conversion interface 2. Each packet has a format in which the content of the first byte is determined by the first byte, and is byte-aligned.

FIG. 3 shows the types of packets transmitted from the computer 1 to the conversion interface 2 and their formats. As shown in the figure, the packet includes a SCSI command (SCSI Command), SCSI data (SCSI Data), and a SCSI message (SCSI Messag).
There are five types: e), converter command, and converter data.

The SCSI command, SCSI data, or SCSI message is sent to the SCSI controller 25.
Are used to transmit commands, data (other than commands and messages) or messages in SCSI to the peripheral device 3, respectively.
Also, the converter command or converter data is
It is used when transmitting a command or data to the CPU 21.

In the first byte (0th byte) of each packet, a hexadecimal identifier (packet identifier) representing the type of the packet is described. Here, SCSI
00h to 02h (h indicates hex) is assigned as an identifier to each of the command, the SCSI data, and the SCSI message. Further, 80h to ffh are assigned to the converter command as identifiers corresponding to the commands to the CPU 21. Furthermore, 7fh is assigned to the converter data as an identifier.

Therefore, the type of each packet can be recognized only by looking at the leading 1 byte. That is, the first 1 byte of the packet is 00h, 01h, 02h,
Or 7fh, it can be seen that the packet is a SCSI command, SCSI data, SCSI message, or converter data, respectively.
The first 1 byte of the packet is 80h to ffh.
If the value is any of the values in the range, it means that the packet is a converter command.

The packet length is described in the first byte (second byte from the beginning) of the SCSI command. The packet length described in the packet is a data length in bytes, excluding the packet length itself and the identifier of the packet. Now, the SCSI command is n + 1 of the 0th to nth bytes. When the packet is composed of bytes, the packet length is n−1 since it is the part of the 0th to nth bytes excluding the 0th and 1st bytes, that is, the 2nd to nth bytes.

SCSI commands (SCSI commands) are described in the second to nth bytes (third to nth byte from the beginning) of the SCSI command. So in this case,
The value of n will depend on the length of the SCSI command described therein.

Next, the packet length is described in the first to third bytes (2nd to 4th bytes from the beginning) of the SCSI data. As described above, the packet length described in the packet is the data length excluding the packet length itself and the identifier of the packet in byte units. When the packet length is composed of n + 1 bytes of n bytes, the packet length is a portion except the 0th to 3rd bytes from the 0th to nth bytes, that is, the 4th to nth bytes.
It becomes n-4. The first to third bytes of the SCSI data describe the lower 8 bits, the middle 8 bits, or the upper 8 bits of the packet length, respectively. SC
Three bytes (1st to 3rd bytes) are used to represent the packet length of SI data, which means that SCSI data (other than commands and messages) is usually This is because the amount of data is large.

In the 4th to nth bytes (5th to nth bytes from the beginning) of the SCSI data, the SCSI data (S
CSI data) is described. Therefore, in this case, the value of n depends on the length of the SCSI data described therein.

The packet length is described in the first byte of the SCSI message, and the SCSI message (SCSI message) is described in the second to nth bytes. Therefore, in this case, the value of n depends on the length of the SCSI message described therein.

The first to nth bytes of the converter command correspond to the identifier described in the 0th byte,
The operand of the command of the CPU 21 is described. Therefore, in this case, the value of n depends on the length (number) of the operand of the command described therein.

The packet length is described in the first byte of the converter data, and the second to nth bytes thereof are
Data for the CPU 21 is described. Therefore, in this case, the value of n depends on the length of the data described therein.

FIG. 4 shows the types of packets transmitted from the conversion interface 2 to the computer 1 and their formats. As shown in the figure, the packet includes SCSI data (SCSI Data), SCSI message (SCSI Message), and SCSI status (SCSI Status).
tus), Converter Message,
There are five types of data and converter data.

The SCSI data, SCSI message, or SCSI status is displayed by the SCSI controller 25.
SCSI data from peripheral device 3 (other than messages and status), messages, received by
Alternatively, it is used when each status (status information) is transmitted to the computer 1. Also,
The converter message or converter data is CP
Used when transmitting a message or data to the CPU 11 from the U21.

As in the case of FIG. 3, in FIG. 4 as well, in order to recognize the type of each packet only by looking at the leading 1 byte, the leading 1 byte (0th byte) is set. Indicates a hexadecimal identifier (packet identifier) indicating the type of the packet. Here, SCSI data, SCSI message, SCSI
01h to 04h or 7f for status, converter message or converter data respectively
h is assigned as the identifier.

The SCSI data, SCSI message, or converter data in FIG. 4 has the same format as that shown in FIG.

The SCSI status is a 2-byte packet, and a 1-byte code representing the status transmitted from the peripheral device 3 is described in the first byte (second byte from the beginning) of the packet. As described above, the SCSI status is determined to be a 2-byte packet, so
Its packet length is not described.

In the second to nth bytes of the converter message, a message (interface message) from the CPU 21 to the CPU 11 is described. Therefore, in this case, the value of n will depend on the length of the message described therein.

Next, FIG. 5 shows a computer 1 (CPU1
It is a flow chart explaining processing of 1). In the computer 1, first in step S1, the RAM 13 is initialized along with the initialization process of the serial controller 14.
A storage area as a transmission buffer, a reception buffer, and a packet queue is secured in step S2, the process proceeds to step S2, and if a packet is stored in the transmission buffer of the RAM 13, the packet is transferred by the serial controller 14 to It is transmitted to the conversion interface 2 (serial controller 24).

Data to be transmitted to the conversion interface 2 (or the peripheral device 3 via the conversion interface 2) (this is the SCS in FIG. 3 described above).
If there is data in a broad sense including an I command, etc.), the data is R
It is set in the transmission buffer of the AM 13 and formed into a packet.

In step S2, as described above, R
When the packet is stored in the transmission buffer of the AM 13, the serial controller 14 transmits the packet to the conversion interface 2 (serial controller 24).

Then, in step S3, the RAM 13
It is determined whether or not a packet (a packet transmitted from the conversion interface 2 in step S102 of FIG. 8 to be described later) (any kind of packet shown in FIG. 4) is stored in the packet queue of FIG. When it is determined in step S3 that there is a packet in the packet queue, the process proceeds to step S4, the CPU 11 reads the packet from the packet queue, performs processing according to the content of the packet, and then executes step S5. Proceed to.

On the other hand, if it is determined in step S3 that there are no packets in the packet queue, step S5
And an exception flag is set (eg 0 and 1
It has become 1) of the above).

Here, the exception flag is normally 0 of 0 and 1, and the serial controller 24
Is set to 1 in step S14 of FIG. 6, which will be described later, when an exceptional interrupt is applied to the computer 1. The exception flag is RAM1
3 is stored in a predetermined area.

When it is determined in step S5 that the exception flag is set, the process proceeds to step S6, an exception process for handling the cause of the exception interrupt is performed, and the process proceeds to step S7. Step S
If it is determined in step 5 that the exception flag is not set, step S6 is skipped, the process proceeds to step S7, and if there is data to be transmitted to the conversion interface 2 by the CPU 11, the data is stored in the RAM.
Processing such as storing in the transmission buffer 13 to form a packet, and other processing (work) are performed, and the process returns to step S2.

Therefore, in the computer 1, the processes of steps S2 to S7 are repeated thereafter.

When the CPU 11 is interrupted while the processing of steps S2 to S7 is being performed, C
The PU 11 performs interrupt processing according to the flowchart shown in FIG.

That is, when an interrupt is applied, it is first determined in step S11 whether or not the interrupt is a reception interrupt issued by the serial controller 14. When it is determined in step S11 that the interrupt is not the reception interrupt, the process proceeds to step S13, and it is determined whether or not the interrupt is an exception interrupt. When it is determined in step S13 that the interrupt is the exception interrupt, the process proceeds to step S14, the exception flag is set, and the interrupt process ends.

If it is determined in step S13 that the interrupt is not the exception interrupt, that is, if the interrupt is other than the reception interrupt and the exception interrupt, the process proceeds to step S15 to process the interrupt. (Other interrupt processing) is performed, and the interrupt processing ends.

On the other hand, if it is determined in step S11 that the interrupt is a reception interrupt, step S11
In step 12, reception interrupt processing is performed, and the interrupt processing ends.

The flowchart of FIG. 7 shows the details of the reception interrupt processing in step S12 of FIG.
As described above, the reception interrupt is issued when the serial controller 14 receives the data from the conversion interface 2 (serial controller 24). Therefore, in step S21, the received data is the head of the packet. Data (1 byte data from the beginning of the packet (0th byte data of the packet)) is determined. When it is determined in step S21 that the received data is the head data of the packet, the process proceeds to step S22, and the type of the packet is determined (identified).

Here, as described above, the computer 1
Since the first byte of the packet exchanged between the packet and the conversion interface 2 represents the type of the packet, the determination in step S22 is performed by referring to the first byte of the packet which is the received data. Be seen.

In step S22, the type of packet formed by the received data is the SCSI shown in FIG.
When it is determined that the received data is the data, the SCSI message, the SCSI status, the converter message, or the converter data, the process proceeds to steps S23 to 27, the received data is stored in the reception buffer of the RAM 13, and the packet currently received. The type storage area, which stores the type of (the packet being processed) and which is secured in advance in the RAM 13, stores the type of the packet composed of the received data, and ends the reception interrupt process.

On the other hand, when it is determined in step S21 that the received data is not the data at the beginning of the packet, that is, the received data is the first byte (the second byte from the beginning) or later of the packet. In this case, the process proceeds to step S28, and the received data (the packet being processed) constitutes any kind of packet of the SCSI data, SCSI message, SCSI status, converter message, and converter data shown in FIG. Is determined. Here, this determination is performed by referring to the type storage area of the RAM 13 described above.

If it is determined in step S28 that the received data (packet being processed) is SCSI data, SCSI message, SCSI status, converter message, or converter data,
In any case, the process proceeds to step S29, and the received data is stored in the reception buffer of the RAM 13.

Then, in step S30, it is determined whether or not the data stored in the reception buffer of the RAM 13 in step S29 is the last data forming a packet.

Here, as shown in FIG. 4, when the packet transmitted from the conversion interface 2 to the computer 1 is SCSI data, the first to third packets are transmitted.
If the byte is a SCSI message, converter message, or converter data, its first
By referring to the byte, the packet length can be recognized, and when the packet is SCSI status, the packet length can be recognized as 2 bytes. Therefore, the determination in step S30 is made based on the data length stored in the reception buffer of the RAM 13 and the recognized packet length.

When it is determined in step S30 that the data stored in the reception buffer of the RAM 13 is not the last data forming the packet, step S31
And skip the reception interrupt. Further, when it is determined in step S30 that the data stored in the reception buffer of the RAM 13 is the last data forming the packet, all the data stored in the reception buffer, that is, the packet is the packet queue of the RAM 13. Is stored and registered (registered), and the reception interrupt process ends.

In the above reception interrupt processing, RAM
After the packet is stored in the packet queue of 13, the CPU 11 reads the packet from the packet queue in step S4 of FIG.
Processing is performed according to the contents of the packet.

Next, FIG. 8 shows the conversion interface 2
It is a flow chart explaining operation of (CPU21). In the conversion interface 2, first, in step S101, the serial controller 24 and S
RAM along with the initialization processing of the CSI controller 25
A storage area as a transmission buffer, a reception buffer, and a packet queue is secured in step 23, and step S10 is performed.
Then, the process proceeds to step 2, and the process of transmitting the packet to the computer 1 is performed.

That is, in step S102, as shown in the flowchart of FIG. 9, first, in step S111, it is determined whether or not a packet is stored in the transmission buffer of the RAM 23. When it is determined in step S111 that the packet is not stored in the transmission buffer of the RAM 23, step S112 is skipped, the packet transmission process ends, and the process proceeds to step S103 in FIG.

On the other hand, in step S111, the RAM
When it is determined that the packet is stored in the transmission buffer 23, the process proceeds to step S112, the serial controller 24 transmits the packet to the computer 1 (serial controller 14), and the packet transmission process ends. , Proceeds to step S103 in FIG.

Here, the data to be transmitted to the computer 1 (this includes the converter message and converter data transmitted from the CPU 21 and the peripheral device 3 received by the SCSI controller 25, as described with reference to FIG. 4). SCSI data, SCSI message,
And in the SCSI status), the data is RA
It is set in the transmission buffer of M23 and formed into a packet.

In the packet transmission process of step S102, the transmission buffer of the RAM 23 is stored in the RAM 23 as described above.
When the packet is stored, the serial controller 24 transmits the packet to the computer 1 (serial controller 14).

Then, the process proceeds to step S103 (FIG. 8) and the packet (packet transmitted from the computer 1 in step S2 of FIG. 5 described above) (packet of any kind shown in FIG. 3) is stored in the packet queue of the RAM 23. )
Is stored. Step S10
3, it is determined that there is a packet in the packet queue of the RAM 23, the process proceeds to step S104 and CP
The U21 reads the packet from the packet queue, and performs processing according to the content of the packet.

That is, in step S104, as shown in the flowchart of FIG. 10, first, in step S121, the type (type) of the packet read from the packet queue of the RAM 23 is referred to by the leading 1 byte. It is judged (identified).

In step S121, the types of packets are the SCSI command (command for SCSI), SCSI data (data for SCSI), SCSI shown in FIG.
After it is determined that the packet is a message (SCSI message), converter command (converter command), or converter data (converter data), the process proceeds to step S122, and processing is performed according to the contents of the packet.

Specifically, a packet read from the packet queue of the RAM 23, that is, a packet transmitted from the computer 1 is a SCSI command or SCSI.
If it is one of the data and the SCSI message, the CPU 21 controls the SCSI controller 25 to cause the peripheral device 3 to transmit the data forming the packet (contents of the packet). If the packet transmitted from the computer 1 is a converter command or converter data, the CPU 21 performs a process according to the converter command or a predetermined process using the converter data, respectively.

After the above processing, the process proceeds to step S105 in FIG.

On the other hand, in step S103 of FIG.
When it is determined that there is no packet in the packet queue of the RAM 23, step S104 is skipped, the process proceeds to step S105, and the CPU 21 causes the computer 1
If there is data to be sent to
The processing of storing the data in the transmission buffer of the AM 23 to form a packet, the processing of causing the SCSI controller 25 to receive the data when the peripheral device 3 receives the data, and the other processing (work) are performed. Done,
It returns to step S102.

Therefore, the conversion interface 2 (CPU
In step 21), the processes of steps S102 to S105 are repeated thereafter.

While the processes of steps S102 to S105 are being performed, a packet is transmitted from the computer 1 (serial controller 14), and the serial controller 24 issues a reception interrupt to the CPU 21. The reception interrupt processing is performed according to the flowchart shown in FIG.

That is, when a reception interrupt is applied, first in step S131, the reception buffer of the RAM 23
The data forming the packet transmitted from the computer 1 (serial controller 14) is stored, and the process proceeds to step S132, where the data currently stored in the reception buffer of the RAM 23 is the data at the beginning of the packet (1 from the beginning of the packet). It is determined whether or not it is the byte data (0th byte data of the packet). When it is determined in step S132 that the data currently stored in the reception buffer of the RAM 23 is the head data of the packet, the process proceeds to step S133, and the packet is a converter command (converter command). It is determined by referring to the 1-byte data at the head of the packet stored in the reception buffer of the RAM 23.

If it is determined in step S133 that the type of packet formed by the data stored in the reception buffer of the RAM 23 is the converter command (command for converter), the process proceeds to step S135 and the reception of the RAM 23 is performed. Data stored in the buffer (1st byte data from the beginning of the packet (0th packet
(Byte data)), the packet length of the packet composed of the data, that is, the packet length of the converter command is determined (determined), is set in a variable PLen (a part of the storage area of the RAM 23), and the processing ends. .

Here, the packet length of the converter command can be recognized as follows. That is, FIG.
As shown in (1), in the first byte (0th byte of the packet) of the converter command from the computer 1, any value in the range of 80h to ffh is described corresponding to the command to the CPU 21. Also, CP
Operands added to each command for U21 are
Since it is predetermined by the command, the packet length of the converter command can be known by referring to the data of the first byte (0th byte) from the beginning of the converter command.

On the other hand, in step S133, the RAM
When it is determined that the type of the packet composed of the data stored in the receive buffer 23 is not the converter command (instruction for converter), that is, the type of the packet is the SCSI command (shown in FIG. 3). SCSI
Command), SCSI data, SCSI message, and converter data, the process proceeds to step S134, and the data stored in the reception buffer of the RAM 23 (the first byte of the packet (the first byte of the packet) From 0 bytes of data)), the packet length of the packet composed of that data is described.
The length of the packet area (designated field) is determined (determined), and is set in the variable PFLen (a part of the storage area of the RAM 23), and the processing is ended.

Here, the packet area in which the packet length of the SCSI command, the SCSI data, the SCSI message, or the converter data is described can be recognized as follows. That is, as shown in FIG. 3, the packet transmitted from the computer 1 is
When it is a SCSI command, SCSI data, SCSI message, or converter data, its packet length is the first byte, the first to third bytes, and the first byte, respectively.
It is described in the byte or the first byte. Therefore,
From the data stored in the reception buffer of the RAM 23 (the data of the first byte from the head of the packet (the data of the 0th byte of the packet)), a packet composed of the data is a SCSI command, SCSI data, a SCSI message, and By determining which of the converter data is, the length (the number of bytes) of the packet area (field) in which the packet length is described can be known.

Specifically, if the packet type is SCSI
If it is a command, SCSI data, SCSI message, or converter data, the variable PFLen contains
1, 3, 1 or 1 will be set respectively.

On the other hand, in step S132, the RAM
If it is determined that the data currently stored in the reception buffer 23 is not the data at the beginning of the packet, that is, if the data is the data of the first byte or later of the packet, the process proceeds to step S136 Whether or not the packet constituted by is a converter command (converter command) is determined in the same manner as in step S133.

In step S136, when it is determined that the packet composed of the data stored in the reception buffer of the RAM 23 is not the converter command, that is, the packet is the SCSI command, SCS.
If it is one of the I data, the SCSI message, and the converter data, the process proceeds to step S137, and the field in which the packet length is described is already received, and the packet length is obtained in step S139 described later. It is determined whether or not (calculated).

In step S137, the packet (SCSI command, SCSI data, SCSI
If it is determined that the packet length of the message or the converter data) has not yet been calculated, the process proceeds to step S138, and whether there is PFLen + 1 bytes of data in the reception buffer of the RAM 23 (already stored). Has been performed) or not. In step S138, P is stored in the reception buffer of the RAM 23.
If it is determined that there is no FLen + 1 byte worth of data, step S139 is skipped and the reception interrupt processing ends.

In step S138, the RAM
When it is determined that the reception buffer 23 has PFLen + 1 bytes of data, the process proceeds to step S139.
From that data, packet length (total length of packet)
Is calculated (calculated), and the reception interrupt process ends.

That is, the packet is a SCSI command, S
In the case of CSI data, SCSI message, or converter data, as shown in FIG. 3, the packet identifier and the packet length are sequentially described in the range of PFLen + 1 bytes from the beginning. Therefore, in steps S138 and S139, when the reception buffer of the RAM 23 has data of PFLen + 1 bytes, the packet length described in the range (this packet length is described as described above). The length of the entire packet is obtained based on the number of bytes of the area and the number of bytes of the area in which the identifier is described, excluding the number of bytes of the entire packet).

The obtained packet length (total packet length) is set in the variable PLen.

On the other hand, in step S137, the RAM
A packet composed of the data that has just been stored in the reception buffer of 23 (SCSI command, SCSI data, S
If it is determined that the packet length of the CSI message or the converter data) has already been calculated, that is, if the packet length has been calculated in step S139 and set in the variable PLen, step S140. Then, it is determined whether all the data forming the packet transmitted from the computer 1 are stored in the reception buffer of the RAM 23 (the entire packet is received).

Here, this determination is made by using the data length (the number of bytes) stored in the reception buffer of the RAM 23 and the variable PL.
It is performed by comparing with the packet length (number of bytes) stored in en (if they match,
It is determined that the entire packet has been received, and if they do not match, it is determined that the entire packet has not been received).

If it is determined in step S140 that the entire packet has not been received, step S14
1 and S142 are skipped, and the reception interrupt process ends. If it is determined in step S140 that the entire packet is received, that is, if all the data forming the packet is stored in the reception buffer of the RAM 23, the process proceeds to step S141, and all the data stored in the reception buffer of the RAM 23 is stored. The data, or packet, is R
It is transferred to the packet queue of the AM 23 and stored (registered). Then, in step S142, the reception buffer of the RAM 23 is cleared (emptied), and the reception interrupt process ends.

On the other hand, in step S136, the RAM
When it is determined that the packet composed of the data stored in the reception buffer 23 is the converter command, the process proceeds to step S140, and the above-described process is performed.

When the packet composed of the data stored in the reception buffer of the RAM 23 is the converter command, the packet length is determined by step S13.
Since it is set to the variable PLen in 5, the above-mentioned determination process is performed using this in step S140.

In the above reception interrupt processing, RAM
After the packet is stored in the packet queue 23, in step S104 (FIG. 10) of FIG. 8 described above, C
The PU 21 reads the packet from the packet queue and performs processing according to the content of the packet.

Next, FIG. 12 shows the conversion interface 2
Between the (SCSI controller 25) and the peripheral device 3,
When the computer 1 receives the data read from the peripheral device 3 by performing the exchange described in FIG.
The interaction between the computer 1 and the conversion interface 2 is shown. That is, FIG. 12 shows an exchange between the computer 1 and the conversion interface 2 when the computer 1 reads data from the peripheral device 3 via the conversion interface 2.

In this case, as shown in the flow chart of FIG. 13, in the computer 1 (CPU 11), first in step S41, the conversion interface 2
The (SCSI controller 25) is inquired about the phase of the SCSI bus. (FIG. 12 (1)). Then, when a response to the inquiry is returned from the conversion interface 2 (FIG. 12 (2)), step S
Proceeding to 42, it is determined whether the response indicates a bus free phase. In step 42,
When it is determined that the response to the inquiry does not indicate the bus free phase, the process returns to step S41.

If it is determined in step S42 that the response to the inquiry indicates the bus free phase, the process proceeds to step S43, and the conversion interface 2 is directed to the target SCSI device (in this case, the peripheral device). An instruction is given to select the device 3) (a packet of a converter command (FIG. 3) instructing the selection of the peripheral device 3 is transmitted from the computer 1 to the conversion interface 2) (FIG. 12 (3)).

Then, in step S44, it is determined whether or not the peripheral device 3 has been selected successfully. Here, the conversion interface 2 (CPU 21) outputs a converter message indicating whether or not the peripheral device 3 has been selected successfully to the computer 1 (FIG. 12).
(4)), the determination in step S44 is performed by referring to this converter message.

If it is determined in step S44 that the selection of the peripheral device 3 has not succeeded, that is, if the selection of the peripheral device 3 fails due to some error, the process proceeds to step S45 to recover the error. Error processing is performed. Then, the process proceeds to step S46, and it is determined whether or not the error can be retried. If it is determined in step S46 that the error can be retried, step S41
Return to If it is determined in step S46 that the error cannot be retried, the process ends.

On the other hand, if it is determined in step S44 that the peripheral device 3 has been selected successfully, step S47
Then, after waiting for the change of the current phase (selection phase) of the SCSI bus, the inquiry of the phase after the change is performed (FIG. 12 (5)). Then, when the response to the inquiry is returned from the conversion interface 2 ((6) in FIG. 12), the process proceeds to step S48, and it is determined whether or not the response indicates the message out phase. In step S48,
When it is determined that the response to the inquiry indicates the message out phase, the process proceeds to step S49, and the conversion interface 2 is instructed to transmit the Identify message to the peripheral device 3 (Id
A packet of a SCSI message (FIG. 3) containing the entify message is transmitted from the computer 1 to the conversion interface 2 (FIG. 12 (7)), step S5.
Go to 1.

On the other hand, when it is determined in step 48 that the response to the inquiry does not indicate the message out phase, the process proceeds to step S50, and it is determined whether or not the response indicates the command phase. . If it is determined in step S50 that the response to the inquiry does not indicate the command phase, that is, if the response does not indicate any one of the message out phase and the command phase, the process proceeds to step S45. Hereinafter, the above-mentioned processing is performed.

When it is determined in step S50 that the response to the inquiry indicates the command phase, the process proceeds to step S51, and a READ command is sent to the peripheral device 3 to the conversion interface 2. An instruction is given (a packet of a SCSI command (FIG. 3) containing a READ command is transmitted from the computer 1 to the conversion interface 2) (FIG. 12)
(8)), and proceeds to step S52.

In step S52, the current SCS
Waiting for a change in the I-bus phase (command phase), the process proceeds to step S53, and the phase after the change is
It is determined which of the message-in phase, the data-in phase, the status phase, and the other phases (other phases).

When it is determined in step S53 that the phase is the message-in phase, the message (Save Data Pointer message) is transmitted to the peripheral device 3 in the message-in phase as described with reference to FIG.
To conversion interface 2 (SCSI controller 2
5), the message is converted into a packet (packet of SCSI message) and transmitted from the conversion interface 2 (FIG. 12 (9)), and in step S61 shown in FIG. Received (captured).

Then, in step S62, it is determined whether or not the message is a Save Data Pointer message. In step S62, step S6
When it is determined that the message received in 1 is not the Save Data Pointer message, steps S63 and S64 are skipped and the process proceeds to step S65. Also,
When it is determined in step S62 that the message received in step S61 is the Save Data Pointer message, the process proceeds to step S63, and the data transferred from the peripheral device 3 to the computer 1 via the conversion interface 2 is stored. The address of the RAM 13 (when data is being transferred, the address of the RAM 13 where the transferred data is stored) is stored (saved) in a predetermined storage area of the RAM 13.

Peripheral device 3, as described in FIG.
After sending the ve Data Pointer message, Disconnect
Since the message is transmitted, the computer 1 waits for the message to be transmitted as a packet (a packet of the SCSI message) from the conversion interface 2 (FIG. 12 (10)), and is received at step S64. (It is captured).

Then, in step S65, it is determined whether or not the received message is a Disconnect message. When it is determined in step S65 that the received message is not the Disconnect message, steps S66 to S70 are skipped and the process proceeds to step S71. If it is determined in step S65 that the received message is the Disconnect message, the process proceeds to step S66, and the conversion interface 2 is instructed to temporarily disconnect the connection with the peripheral device 3 (connection A packet of a converter command (FIG. 3) for instructing to turn off is transmitted from the computer 1 to the conversion interface 2 (see FIG.
1)).

Then, the process proceeds to step S67, another process (work) is performed, and it is determined in step S68 whether the conversion interface 2 has been reselected by the peripheral device 3.

Here, the conversion interface 2 (SCS
After the connection with the peripheral device 3 is once disconnected by the I controller 25), the phase is set to the arbitration phase by the peripheral device 3 as described with reference to FIG. When the usage right is acquired, the reselection phase is entered. In the reselection phase, the peripheral device 3 designates (reselects or reconnects) the conversion interface 2 (SCSI controller 25), and when the conversion interface 2 is reselected, the SC indicates the fact.
A packet of an SI message (for example, a SCSI message having the content of reconnection from the target of ID number X (where X is the ID number of the peripheral device 3)) is transmitted to the computer 1 (FIG. 12 (12)). . In step S68, the packet of this SCSI message is
When received by the computer 1, it is determined that the conversion interface 2 has been reselected by the peripheral device 3.

When it is determined in step S68 that the conversion interface 2 has not been reselected by the peripheral device 3, the process returns to step S67. That is, the computer 1 performs other processing (operation) until the conversion interface 2 is reselected by the peripheral device 3.

When it is determined in step S68 that the conversion interface 2 has been reselected by the peripheral device 3, the process proceeds to step S69.

Here, as described with reference to FIG. 2, in the reselection phase, the peripheral device 3 reselects the conversion interface 2 (SCSI controller 25) and then shifts the phase to the message in phase. In this message in phase, the message (Id
Since the entify message) is transmitted from the peripheral device 3 to the conversion interface 2 (SCSI controller 25), the message is converted into a packet (a SCSI message packet) and transmitted from the conversion interface 2 in the computer 1. (Fig. 12 (1
3)), and is received (acquired) in step S69.

Then, in step S70, it is determined whether the message received in step S69 is an Identify message. In step S70,
When the message received in step S69 is determined to be the Identify message, step S in FIG.
Return to 52.

If it is determined in step S70 that the message received in step S69 is not the Identify message, the process proceeds to step S71 and the message (here, steps S61, S64, or S
It is determined whether the message received at 69) is a Command Complete message. When it is determined in step S71 that the message is the Command Complete message, that is, the Command Complete message indicating that the data transfer is completed is transmitted from the peripheral device 3 to the computer 1 via the conversion interface 2. If (FIG. 12 (16)), step S7
Go to 2 and convert interface from computer 1 to interface 2
Is instructed to disconnect the connection between the SCSI controller 25 and the peripheral device 3 (the SCSI controller 25
A packet of a converter command (FIG. 3) instructing disconnection between the computer and the peripheral device 3 is transmitted from the computer 1 to the conversion interface 2) (FIG. 12 (17)).

When it is determined in step S71 that the message is not the Command Complete message, the process proceeds to step S73, a predetermined error process is performed, and the process ends.

Returning to FIG. 13, in step S53,
When it is determined that the phase is the data-in phase, as described in FIG. 2, in the data-in phase,
The data read from the peripheral device 3 is transmitted to the conversion interface 2 (SCSI controller 25), and the data is further converted into a packet (a packet of SCSI data) and transmitted from the conversion interface 2. 12 (14)), step S81 in FIG.
Address (storage position) of the RAM 13 for storing the data (in step S63 of FIG. 14, the RAM 13 is stored).
(The address stored in) is updated (for example, the address is incremented by 1).

Then, in step S82, the SCSI data transmitted from the conversion interface 2 is received (read), the process proceeds to step S83, and the data is stored (stored) in the address updated in step S81. .

After that, the process proceeds to step S84, the SCSI
It is determined whether the phase of the bus has changed. When it is determined in step S84 that the phase has not changed, the process returns to step S53 of FIG. 13, the changed phase is determined as described above, and the process is performed according to the determination result.

If it is determined in step S84 that the phase has changed, then the flow proceeds to step S85,
It is determined whether or not the required amount of data has been received (read) from the peripheral device 3 via the conversion interface 2. If it is determined in step S85 that the necessary amount of data has been received from the peripheral device 3,
That is, when all the data to be read from the peripheral device 3 is transferred to the computer 1 via the conversion interface 2, the process returns to step S52 of FIG. If it is determined in step S85 that the necessary amount of data has not been received from the peripheral device 3, the process returns to step S81.

Here, in step S85, it is determined that the necessary amount of data has been received from the peripheral device 3,
After returning to step S52 of FIG. 13, the following steps S53, S74, S75, S52, S53, S61, and S are performed.
The process is performed in the order of 62, S65, S71, S72 (provided that the computer 1, the conversion interface 2, and the peripheral device 3 operate normally).

On the other hand, if it is determined in step S53 (FIG. 13) that the phase is the status phase, the process proceeds to step S74 in FIG. 14 and, as described with reference to FIG. From peripheral device 3 to conversion interface 2 (SCSI
Since it is sent to the controller 25), it is sent as a packet (packet with SCSI status) from the conversion interface 2 (see FIG. 12 (1
5)) is received (received).

Then, the process proceeds to step S75, and it is determined whether or not the packet received in step S74 indicates the Good status. When it is determined in step S75 that the packet indicates the Good status, the process returns to step S52 in FIG. Also,
When it is determined in step S75 that the packet does not indicate the Good status, the process proceeds to step S73, a predetermined error process is performed, and the process ends.

On the other hand, in step S53 of FIG.
When it is determined that the phase is a phase (other phase) other than the message-in phase, the data-in phase, and the status phase, the process proceeds to step S73 in FIG. 14, a predetermined error process is performed, and the process ends. To do.

As described above, in the computer system shown in FIG. 1, even if the computer 1 has only a high-speed serial bus, the conversion interface 2 allows the various types of SCSI to be processed in accordance with the SCSI control procedure. It becomes possible to communicate with the device at high speed.

In this embodiment, the RAM 23
A storage area as a reception buffer, a transmission buffer, and a packet queue is secured in the RAM 13 (similarly). However, when data is sequentially stored in the reception buffer, the head of a packet composed of the data or By remembering the end position, R
It is not necessary to secure a storage area as a packet queue in the AM 23.

[0154]

As described above, according to the present invention, high-speed communication can be performed between an information processing device having a high-speed serial bus and a peripheral device having a SCSI bus. Further, it is possible to prevent the information processing device from becoming large.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a computer system to which the present invention is applied.

FIG. 2 is a diagram illustrating a SCSI control procedure.

FIG. 3 is a diagram illustrating a format of a packet transmitted from the computer 1 of FIG. 1 to a conversion interface 2.

4 is a diagram illustrating a format of a packet transmitted from the conversion interface 2 of FIG. 1 to the computer 1.

5 is a flowchart illustrating an operation of the computer 1 of FIG.

FIG. 6 is a flowchart illustrating an interrupt process in the computer 1 of FIG.

FIG. 7 is a flowchart illustrating more details of step S12 of FIG.

8 is a flowchart illustrating an operation of the conversion interface 2 of FIG.

9 is a flowchart illustrating more details of step S102 of FIG.

10 is a flowchart illustrating more details of step S104 in FIG.

11 is a flowchart illustrating a reception interrupt process in the conversion interface 2 of FIG.

FIG. 12 is a diagram showing the exchange of packets between the computer 1 and the conversion interface 2 of FIG.

13 is a flowchart illustrating the operation of the computer 1 shown in FIG. 12 when packets are exchanged.

14 is a flowchart following the flowchart of FIG.

FIG. 15 is a flowchart following the flowchart of FIG.

[Explanation of symbols]

 1 Computer 2 Conversion Interface 3 Peripheral Device 11 CPU 12 ROM 13 RAM 14 Serial Controller 21 CPU 22 ROM 23 RAM 24 Serial Controller 25 SCSI Controller

Claims (3)

[Claims] 1. An information processing apparatus having a high-speed serial bus and a SCSI (Small Computer System Interface)
A communication interface that is connected to a peripheral device having a bus and that controls communication between the peripheral device and a serial bus communication unit that communicates with the information processing device via the serial bus; and via the SCSI bus. And a SCSI bus communication unit that communicates with the peripheral device, and controls the SCSI bus communication unit in response to the data from the information processing device received by the serial bus communication unit. Corresponding to the data from the peripheral device received by the means,
A communication interface comprising: a control unit that controls the serial bus communication unit. 2. The information processing apparatus inquires of the control means via the serial bus communication means about the phase of the SCSI bus state, and in accordance with the response to the inquiry, the serial bus communication means In response to an inquiry about the phase from the information processing device, the control unit causes the SCSI bus communication unit to check the phase, and the information processing is performed via the serial bus communication unit. The communication interface according to claim 1, wherein the communication interface notifies a device. 3. The communication interface according to claim 1, wherein the information processing device and the serial bus communication unit perform communication in conformity with the RS232C or RS422 standard.